A Configuration EPROMs for FLEX 8000 Devices August 1993, ver. 2 Features Functional Description Data Sheet | Family of serial EPROMs designed to configure FLEX 8000 devices Available in compact, one-time programmable (OTP) 8-pin plastic dual in-line (PDIP) and 20-pin plastic J-lead chip carrier (PLCC) packages (see Figure 1); 32-pin thin quad flat pack (TOFP) packages under development Simple 4-wire interface to FLEX 8000 devices for ease of use Low current during configuration (15 mA) and near-zero standby current (100 A) ) Software design support with Alteras MAX+PLUS II development system for IBM PC, Sun SPARCstation, and HP 9000 Series 700 platforms . G1 Programming support with Alteras Master Programming Unit (MPU) and programming hardware from other manufacturers, including Data 1/O ov coo In SRAM-based devices, configuration data must be reloaded each time the system initializes, or whenever new configuration data is desired. Alteras serial-memory Configuration EPROMs store configuration data for the SRAM-based Altera FLEX 8000 devices. Figure 1. Configuration EPROM Package Pin-Out Diagrams Package outlines not drawn to scale. 9 2 DCLK N.C. N.C. N.C. OE EPCxxxx 1 10 12 RAG g2 ncasc 8-Pin DIP 20-Pin J-Lead LJ VCC EI N.C. Fy N.C. N.C. N.C. Table 1 shows the size of each Altera Configuration EPROM and indicates which FLEX 8000 device is typically configured by each. | Altera Corporation COPYRIGHT ASPECT DEVELOPMENT, INC. 1994. Page 341 ALTEDOOt ma) co = oa = o J p 4) =) 2) io) es oOConfiguration EPROMs for FLEX 8000 Devices Data Sheet Table 1. Typical Application for Altera Configuration EPROMs Device Device Size Typical FLEX 8000 Device Configured EPC1064 65,536 x 1 bit EPF8282, EPF8282V, EPF8452 EPC1213 212,992 x 1 bit EPF8820, EPF81188 Figure 2 shows a block diagram of the Configuration EPROM. Configuration data is stored in the EPROM array and clocked out serially by the DCLK input. The Output Enable (OE), Chip-Select (ncs), and Clock (DCLK) pins supply the control signals for the address counter and the output tri-state. The device presents the configuration data as a serial bit stream on the DATA pin. This data is routed into the FLEX 8000 device via the DATAO input pin. The ncasc pin provides handshaking between multiple Configuration EPROMs, so that a set of devices can be linked together to serially configure a large FLEX 8000 device. Refer to the FLEX 8000 Programmable Logic Device Family Data Sheet and Application Note 33 (Configuring FLEX 8000 Devices) in this data book for more information on FLEX architecture and configuration. Figure 2. Configuration EPROM Functional Block Diagram > Address DCLK [> i Counter 1 > Control ncS [> p| Logic -K> nCASC OE C> > Y EPROM Array VVVVVVVY | Shift Register DATA The control signals for Configuration EPROMs (DCLK, nCs, OF) interface directly to the FLEX 8000 device control signals. A FLEX 8000 device can control the entire configuration process by retrieving the configuration data from the Configuration EPROM without an external intelligent controller. Configuration usually occurs automatically at system power- up. The OF and nCs pins work together to control the tri-state buffer on the DATA output pin, and to enable the address counter in the Configuration EPROM. When OE is driven low, the device resets the address counter and tri-states the DATA pin. When the OE pin is driven high again, the device is Page 342 Altera Corporation | COPYRIGHT ASPECT DEVELOPMENT, INC. 1994. ALTEDOOtData Sheet Configuration EPROMs for FLEX 8000 Devices controlled by the ncs pin. If ncs is held high after the OE reset pulse, the counter is disabled, and the DATA output pin is tri-stated. When ncs is driven low, the counter is enabled and the DATA output pin is enabled. The ncs pin can then be held either high or low to control the output and counter. When OE is driven low again, regardless of the state of nCs, the address counter is reset and the DATA output pin is tri-stated. Upon power- up, the address counter is automatically reset. Table 2 describes the pin functions of Altera Configuration EPROMs. Table 2. Configuration EPROM Pin Functions Pin Name | 8-Pin PDIP | 20-Pin PLCC | Pin Type Description Pin Number | Pin Number DATA 1 Output | Serial data output. DCLK 2 Input Clock input. Rising edges on DCLK increment the internal address counter and cause the next bit of data to be presented on DATA. The counter is incremented only if the OF input is held high and the ncs input is held low. OE 3 8 Input Output Enable (active high) and Reset (active low). A low logic level resets the address counter. A high logic level enables DATA and permits the address counter to count. ncs 4 9 Input Chip-Select output (active low). A low input allows DCLK to increment the address counter and enables DATA. nCASC 6 12 Output | Cascade-Select output (active low). This output goes low when the address counter has reached its maximum value. nCASC is usually connected to the ncs input of the next Configuration EPROM ina daisy-chain, so the next DCLK clocks data out of the next Configuration EPROM. GND 5 10 Ground |A0.2-uF decoupling capacitor must be placed between the vcc and GND pins. vec 7,8 18, 20 Power | Power pin Single-Device The active serial (AS) configuration scheme uses a serial Configuration . . EPROM (e.g., EPC1213) as a data source for a FLEX 8000 device. The Conti gu ration Configuration EPROM presents its data to the FLEX 8000 device in a serial bit-stream. Figure 3 shows a typical circuit in which the FLEX 8000 device controls the configuration process and uses a serial Configuration EPROM as the data source. For additional information, refer to Application Note 33 (Configuring FLEX 8000 Devices). | Altera Corporation COPYRIGHT ASPECT DEVELOPMENT, INC. 1994. Page 343 ALTEDOO1 nm co = o ial o I 4 ua cw o = oConfiguration EPROMs for FLEX 8000 Devices Data Sheet Figure 3. Active Serial Configuration FLEX 8000 o" pl ns vec Configuration 0 MSELO 1.0kQ EPROM 0 | MSEL1 , CONF_DONE nes vec vec 7 1.0 kQ nSTATUS BP) NCONFIG DATAO }_ DATA DCLK >| OE DCLK The ncOnF IG pin on the FLEX 8000 device in Figure 3 is connected to Vcc, so the device automatically configures itself at system power-up. The system can monitor the nSTATUS pin to ensure that configuration occurs correctly. Immediately after power-up, the FLEX 8000 device pulls the nSTATUS pin low and releases it within 100 ms. Once released, the open- drain nSTATUS pin is pulled up to Vcc by an external 1.0-kQ pull-up resistor. If an error occurs during configuration, the FLEX 8000 device pulls the nSTATUS pin low, indicating that configuration was unsuccessful. The DCLX signal, which is driven by the FLEX 8000 device, clocks sequential data bits from the Configuration EPROM. While the SRAM data is being loaded, the FLEX 8000 device holds the open-drain CONF_DONE pin at GND, indicating that data is loading. A 24-bit program-length counter within the FLEX 8000 device stores the program length, ie., the total number of configuration bits. Once the terminal count value for the configuration data (i.e., the last configuration data bit) has been reached, the FLEX 8000 device releases the CONF_DONE pin, which is subsequently pulled up to Vec by an external 1.0-kQ pull-up resistor. The resulting high input on the nCs pin causes the Configuration EPROM to tri-state its DATA output, electrically removing the Configuration EPROM from the circuit. After it releases the CONF_DONE pin, the FLEX 8000 device uses it as an input for monitoring the configuration process. When the FLEX 8000 device senses a high logic level on CONF__DONE, it completes the initialization process and enters user mode. Figure 4 shows the timing associated with the AS configuration process and the order of transitions on the control signals. Worst-case values for the timing parameters shown in Figure 4 are given in the Timing Parameters table later in this data sheet. | Page 344 Altera Corporation COPYRIGHT ASPECT DEVELOPMENT, INC. 1994. ALTEDOO1| Data Sheet Configuration EPROMs for FLEX 8000 Devices Figure 4. Single-Device Configuration Timing Waveforms nCS /CONF_DONE DCLK DATA loss: lesxz tosu In the circuit shown in Figure 3, the nCONFIG pin on the FLEX 8000 device is tied to the Output Enable (OE) input of the Configuration EPROM; both are tied to Vec. A high logic level on the nCONFIG input automatically starts the configuration. The output of the serial Configuration EPROM is enabled by a high input on its OE pin. If an error occurs during circuit configuration, the FLEX 8000 device pulls and holds the nSTATUS pin low, indicating a configuration error. External circuitry is used to monitor the nSTATUS pin and take appropriate action if configuration fails. This circuitry must assert a high-low-high pulse on the nCONFIG pin to reconfigure the device after the error. The same circuitry can also be used to begin reconfiguring the FLEX 8000 device at any time after system power-up. al ot | i) _ o bon p a a=] 37) i] = io) The FLEX 8000 device's built-in Auto-Restart Configuration on Frame Error option bit allows the device to automatically reconfigure itself if it encounters an error during configuration. If this option bit is turned on, a configuration error causes the FLEX 8000 device to pull the nSTATUS pin low for 10 internal Clock cycles and then release it. This 1- to 3-us pulse on the nSTATUS pin provides an external indication that reconfiguration is about to begin. It also can be used to reset the Altera Configuration EPROM. Figure 5 shows a circuit that uses the Auto-Restart Configuration on Frame Error option. The nSTATUS pin is connected to the OE input on the Altera Configuration EPROM so that the error-reset pulse on nSTATUS resets the internal address counter on the Configuration EPROM and prepares it to reconfigure the FLEX 8000 device. The nCONFIG input is also available to initiate a reconfiguration cycle externally. Since the nSTATUS pin is pulled low and then released whenever configuration begins, it resets the Configuration EPROM before reconfiguration. During device operation, if Vec drops below the power-on reset (POR) threshold for the FLEX 8000 device, nSTATUS is pulsed and the Configuration EPROM is reset in the same way to provide automatic reconfiguration. Timing for the circuit in Figure 5 is identical to the timing shown in Figure 4 for the AS configuration scheme (the error-reset pulse on nSTATUS is not shown). | Altera Corporation Page 345 COPYRIGHT ASPECT DEVELOPMENT, INC. 1994. ALTEDOO1Configuration EPROMs for FLEX 8000 Devices Data Sheet Figure 5. Active Serial Device Configuration with Automatic Reconfiguration on Error FLEX 8000 io PB) nsip vec Configuration 0 _ >| MSELO , 1.0kQ EPROM 0 } | MSEL1 CONF_DONE acs voc voc 10 Ko | <q nSTATUS P| nCONFIG DATAO |} DATA DCLK OE DOLK MAX+PLUS Il The MAX+PLUS ll development system provides programming support for Altera Configuration EPROMs. MAX+PLUS II software automatically Su pport generates a Programmer Object File (.pof) for every FLEX 8000 device ina project. By default, each FLEX 8000 device in a multi-device project has a dedicated serial Configuration EPROM. MAX+PLUS II selects the appropriate Configuration EPROM to most efficiently store the data for each FLEX 8000 device. The POF includes a preamble, cyclic redundancy check (CRC), and synchronization data that allow it to be used in a serial bitstream. The POF is programmed into the Configuration EPROM with MAX+PLUS II and a Configuration EPROM programming adapter. A number of other programming hardware manufacturers, including Data I/O, support programming of Configuration EPROMs. See the Altera Programming Hardware and Programming Hardware Manufacturers data sheets in this data book. Page 346 Altera Corporation COPYRIGHT ASPECT DEVELOPMENT, INC. 1994. ALTEDOOt| Data Sheet Absolute Maximum Ratings Configuration EPROMs for FLEX 8000 Devices See Operating Requirements for Altera Devices in this data book. Symbol Parameter Conditions Min Max | Unit Voc Supply voltage With respect to GND -2.0 7.0 Vv Vv) DC input voltage Note (1) -2.0 7.0 Vv bax DC Voc or GND current 20 lout DC output current, per pin 25 25 Pp Power dissipation 100 Tstg Storage temperature No bias -65 150 T AMB Ambient temperature Under bias -65 135 Ty Junction temperature Under bias 150 Recommended Operating Conditions Symbol Parameter Conditions Min Max Voc Supply voltage With respect to GND 4.75 5.25 v\ Input voitage Note (1) 0 Voc Vo Output voltage 0 Voc Ta Operating temperature For commercial use 0 70 Ta Operating temperature For industrial use 40 85 To Case temperature For military use -55 125 ta Input rise time 20 ns te Input fall time 20 ns DC Operating Conditions Notes (2), (3) Symbol Parameter Conditions Min Max | Unit Von High-level input voltage 2.0 Veco + 0.3] V Vie Low-level input voltage 0.3 0.8 V Vou High-level TTL output voltage loH = 4mADC 2.4 Vv Voi Low-level output voltage lo. = 4mADC 0.45 Vv 1, Input leakage current Vi =Voc or GND -10 10 HA loz Tri-state output off-state current Vo =Vcc or GND -10 10 pA Supply Current Symbol Parameter Conditions Min Typ Max | Unit loco Voc Supply current (standby) 100 HA loci Voc supply current DCLK = 8 MHz 10 mA (during configuration) | Altera Corporation Page 347 ALTEDO01 COPYRIGHT ASPECT DEVELOPMENT, INC. 1994. iu o = oa anes = | 5 J J 3)| Configuration EPROMs for FLEX 8000 Devices Data Sheet Capacitance Note (4) Symbol Parameter Conditions Min Max | Unit Cin Input capacitance Vin = OV,f = 1.0 MHz 10 pF Court | Output capacitance Vout = OV, f = 1.0 MHz 10 pF Timing Parameters Symbol Parameter Conditions Min | Max | Unit toezx _| OF high to DATA output enabled 50 ns teszx | nCS low toDATA output enabled 50 ns tesxz | ncs high to DATA output disabled 50 ns tess ncs low setup time to first DCLK rising edge 100 ns tosH ncs low hold time after DcLK rising edge 0 ns tpsu Data setup time before rising edge on DCLK 50 ns ton Data hold time after rising edge on DCLK 0 ns too DCLK to DATA out delay, Note (5) : 75 ns tex Clock period 160 ns fox Clock frequency 6 MHz tet DCLK low time 80 ns ton DCLK high time 80 ns tyz OE low orncs high to DATA output disabled 50 ns toew OE pulse width to guarantee counter reset 100 ns tcasc _| Last DCLK + 1 toncasc low delay 60 ns texxz _ | Last DCLK + 1 toDATA tri-state delay 50 ns tegout | ncs high toncasc high delay 100 ns Notes to tables: (1) Minimum DC input is -0.3 V. During transitions, the inputs may undershoot to -2.0 V or overshoot to 7.0 V for periods shorter than 20 ns under no-load conditions. (2) Typical values are for Ty = 25 C and Voc = 5.0 V. (3) Operating conditions: Vcc = 5.0 V + 5%, T, = 0 C to 70 C for commercial use. (4) Capacitance is sample-tested only. (5) Eight Clock cycles are required after the tegg setup time has been met to clock out the first eight bits. These bits are all high and are used to synchronize the configuration process. The ninth Clock cycle presents the first configuration data bit. Product Product Grade Availability Availability Commercial Temp. (0 C to 70 C) EPC1213, EPC1064 Industrial Temp. (40 C to 85 C) Consult factory Military Temp. (-55 C to 125 C) Consult factory Pa ckage See the Package Outlines Data Sheet in this data book for dimensions of the . Configuration EPROM 8-pin PDIP and 20-pin PLCC packages. For package Outlines outlines of the 32-pin TQFP Configuration EPROM, contact Altera Applications at (800) 800-EPLD. | Page 348 Altera Corporation | COPYRIGHT ASPECT DEVELOPMENT, INC. 1994. ALTEDOO1