DATASHEET 9ZX21901C 19-Output Differential Zbuffer for PCIe Gen2/3 and QPI Description Features/Benefits The 9ZX21901 is Intel DB1900Z Differential Buffer suitable for PCI- * Express Gen3 or QPI applications. The part is backwards compatible * to PCIe Gen1 and Gen2. A fixed external feedback maintains low drift for critical QPI applications. In bypass mode, the 9ZX21901 * can provide outputs up to 400MHz. * Recommended Application * 19 output PCIe Gen3/QPI buffer with fixed feedback for Romley platforms * Output Features * * * * 19 - 0.7V current mode differential HCSL output pairs Fixed feedback path/ 0ps input-to-output delay 9 Selectable SMBus addresses/ Multiple devices can share same SMBus segment 8 dedicated OE# pins/ hardware control of outputs PLL or bypass mode/ PLL can dejitter incoming clock Selectable PLL BW/ minimizes jitter peaking in downstream PLL's Spread spectrum compatible/tracks spreading input clock for EMI reduction SMBus Interface/ unused outputs can be disabled 100MHz & 133.33MHz PLL mode/ Legacy QPI support Undriven differential outputs in Power Down mode for maximum power savings Key Specifications * * * * * * Cycle-to-cycle jitter: < 50ps Output-to-output skew: <65ps Input-to-output delay: Fixed at 0 ps Input-to-output delay variation: <50ps Phase jitter: PCIe Gen3 < 1ps rms Phase jitter: QPI 9.6GB/s < 0.2ps rms Functional Block Diagram OE(5_12)# 8 DFB_OUT Z-PLL (SS Compatible) DIF_IN DIF_IN# HIBW_BYPM_LOBW# 100M_133M# CKPWRGD/PD# SMB_A0_tri SMB_A1_tri DIF(18:0) Logic SMBDAT SMBCLK IREF Note: Even though the feedback is fixed, DFB_OUT still needs a termination network for the part to function. IDT(R) 19-Output Differential Zbuffer for PCIe Gen2/3 and QPI 1648H - 12/08/11 1 9ZX21901C 19-Output Differential Zbuffer for PCIe Gen2/3 and QPI DIF_12 DIF_12# OE12# VDD DIF_13 DIF_13# DIF_14 DIF_14# GND DIF_15 DIF_15# DIF_16 DIF_16# VDD DIF_17 DIF_17# DIF_18 DIF_18# Pin Configuration 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 OE11# 53 DIF_11# VDDA 1 GNDA 2 52 DIF_11 51 OE10# IREF 3 100M_133M# 4 50 DIF_10# 49 DIF_10 HIBW_BYPM_LOBW# 5 CKPWRGD_PD# 6 48 OE9# 47 DIF_9# GND 7 VDDR 8 9ZX21901C 46 DIF_9 NOTE: DFB_OUT pins must be terminated identically DIF_IN# 10 45 VDD to the regular DIF outputs GND DIF_IN 9 SMB_A0_tri 11 44 43 OE8# 42 DIF_8# SMBDAT 12 SMBCLK 13 41 DIF_8 40 OE7# SMB_A1_tri 14 NC 15 NC 16 39 DIF_7# 38 DIF_7 DFB_OUT# 17 37 OE6# DFB_OUT 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 DIF_6# DIF_6 OE5# DIF_5# DIF_5 VDD DIF_4# DIF_4 DIF_3# DIF_3 GND DIF_2# DIF_2 DIF_1# DIF_1 VDD DIF_0# DIF_0 72-pin MLF Functionality at Power Up (PLL Mode) DIF_IN 100M_133M# (MHz) 1 100.00 0 133.33 DIF (MHz) DIF_IN DIF_IN PLL Operating Mode Readback Table HiBW_BypM_LoBW# Byte0, bit 7 Low (Low BW) 0 Mid (Bypass) 0 High (High BW) 1 Byte 0, bit 6 0 1 1 PLL Operating Mode HiBW_BypM_LoBW# Low Power Connections Pin Number VDD 1 8 21, 31, 45, 58, 68 Description GND 2 7 Analog PLL Analog Input 26, 44, 63 DIF clocks 9ZX21901 SMBus Addressing Pin SMBus Address SMB_A1_tri SMB_A0_tri (Rd/Wrt bit = 0) 0 D8 0 0 M DA 1 0 DE M 0 C2 M C4 M 1 M C6 0 1 CA M 1 CC 1 1 CE MODE PLL Lo BW Mid Bypass High PLL Hi BW NOTE: PLL is OFF in Bypass Mode Tri-level Input Thresholds Level Voltage <0.8V Low Mid 1.2<Vin<1.8V High Vin > 2.2V IDT(R) 19-Output Differential Zbuffer for PCIe Gen2/3 and QPI 1648H- 12/08/11 2 9ZX21901C 19-Output Differential Zbuffer for PCIe Gen2/3 and QPI Pin Description PIN # 1 2 PIN NAME VDDA GNDA PIN TYPE PWR PWR 3 IREF OUT 4 100M_133M# IN 5 HIBW_BYPM_LOBW# IN 6 CKPWRGD_PD# IN 7 GND PWR 8 VDDR PWR 9 10 DIF_IN DIF_IN# IN IN 11 SMB_A0_tri IN 12 13 SMBDAT SMBCLK I/O IN 14 SMB_A1_tri IN 15 16 NC NC N/A N/A 17 DFB_OUT# OUT 18 DFB_OUT OUT 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 DIF_0 DIF_0# VDD DIF_1 DIF_1# DIF_2 DIF_2# GND DIF_3 DIF_3# DIF_4 DIF_4# VDD DIF_5 DIF_5# OUT OUT PWR OUT OUT OUT OUT PWR OUT OUT OUT OUT PWR OUT OUT 34 OE5# 35 36 DIF_6 DIF_6# IN OUT OUT DESCRIPTION 3.3V power for the PLL core. Ground pin for the PLL core. This pin establishes the reference for the differential current-mode output pairs. It requires a fixed precision resistor to ground. 475ohm is the standard value for 100ohm differential impedance. Other impedances require different values. See data sheet. Input to select operating frequency 1 = 100MHz, 0 = 133.33MHz Trilevel input to select High BW, Bypass or Low BW mode. See PLL Operating Mode Table for Details. Notifies device to sample latched inputs and start up on first high assertion, or exit Power Down Mode on subsequent assertions. Low enters Power Down Mode. Ground pin. 3.3V power for differential input clock (receiver). This VDD should be treated as an analog power rail and filtered appropriately. 0.7 V Differential TRUE input 0.7 V Differential Complementary Input SMBus address bit. This is a tri-level input that works in conjunction with the SMB_A1 to decode 1 of 9 SMBus Addresses. Data pin of SMBUS circuitry, 5V tolerant Clock pin of SMBUS circuitry, 5V tolerant SMBus address bit. This is a tri-level input that works in conjunction with the SMB_A0 to decode 1 of 9 SMBus Addresses. No Connection. No Connection. Complementary half of differential feedback output, provides feedback signal to the PLL for synchronization with input clock to eliminate phase error. True half of differential feedback output, provides feedback signal to the PLL for synchronization with the input clock to eliminate phase error. 0.7V differential true clock output 0.7V differential Complementary clock output Power supply, nominal 3.3V 0.7V differential true clock output 0.7V differential Complementary clock output 0.7V differential true clock output 0.7V differential Complementary clock output Ground pin. 0.7V differential true clock output 0.7V differential Complementary clock output 0.7V differential true clock output 0.7V differential Complementary clock output Power supply, nominal 3.3V 0.7V differential true clock output 0.7V differential Complementary clock output Active low input for enabling DIF pair 5. 1 =disable outputs, 0 = enable outputs 0.7V differential true clock output 0.7V differential Complementary clock output IDT(R) 19-Output Differential Zbuffer for PCIe Gen2/3 and QPI 1648H- 12/08/11 3 9ZX21901C 19-Output Differential Zbuffer for PCIe Gen2/3 and QPI Pin Description (continued) PIN # PIN NAME 37 OE6# 38 39 DIF_7 DIF_7# 40 OE7# 41 42 DIF_8 DIF_8# 43 OE8# 44 45 46 47 GND VDD DIF_9 DIF_9# 48 OE9# 49 50 DIF_10 DIF_10# 51 OE10# 52 53 DIF_11 DIF_11# 54 OE11# 55 56 DIF_12 DIF_12# 57 OE12# 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 VDD DIF_13 DIF_13# DIF_14 DIF_14# GND DIF_15 DIF_15# DIF_16 DIF_16# VDD DIF_17 DIF_17# DIF_18 DIF_18# PIN TYPE IN OUT OUT IN OUT OUT IN PWR PWR OUT OUT IN OUT OUT IN OUT OUT IN OUT OUT IN PWR OUT OUT OUT OUT PWR OUT OUT OUT OUT PWR OUT OUT OUT OUT DESCRIPTION Active low input for enabling DIF pair 6. 1 =disable outputs, 0 = enable outputs 0.7V differential true clock output 0.7V differential Complementary clock output Active low input for enabling DIF pair 7. 1 =disable outputs, 0 = enable outputs 0.7V differential true clock output 0.7V differential Complementary clock output Active low input for enabling DIF pair 8. 1 =disable outputs, 0 = enable outputs Ground pin. Power supply, nominal 3.3V 0.7V differential true clock output 0.7V differential Complementary clock output Active low input for enabling DIF pair 9. 1 =disable outputs, 0 = enable outputs 0.7V differential true clock output 0.7V differential Complementary clock output Active low input for enabling DIF pair 10. 1 =disable outputs, 0 = enable outputs 0.7V differential true clock output 0.7V differential Complementary clock output Active low input for enabling DIF pair 11. 1 =disable outputs, 0 = enable outputs 0.7V differential true clock output 0.7V differential Complementary clock output Active low input for enabling DIF pair 12. 1 =disable outputs, 0 = enable outputs Power supply, nominal 3.3V 0.7V differential true clock output 0.7V differential Complementary clock output 0.7V differential true clock output 0.7V differential Complementary clock output Ground pin. 0.7V differential true clock output 0.7V differential Complementary clock output 0.7V differential true clock output 0.7V differential Complementary clock output Power supply, nominal 3.3V 0.7V differential true clock output 0.7V differential Complementary clock output 0.7V differential true clock output 0.7V differential Complementary clock output IDT(R) 19-Output Differential Zbuffer for PCIe Gen2/3 and QPI 1648H- 12/08/11 4 9ZX21901C 19-Output Differential Zbuffer for PCIe Gen2/3 and QPI Electrical Characteristics - Absolute Maximum Ratings PARAMETER SYMBOL 3.3V Core Supply Voltage 3.3V Logic Supply Voltage Input Low Voltage Input High Voltage Input High Voltage VDDA VDD VIL VIH VIHSMB Storage Temperature Junction Temperature Case Temperature Input ESD protection Ts Tj Tc ESD prot CONDITIONS MIN TYP UNITS NOTES MAX 4.6 4.6 GND-0.5 Except for SMBus interface SMBus clock and data pins V DD+0.5V 5.5V -65 Human Body Model V V V V V 1,2 1,2 1 1 1 1 1 1 1 C C C V 150 125 110 2000 1 Guaranteed by design and characterization, not 100% tested in production. 2 Operation under these conditions is neither implied nor guaranteed. Electrical Characteristics - Input/Supply/Common Parameters TA = TCOM; Supply Voltage VDD/VDDA = 3.3 V +/-5%, See Test Loads for Loading Conditions PARAMETER SYMBOL CONDITIONS MIN Ambient Operating Temperature TCOM Commmercial range 0 70 C 1 Input High Voltage VIH 2 VDD + 0.3 V 1 Input Low Voltage VIL GND - 0.3 0.8 V 1 I IN Input Current Input Frequency Pin Inductance Capacitance IINP Fibyp Fipll Fipll Lpin CIN CINDIF_IN COUT Single-ended inputs, except SMBus, low threshold and tri-level inputs Single-ended inputs, except SMBus, low threshold and tri-level inputs Single-ended inputs, VIN = GND, VIN = VDD TYP MAX UNITS NOTES -5 5 uA 1 Single-ended inputs VIN = 0 V; Inputs with internal pull-up resistors VIN = VDD; Inputs with internal pull-down resistors -200 200 uA 1 VDD = 3.3 V, Bypass mode VDD = 3.3 V, 100MHz PLL mode VDD = 3.3 V, 133.33MHz PLL mode 33 90 120 Logic Inputs, except DIF_IN DIF_IN differential clock inputs 1.5 1.5 400 105 140 7 5 2.7 MHz MHz MHz nH pF pF 2 2 2 1 1 1,4 6 pF 1 1.8 ms 1,2 30 33 kHz 1 1 3 cycles 1,3 300 us 1,3 5 5 0.8 5.5 1000 300 ns ns V V V mA V ns ns 1,2 1,2 1 1 1 1 1 1 1 100 kHz 1,5 Output pin capacitance Clk Stabilization TSTAB Input SS Modulation Frequency f MODIN OE# Latency t LATOE# Tdrive_PD# t DRVPD Tfall Trise SMBus Input Low Voltage SMBus Input High Voltage SMBus Output Low Voltage SMBus Sink Current Nominal Bus Voltage SCLK/SDATA Rise Time SCLK/SDATA Fall Time SMBus Operating Frequency tF tR From VDD Power-Up and after input clock stabilization or de-assertion of PD# to 1st clock Allowable Frequency (Triangular Modulation) DIF start after OE# assertion DIF stop after OE# deassertion DIF output enable after PD# de-assertion Fall time of control inputs Rise time of control inputs VILSMB VIHSMB VOLSMB I PULLUP VDDSMB tRSMB t FSMB @ I PULLUP @ VOL 3V to 5V +/- 10% (Max VIL - 0.15) to (Min VIH + 0.15) (Min VIH + 0.15) to (Max VIL - 0.15) f MAXSMB Maximum SMBus operating frequency 2.1 4 2.7 100.00 133.33 VDDSMB 0.4 1 Guaranteed by design and characterization, not 100% tested in production. Control input must be monotonic from 20% to 80% of input swing. 3 Time from deassertion until outputs are >200 mV 4 DIF_IN input 2 5 The differential input clock must be running for the SMBus to be active IDT(R) 19-Output Differential Zbuffer for PCIe Gen2/3 and QPI 1648H- 12/08/11 5 9ZX21901C 19-Output Differential Zbuffer for PCIe Gen2/3 and QPI Electrical Characteristics - Clock Input Parameters TA = TCOM; Supply Voltage VDD/VDDA = 3.3 V +/-5%, See Test Loads for Loading Conditions PARAMETER SYMBOL Input High Voltage - DIF_IN VIHDIF Input Low Voltage - DIF_IN VILDIF Input Common Mode Voltage - DIF_IN Input Amplitude - DIF_IN Input Slew Rate - DIF_IN Input Leakage Current Input Duty Cycle Input Jitter - Cycle to Cycle 1 2 CONDITIONS Differential inputs (single-ended measurement) Differential inputs (single-ended measurement) MIN TYP MAX UNITS NOTES 600 750 1150 mV 1 VSS - 300 0 300 mV 1 VCOM Common Mode Input Voltage 300 1000 mV 1 VSWING dv/dt I IN dtin J DIFIn Peak to Peak value Measured differentially VIN = VDD , VIN = GND Measurement from differential wavefrom Differential Measurement 300 0.4 -5 45 0 1450 8 5 55 125 mV V/ns uA % ps 1 1,2 1 1 1 Guaranteed by design and characterization, not 100% tested in production. Slew rate measured through +/-75mV window centered around differential zero Electrical Characteristics - DIF 0.7V Current Mode Differential Outputs TA = TCOM; Supply Voltage VDD/VDDA = 3.3 V +/-5%, See Test Loads for Loading Conditions PARAMETER SYMBOL CONDITIONS MIN TYP Slew rate Slew rate matching Rise/Fall Time Matching dV/dt dV/dt Trf Scope averaging on Slew rate matching, Scope averaging on Rise/fall matching, Scope averaging off 1 2.5 Voltage High VHigh 660 750 Voltage Low VLow Statistical measurement on single-ended signal using oscilloscope math function. (Scope averaging on) Max Voltage Min Voltage Vswing Crossing Voltage (abs) Crossing Voltage (var) Vmax Vmin Vswing Vcross_abs -Vcross Measurement on single ended signal using absolute value. (Scope averaging off) Scope averaging off Scope averaging off Scope averaging off MAX UNITS V/ns 4 % 20 ps 125 NOTES 1, 2, 3 1, 2, 4 1, 7, 8 850 1 mV -150 150 1150 -300 300 250 550 140 1 mV mV mV mV 1 1 1, 2 1, 5 1, 6 Guaranteed by design and characterization, not 100% tested in production. IREF = VDD/(3xRR). For RR = 475 (1%), I REF = 2.32mA. I OH = 6 x I REF and VOH = 0.7V @ ZO=50 (100 differential impedance). 1 2 Measured from differential waveform 3 Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around differential 0V. 4 Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. 5 Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising edge (i.e. Clock rising and Clock# falling). 6 The total variation of all Vcross measurements in any particular system. Note that this is a subset of V_cross_min/max (V_cross absolute) allowed. The intent is to limit Vcross induced modulation by setting V_cross_delta to be smaller than V_cross absolute. 7 Measured from single-ended waveform 8 Measured with scope averaging off, using statistics function. Variation is difference between min and max. Electrical Characteristics - Current Consumption TA = TCOM; Supply Voltage VDD/VDDA = 3.3 V +/-5%, See Test Loads for Loading Conditions PARAMETER SYMBOL CONDITIONS TYP MAX UNITS NOTES Operating Supply Current IDD3.3OP I DD3.3PDZ All outputs active @100MHz, CL = Full load; 407 500 mA 1 All differential pairs tri-stated 12 36 mA 1 Powerdown Current 1 Guaranteed by design and characterization, not 100% tested in production. IDT(R) 19-Output Differential Zbuffer for PCIe Gen2/3 and QPI 6 MIN 1648H- 12/08/11 9ZX21901C 19-Output Differential Zbuffer for PCIe Gen2/3 and QPI Electrical Characteristics - Skew and Differential Jitter Parameters TA = TCOM; Supply Voltage VDD/VDDA = 3.3 V +/-5%, See Test Loads for Loading Conditions PARAMETER SYMBOL CONDITIONS Input-to-Output Skew in PLL mode nominal value @ 25C, 3.3V Input-to-Output Skew in Bypass mode nominal value @ 25C, 3.3V Input-to-Output Skew Varation in PLL mode across voltage and temperature CLK_IN, DIF[x:0] tSPO_PLL CLK_IN, DIF[x:0] tPD_BYP CLK_IN, DIF[x:0] tDSPO_PLL CLK_IN, DIF[x:0] tDSPO_BYP Input-to-Output Skew Varation in Bypass mode across voltage and temperature CLK_IN, DIF[x:0] tDTE Random Differential Tracking error beween two 9ZX devices in Hi BW Mode CLK_IN, DIF[x:0] tDSSTE Random Differential Spread Spectrum Tracking error beween two 9ZX devices in Hi BW Mode DIF{x:0] tSKEW_ALL PLL Jitter Peaking PLL Jitter Peaking PLL Bandwidth PLL Bandwidth Duty Cycle jpeak-hibw jpeak-lobw pllHIBW pllLOBW tDC Duty Cycle Distortion t DCD Jitter, Cycle to cycle tjcyc-cyc Output-to-Output Skew across all outputs (Common to Bypass and PLL mode) LOBW#_BYPASS_HIBW = 1 LOBW#_BYPASS_HIBW = 0 LOBW#_BYPASS_HIBW = 1 LOBW#_BYPASS_HIBW = 0 Measured differentially, PLL Mode Measured differentially, Bypass Mode @100MHz PLL mode Additive Jitter in Bypass Mode MIN TYP MAX UNITS NOTES -100 0 100 ps 1,2,4,5,8 2.5 3.5 4.5 ns 1,2,3,5,8 -50 0 50 ps 1,2,3,5,8 250 ps 1,2,3,5,8 3 5 ps (rms) 1,2,3,5,8 15 75 ps 1,2,3,5,8 37 65 ps 1,2,3,8 0 0 2 0.7 45 1.3 0.8 3 1.1 50 2.5 2 4 1.4 55 dB dB MHz MHz % 7,8 7,8 8,9 8,9 1 -2 0 2 % 1,10 41 20 50 50 ps ps 1,11 1,11 -250 Notes for preceding table: Measured into fixed 2 pF load cap. Input to output skew is measured at the first output edge following the corresponding input. 2 Measured from differential cross-point to differential cross-point. This parameter can be tuned with external feedback path, if present. 1 3 All Bypass Mode Input-to-Output specs refer to the timing between an input edge and the specific output edge created by it. 4 This parameter is deterministic for a given device 5 Measured with scope averaging on to find mean value. DIF_IN slew rate must be matched to DIF output slew rate. t is the period of the input clock 6. 7 Measured as maximum pass band gain. At frequencies within the loop BW, highest point of magnification is called PLL jitter peaking. 8. Guaranteed by design and characterization, not 100% tested in production. 9 Measured at 3 db down or half power point. 10 Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode. 11 Measured from differential waveform IDT(R) 19-Output Differential Zbuffer for PCIe Gen2/3 and QPI 1648H- 12/08/11 7 9ZX21901C 19-Output Differential Zbuffer for PCIe Gen2/3 and QPI Electrical Characteristics - Phase Jitter Parameters TA = TCOM; Supply Voltage VDD/VDDA = 3.3 V +/-5%, See Test Loads for Loading Conditions PARAMETER SYMBOL t jphPCIeG1 t jphPCIeG2 Jitter, Phase t jphPCIeG3 t jphQPI_SMI t jphPCIeG1 t jphPCIeG2 Additive Phase Jitter, Bypass mode t jphPCIeG3 t jphQPI_SMI CONDITIONS PCIe Gen 1 PCIe Gen 2 Lo Band 10kHz < f < 1.5MHz PCIe Gen 2 High Band 1.5MHz < f < Nyquist (50MHz) PCIe Gen 3 (PLL BW of 2-4MHz, CDR = 10MHz) QPI & SMI (100MHz or 133MHz, 4.8Gb/s, 6.4Gb/s 12UI) QPI & SMI (100MHz, 8.0Gb/s, 12UI) QPI & SMI (100MHz, 9.6Gb/s, 12UI) PCIe Gen 1 PCIe Gen 2 Lo Band 10kHz < f < 1.5MHz PCIe Gen 2 High Band 1.5MHz < f < Nyquist (50MHz) PCIe Gen 3 (PLL BW of 2-4MHz, CDR = 10MHz) QPI & SMI (100MHz or 133MHz, 4.8Gb/s, 6.4Gb/s 12UI) QPI & SMI (100MHz, 8.0Gb/s, 12UI) QPI & SMI (100MHz, 9.6Gb/s, 12UI) MIN TYP 39 MAX 86 1.1 3 2.6 3.1 0.6 1 0.36 0.5 0.23 0.3 0.18 0.2 4 10 0.25 0.3 0.57 0.7 0.20 0.3 0.22 0.3 0.08 0.1 0.08 0.1 UNITS ps (p-p) ps (rms) ps (rms) ps (rms) ps (rms) ps (rms) ps (rms) ps (p-p) ps (rms) ps (rms) ps (rms) ps (rms) ps (rms) ps (rms) Notes 1,2,3 1,2 1,2 1,2,4 1,5 1,5 1,5 1,2,3 1,2,6 1,2,6 1,2,4,6 1,5,6 1,5,6 1,5,6 1 Applies to all outputs. See http://www.pcisig.com for complete specs 3 Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12. 4 Subject to final radification by PCI SIG. 5 Calculated from Intel-supplied Clock Jitter Tool v 1.6.3 6 For RMS figures, additive jitter is calculated by solving the following equation: (Additive jitter)^2 = (total jittter)^2 - (input jitter)^2 2 Power Management Table Inputs CKPWRGD_PD# DIF_IN/ DIF_IN# SMBus EN bit 0 X 1 Running X 0 1 1 Control Bits/Pins DIF(5:12)/ OE# Pin DIF(5:12)# X X 0 1 Hi-Z1 Hi-Z1 Running Hi-Z1 Other DIF/ DIF# Outputs DFB_OUT/ DFB_OUT# PLL State Hi-Z1 Hi-Z1 Running Running Hi-Z1 Running Running Running OFF ON ON ON NOTE: 1. Due to external pull down resistors, HI-Z results in Low/Low on the True/Complement outputs IDT(R) 19-Output Differential Zbuffer for PCIe Gen2/3 and QPI 1648H- 12/08/11 8 9ZX21901C 19-Output Differential Zbuffer for PCIe Gen2/3 and QPI Clock Periods - Differential Outputs with Spread Spectrum Disabled SSC OFF Center Freq. MHz DIF 100.00 133.33 1 Clock 1us 0.1s - ppm -SSC -c2c jitter Short-Term Long-Term AbsPer Average Average Min Min Min 9.94900 9.99900 7.44925 7.49925 Measurement Window 0.1s 0.1s + ppm 0 ppm Long-Term Period Average Nominal Max 10.00000 10.00100 7.50000 7.50075 1us +SSC Short-Term Average Max 1 Clock +c2c jitter AbsPer Max 10.05100 7.55075 Units Notes ns ns 1,2,3 1,2,4 Clock Periods - Differential Outputs with Spread Spectrum Enabled SSC ON Center Freq. MHz DIF 99.75 133.00 1 Clock 1us 0.1s - ppm -SSC -c2c jitter Short-Term Long-Term AbsPer Average Average Min Min Min 9.94906 9.99906 10.02406 7.44930 7.49930 7.51805 Measurement Window 0.1s 0.1s + ppm 0 ppm Long-Term Period Average Nominal Max 10.02506 10.02607 7.51880 7.51955 1us +SSC Short-Term Average Max 10.05107 7.53830 1 Clock +c2c jitter AbsPer Max 10.10107 7.58830 Units Notes ns ns 1,2,3 1,2,4 Notes: 1 Guaranteed by design and characterization, not 100% tested in production. 2 All Long Term Accuracy specifications are guaranteed with the assumption that the input clock complies with CK420BQ/CK410B+ accuracy requirements (+/-100ppm). The 9ZX21901 itself does not contribute to ppm error. 3 4 Driven by SRC output of main clock, 100 MHz PLL Mode or Bypass mode Driven by CPU output of main clock, 133 MHz PLL Mode or Bypass mode Thermal Characteristics Parameter Thermal Resistance Junction to Ambient Thermal Resistance Junction to Case Thermal Resistance Junction to Board Symbol JA JA JA JC JB Conditions Min. Typ. Max. Units Still air 26.2 C/W 1 m/s air flow 23.1 C/W 3 m/s air flow 19.6 C/W 10.4 C/W 0.3 C/W Differential Output Termination Table DIF Zo () Iref () Rs () Rp () 100 85 475 412 33 27 50 43.2 9ZX21901 Differential Test Loads 10 inches Rs Differential Zo 2pF Rs Rp 2pF Rp HCSL Output Buffer IDT(R) 19-Output Differential Zbuffer for PCIe Gen2/3 and QPI 1648H- 12/08/11 9 9ZX21901C 19-Output Differential Zbuffer for PCIe Gen2/3 and QPI General SMBus serial interface information for the 9ZX21901C (See also 9ZX21901 SMBus Addressing on page 2) How to Write: How to Read: Controller (host) sends a start bit. Controller (host) sends the write address XX (H) IDT clock will acknowledge Controller (host) sends the beginning byte location = N IDT clock will acknowledge Controller (host) sends the data byte count = X IDT clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 * IDT clock will acknowledge each byte one at a time * Controller (host) sends a Stop bit * * * * * * * * * * * * * * * * * * * * * * Index Block Read Operation Index Block Write Operation Controller (Host) starT bit T Controller (host) will send start bit. Controller (host) sends the write address XX (H) IDT clock will acknowledge Controller (host) sends the begining byte location = N IDT clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read addressYY (H) IDT clock will acknowledge IDT clock will send the data byte count = X IDT clock sends Byte N + X -1 IDT clock sends Byte 0 through byte X (if X(H) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit IDT (Slave/Receiver) T Controller (Host) starT bit IDT (Slave/Receiver) Slave Address XX (H) WR WRite Slave Address XX(H) WRite WR ACK ACK Beginning Byte = N Beginning Byte = N ACK ACK RT Data Byte Count = X ACK Repeat starT Slave Address YY (H) RD ReaD Beginning Byte N ACK X Byte ACK Data Byte Count = X ACK Beginning Byte N Byte N + X - 1 ACK X Byte ACK P stoP bit Note: XX(H) is defined by SMBus address select pins. Byte N + X - 1 N P IDT(R) 19-Output Differential Zbuffer for PCIe Gen2/3 and QPI Not acknowledge stoP bit 1648H- 12/08/11 10 9ZX21901C 19-Output Differential Zbuffer for PCIe Gen2/3 and QPI SMBusTable: PLL Mode, and Frequency Select Register Byte 0 Pin # Name Control Function 5 PLL Mode 1 PLL Operating Mode Rd back 1 Bit 7 5 PLL Mode 0 PLL Operating Mode Rd back 0 Bit 6 72/71 DIF_18_En Output Control overrides OE# pin Bit 5 70/69 DIF_17_En Output Control overrides OE# pin Bit 4 67/66 DIF_16_En Output Control overrides OE# pin Bit 3 Reserved Bit 2 Reserved Bit 1 4 100M_133M# Frequency Select Readback Bit 0 Type R R RW RW RW R 133MHz 100MHz 0 1 Hi-Z Enable 0 1 Hi-Z Enable 0 1 SMBusTable: Output Control Register Byte 1 Pin # Name 39/38 DIF_7_En Bit 7 35/36 DIF_6_En Bit 6 32/33 DIF_5_En Bit 5 29/30 DIF_4_En Bit 4 27/28 DIF_3_En Bit 3 24/25 DIF_2_En Bit 2 22/23 DIF_1_En Bit 1 19/20 DIF_0_En Bit 0 Output Output Output Output Output Output Output Output Control Function Control overrides OE# pin Control overrides OE# pin Control overrides OE# pin Control overrides OE# pin Control overrides OE# pin Control overrides OE# pin Control overrides OE# pin Control overrides OE# pin Type RW RW RW RW RW RW RW RW SMBusTable: Output Control Register Byte 2 Pin # Name 65/64 DIF_15_En Bit 7 62/61 DIF_14_En Bit 6 60/59 DIF_13_En Bit 5 56/55 DIF_12_En Bit 4 53/52 DIF_11_En Bit 3 50/49 DIF_10_En Bit 2 47/46 DIF_9_En Bit 1 42/41 DIF_8_En Bit 0 Output Output Output Output Output Output Output Output Control Function Control overrides OE# pin Control overrides OE# pin Control overrides OE# pin Control overrides OE# pin Control overrides OE# pin Control overrides OE# pin Control overrides OE# pin Control overrides OE# pin Type RW RW RW RW RW RW RW RW SMBusTable: Output Enable Pin Status Readback Register Byte 3 Name Control Function Pin # 57 OE_RB12 Real Time readback of OE#12 Bit 7 54 OE_RB11 Real Time readback of OE#11 Bit 6 51 OE_RB10 Real Time readback of OE#10 Bit 5 48 OE_RB9 Real Time readback of OE#9 Bit 4 43 OE_RB8 Real Time readback of OE#8 Bit 3 40 OE_RB7 Real Time readback of OE#7 Bit 2 37 OE_RB6 Real Time readback of OE#6 Bit 1 34 OE_RB5 Real Time readback of OE#5 Bit 0 IDT(R) 19-Output Differential Zbuffer for PCIe Gen2/3 and QPI 0 1 See PLL Operating Mode Readback Table Hi-Z Enable Hi-Z Enable Hi-Z Enable Type R R R R R R R R OE# pin Low Default Latch Latch 1 1 1 0 0 Latch Default 1 1 1 1 1 1 1 1 Default 1 1 1 1 1 1 1 1 Default Real time Real time Real time Real time OE# Pin High Real time Real time Real time Real time 1648H- 12/08/11 11 9ZX21901C 19-Output Differential Zbuffer for PCIe Gen2/3 and QPI SMBusTable: Reserved Register Byte 4 Pin # Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SMBusTable: Vendor & Revision ID Register Byte 5 Pin # Name RID3 Bit 7 RID2 Bit 6 RID1 Bit 5 RID0 Bit 4 VID3 Bit 3 VID2 Bit 2 VID1 Bit 1 VID0 Bit 0 SMBusTable: DEVICE ID Byte 6 Pin # Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name SMBusTable: Byte Count Register Byte 7 Pin # Name Bit 7 Bit 6 Bit 5 BC4 Bit 4 BC3 Bit 3 BC2 Bit 2 BC1 Bit 1 BC0 Bit 0 Control Function Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Type 0 1 Default 0 0 0 0 0 0 0 0 Control Function Type R R R R R R R R 0 1 - - Default X X X X 0 0 0 1 Type R R R R R R R R 0 1 REVISION ID VENDOR ID Control Function Device ID 7 (MSB) Device ID 6 Device ID 5 Device ID 4 Device ID 3 Device ID 2 Device ID 1 Device ID 0 Control Function Reserved Reserved Reserved Writing to this register configures how many bytes will be read back. SMBusTable: Reserved Register Byte 8 Pin # Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Control Function Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved IDT(R) 19-Output Differential Zbuffer for PCIe Gen2/3 and QPI Type RW RW RW RW RW Type B rev = 0001 C Rev = 0010 Device ID is 219 decimal or DB hex. 0 1 Default value is 8 hex, so 9 bytes (0 to 8) will be read back by default. 0 1 Default 1 1 0 1 1 0 1 1 Default 0 0 0 0 1 0 0 0 Default 0 0 0 0 0 0 0 0 1648H- 12/08/11 12 9ZX21901C 19-Output Differential Zbuffer for PCIe Gen2/3 and QPI DIF Reference Clock Common Recommendations for Differential Routing L1 length, route as non-coupled 50ohm trace L2 length, route as non-coupled 50ohm trace L3 length, route as non-coupled 50ohm trace Rs Rt Dimension or Value 0.5 max 0.2 max 0.2 max 33 49.9 Unit inch inch inch ohm ohm Figure 1 1 1 1 1 Down Device Differential Routing L4 length, route as coupled microstrip 100ohm differential trace 2 min to 16 max L4 length, route as coupled stripline 100ohm differential trace 1.8 min to 14.4 max inch inch 1 1 Differential Routing to PCI Express Connector L4 length, route as coupled microstrip 100ohm differential trace 0.25 to 14 max L4 length, route as coupled stripline 100ohm differential trace 0.225 min to 12.6 max inch inch 2 2 Figure 1: Down Device Routing L2 L1 Rs L4 L4' L2' L1' Rs HCSL Output Buffer Rt Rt L3' PCI Express Down Device REF_CLK Input L3 Figure 2: PCI Express Connector Routing L2 L1 Rs L4 L4' L2' L1' HCSL Output Buffer Rs Rt Rt L3' IDT(R) 19-Output Differential Zbuffer for PCIe Gen2/3 and QPI PCI Express Add-in Board REF_CLK Input L3 1648H- 12/08/11 13 9ZX21901C 19-Output Differential Zbuffer for PCIe Gen2/3 and QPI Alternative Termination for LVDS and other Common Differential Signals (figure 3) Vdiff Vp-p Vcm R1 R2 R3 R4 Note 0.45v 0.22v 1.08 33 150 100 100 0.58 0.28 0.6 33 78.7 137 100 0.80 0.40 0.6 33 78.7 none 100 ICS874003i-02 input compatible 0.60 0.3 1.2 33 174 140 100 Standard LVDS R1a = R1b = R1 R2a = R2b = R2 Figure 3 L2 L1 R3 R1a L4 R4 L4' L2' L1' R1b HCSL Output Buffer R2a R2b L3' Down Device REF_CLK Input L3 Cable Connected AC Coupled Application (figure 4) Component Value Note R5a, R5b 8.2K 5% R6a, R6b 1K 5% Cc 0.1 F Vcm 0.350 volts Figure 4 3.3 Volts R5a R5b R6a R6b Cc L4 L4' Cc IDT(R) 19-Output Differential Zbuffer for PCIe Gen2/3 and QPI PCIe Device REF_CLK Input 1648H- 12/08/11 14 9ZX21901C 19-Output Differential Zbuffer for PCIe Gen2/3 and QPI (Ref. ) Seating Plane (N D - 1)x e (Ref. ) A1 Index Area ND & NE Even A3 N L N e (Typ.) 2 If N D & N E are Even 1 Anvil Singulation 1 2 E2 OR E (Ref. ) 2 Sawn Singulation Top View (N E - 1)x e E2 b (Ref.) A D e Thermal Base D2 2 ND & NE Odd D2 Chamfer 4x 0.6 x 0.6 max OPTIONAL C 0.08 C THERMALLY ENHANCED, VERY THIN, FINE PITCH QUAD FLAT / NO LEAD PLASTIC PACKAGE DIMENSIONS SYMBOL N ND NE DIMENSIONS (mm) 72L 72 18 18 SYMBOL A A1 A3 b e D x E BASIC D2 MIN. / MAX. E2 MIN. / MAX. L MIN. / MAX. MAX. MIN. 0.8 1.0 0 0.05 0.25 Reference 0.18 0.3 0.50 BASIC 10.00 x 10.00 5.75 6.15 5.75 6.15 0.3 0.5 Ordering Information Part / Order Number 9ZX21901CKLF 9ZX21901CKLFT Shipping Package Trays Tape and Reel Package 72-pin MLF 72-pin MLF Temperature 0 to +70C 0 to +70C "LF" designates PB-free configuration, RoHS compliant. IDT(R) 19-Output Differential Zbuffer for PCIe Gen2/3 and QPI 1648H- 12/08/11 15 9ZX21901C 19-Output Differential Zbuffer for PCIe Gen2/3 and QPI Revision History Rev. 0.1 A B C D E F G H Issue Date Who Description Page # 1/20/2010 RDW Initial release Various 1. Corrected input clock on block diagram, updated QPI reference to 9.6GTs, added note about fixed feedback path, added comment about DFB_OUT needed termination network. 6/10/2010 RDW 1,5,6,9 2. Reformatted electrical tables to fit new standard format 3. Added output termination/test load drawing and table 4. Released to final 1. Merged Phase Jitter Tables into Single Table. 6/22/201 RDW 8 2. Reformatted Electrical Tables into common format for future datasheets. 1. Updated front page to standard 9ZX format. 2. Clarified that SMBus Address Selection table includes the Read/Write Bit. Minor 8/3/2010 RDW clarifications to other tables. 3. Added additive phase jitter table for bypass mode. 1-3, 5-11 3/2/2011 RDW 1. Added rise/fall varation spec to HCSL_Out table 6 5/11/2011 RDW 1. Added note to pinout indicating that the DFB_OUT pins must be terminated. 2 1. Added "Case Temperature" to Abs Max specs. 9/20/2011 RDW Various 2. Added Thermal Char data 10/24/2011 LPL 1. Updated Thermal Characteristics table. 9 12/8/2011 RDW 1. Updated tDSPO_BYP parameter from +/-350 to +/-250ps. 7 Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 408-284-6578 pcclockhelp@idt.com Corporate Headquarters Asia Pacific and Japan Europe Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) IDT Singapore Pte. Ltd. 1 Kallang Sector #07-01/06 KolamAyer Industrial Park Singapore 349276 Phone: 65-6-744-3356 Fax: 65-6-744-1764 IDT Europe Limited 321 Kingston Road Leatherhead, Surrey KT22 7TU England Phone: 44-1372-363339 Fax: 44-1372-378851 (c) 2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, ICS, and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA 16