ICs for Communications
Broadband Multichannel Subscriber Line-Interface Circuits for
Splitterless G.Lite Applications
B-MuSLIC
PEB 4550
PEB 3554
PEB 55504
PEB 35508
Preliminary Product Overview 05.99
•
For questions on technology, delive ry and prices please contact the Infineon Technologies Offices
in Germany or the Infine on Tec hnologies Companies and Representatives worldwide:
see our webpage at http://www.infineon.com
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© Infineon Technologies AG i. Gr. 1999.
All Rights Reserved.
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applications, processes and circuits implemented within components or assemblies.
The information describes the type of component and shall not be considered as assured characteristics.
Terms of delivery and rights to change design reserved.
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question please contact your nearest Infineon Technologies Office.
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Preliminary Product Overview 3 05.99
12YHUYLHZ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
1.2 Typical Ap plica tio ns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
1.3 Product Family Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
2)XQFWLRQDO'HVFULSWLRQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
2.1 B-SLIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
2.2 B-Q AP ADSL-Lite A nalog Frontend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
2.3 ALiDD ADSL-Lite Data Pump Functions . . . . . . . . . . . . . . . . . . . . . . . . . . .16
2.4 B-MuPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
2.5 Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
2.6 Pro grammable Voice-path Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.6.1 BORSCHT Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
2.6.2 Additional Lin e Circuit Functions: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
2.6.3 DC Feeding Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
2.7 Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
2.8 Pro gra mmable Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
32SHUDWLRQDO'HVFULSWLRQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
3.1 Active with Concurrent Data and Voice Transmission . . . . . . . . . . . . . . . . . 29
3.2 Active-voice-only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
3.3 Ringi ng . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
3.4 Power-saving Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
3.5 Subscriber Loop Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.6 Line Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
3.6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.6.2 Traditional Line Testin g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.6.3 ITDF (Integrated Test and Diagnostic Functions) with the B-MuSLIC . . . 34
4,QWHUIDFHV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
4.1 PCM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
4.2 IOM-2 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
4.3 Utopia-2 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
4.4 B-Mu PP 8-bit Microcontroller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
4.5 ALi DD 8/16-bit Micro co ntrol ler Interface . . . . . . . . . . . . . . . . . . . . . . . . . . .41
4.5.1 Host Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4.6 Tip-a nd- ring Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
5$SSOLFDWLRQ&LUFXLWDQG7RROV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
5.1 Typical Ap plica tio n Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
5.2 Support Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
5.2.1 B-MuSLICOS Coefficient Calculating Software . . . . . . . . . . . . . . . . . . . .44
5.2.2 SMART 35508 and SMART 55504 Tool Packages . . . . . . . . . . . . . . . . .45
63DFNDJH2XWOLQHV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
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Preliminary Product Overview 4 05.99
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This document summarizes the Broadband Multichannel Subscriber Line-Interface
Circuits for Splitterless G.Lite Applications (B-MuSLIC). The B-MuSLIC is a highly
integrated chipset integrating ADSL-Lite functionality with the proven MuSLIC PCM
codec filter for analog telephony applications. This product provides all ADSL-Lite
functionality required by ITU-T G.992.2, and provides software-programmable
BORSCHT functionality to meet worldwide voice telephony standards. The B-MuSLIC
provides up to 8 ADSL Lite and analog voice channels, is totally programmable, and
integrates many pr eviously external functions on-chip.
This document contains general information about the B-MuSLIC and describes in brief
the main features, function al blocks, interfaces, and typical applications of the chipset.
Please refer to Related Documentation for technical specifica t ions.
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Abbrevia tions and acronyms are shown at the end of the document.
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Preliminary Product Overview 5 05.99
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The B-MuSLIC chipset (Figure 1-1) is used in ADSL-Lite DSLAMs for Central Offices
(COs) and Digital-Loop Carrier systems (DLCs).
The %0X6/,& (Broadband Multichannel Subscriber Line-Interface Circuits for
Splitterless G.Lite Applications) chipset comprises:
•%6/,& ( PEB 45 50 Broadband Ringing SLIC)
– Single-channel Bro adband Subscriber Line Circuit
•%4$3(PEB 3554) ADSL.lite Analog Frontend
– 4-channel AD/DA converter with integrated filters
•$/L'' (PEB 55504)
– 4-channel ADSL-Lite Data Pump compatible with G.Lite standard
%0X33(PEB 35508 Bro adband Multichannel Proce ssor for POTS)
– 8-channel voice processing DSP with µC and PCM/IOM2 interface
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The B-MuSLIC chipset supports data transmission at rates of 1536 kbps downstream
and 512 kbps upstream simultaneously with voice transmission. Eight-bit data is sent to
the ALiDD using a Utopia-2 ATM interface, while voice is sent to the B-MuPP using either
a PCM highway or the IOM-2 interface (Figure 1-3). Programming, control, and signalling
information from the ALi DD and the B-MuPP is sent to the local processor via a flexib le
8-bi t parallel µP interface.
ADSL-Lite utilizes the existing copper pair that traditionally has been used only for POTS
service. ADSL-Li te offers subscrib ers the adva ntage of concurren t sp litterless da ta and
voice transmission. The data and voice services are separated within the B-MuSLIC
chipset; thus, no external splitter is required (Figure 1-1). For each channel, the linecard
provides a line driver , an A/D and D/A converter, and an ADS L-L ite data pump.
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The B-MuSLIC is an optimized and integrated solution for linecards, providing 4
channels of ADSL-Lite data transmission at 1536 kbps downstream and up to 512 kbps
upstream in one ch ipset.
Eight-bit d ata is sent to the ALiDD u sing an Utopia-2 ATM interface. Programming and
control information for ALiDD and B-MuPP is exchanged with a local processor via a
flexible 8- or 16-bit parallel µP interface.
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• Applica tion for COs, Access Networks (ANs), DLCs, PBXs
• Highly integ rated
• 8-channel G.992.2 (ADSL-lite) compliant
• Data pump fully software upgradeable
• Integrated data/voice separation, no additional POTS Splitter required
• No separate ADSL Linecard required, no DSLAM required
•µC/PCM and IOM-2 Inte rfaces for voice
• Data inte rface switch able between Utopia-2 or µC interface
• Integrated prog rammable balanced ringing (85 Vrms) with supp ort for external
unba lanced rin ging
• Voice telepho ny in accordance with relevant ITU-T Q.552 Z interface, LSSGR,
Bellcore, and DTAG recommendations
• Chann el-independent prog rammable filters for country-specific requirements:
– Impedance matching
– Transhybrid balancing
– Frequency response
– Receive/transmit levels
– DC-feeding
• Line supervision
• Integrated Test and Diagnostic Functionality (ITDF)
– Line test, circuit test, board test
• Utopia-2 compliant data interface
•µC Interface for chipset control
• High-performance 1 3-bit A/D and D/A conversio n
• GPIO pins
• Data-onl y mode uses tones #1-5 for upstream directio n (optional)
• Chipset fa mily offers
- Migration path to fu ll-rate ADSL
- Higher integration (fewer external parts, more channels)
- Solution for DSLAMs (ADSL-Lite d ata only); refe r to separate product overview
• Power Down Mode with Off-Hook (Voice) and Remote Active Request (Data)
detection; each channel can be powered down individ ually
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Many applications benefit from the highly integrated,
versatile B-MuSLIC architecture. Product reliability and
manufacturability are enhanced by the high level of
integration and by fabrication in low-power mixed-
signal CMOS technology. The inherent flexibility and
scalability reduces time-to-market, inventory costs,
and support administration. The following list and
figures show some of the typical applications for which
the B-MuSLIC was designed.
• Highly integrated ADSL-Lite linecards for linecards
with 4, 8, or more channels in:
– COs (Figure 1-3)
–PBXs
–ANs
– DLCs
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This document describes the B-MuSLIC and its features. The roadmap for the B-MuSLIC
includes higher integration, and the B-MuSLIC-F, which will support full-rate ADSL
according to G.99 2.1.
For data-only G.Lite DSLAM applicat ions, refer to the MuCADO L/F documentation.
In contrast to the B-MuSLIC architecture described above, the MuCADO L is a highly
integrated chipset solution for ADSL-Lite data-only service without voice-transmission. It
is targeted at DSLAM applications that support ADSL-Lite .
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This section describes the functional blocks of the B-MuSLIC chipset (Figure 2-1).
Functions are described in detail in the following sections:
• 2.3 ALiDD ADS L-Lite Data Pump Functions
• 2.2 B-QAP ADSL-Lite Analog Frontend
• 2.4 B-MuPP
• 2.1 B-SLIC
• 2.5 Interfaces
• 2.6 Pro grammable Voice -pa th Parameter
• 2.7 Powe r Dissipation
• 2.8 Programmable Parameters
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The B-MuSLIC chipset is a cost-effective, high-performance solution for Integrated
Voice and Data (IVD) ADSL-Lite linecards according to the ITU-T recommendation
G.992.2. It offers splitterless operation (no splitter in CO and no splitter at CPE needed)
and a fully-featur ed solution for voice telephony.
The detailed functional block (Figure 2-5) shows how all G.992.2 functions and voice
functions are implemented using 4 integrated circuits. The ALiDD is a DSP optimized for
ADSL-Lite; it offers an Utopia-2 interface for data, and a synchronous parallel µC
interface for programming and control. The mixed-signal B-QAP provides 4 channels of
A/D and D/A conversion and filtering. The B-MuPP is a digital signal processor for analog
voice telephony, controls the B-QAP and generates required clocks. Its parallel interface
connects to a µC. The B-SL IC pro vi des all nece ssary line fee din g functi onality an d h as
very low harmonic distortio n.
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The B-SLIC (Broadband Subscriber Line Interface Circuit) is used as the interface
between the te lephone line and the B-QAP/B-Mu PP/ALIDD within integrated voice an d
data linecard s. It offers high-voltage func tionality.
Features:
• High-voltage line feeding
• Very linear data transmission
– THD = -70dB at 550 kHz (downstream)
– GBW = 20 MHz (downstream)
• Power Spectral Density -40dBm/Hz
• Internal ring signal injection up to 85 Vr ms (balanced)
• Sen sing of transversa l and longitudi nal line current
• Reliable170 V SM ART technolog y
• Boo sted battery mode for long telep hone lines
• Thermal shutdown
• Small P-DSO-20 power package
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The B-QAP contains all analog frontend functions for 4 independent voice and G-Lite
channels with sepa rate interfaces to 4 B-SLICs. In th e downstr eam direction, the seri al
data bitstream received from the ALiDD and the serial voice bitstream received from the
B-MuPP is combined into on datastream and then converted to analog with a D/A
converter. Th e signal passes a programmable gain stage before it re aches the external
B-SLIC. In the upstream direction, the received signal is converted to a digital data
stream and then separated into the data bitstream for ALiDD and the voice bitstream for
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Preliminary Produ ct Ove rview 15 05.99
B-MuPP. After passing hardware filters the bitstream is transferred to the ALiDD and B-
MuPP.
Also common to all 4 channels are the serial, digital interfaces to ALiDD and to B-MuPP.
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• 4-channel analog frontend for POTS and G .Lite data transmission
• No trimming or adjustmen ts required
• Advanced low-power 0.5-µm BiCMOS technology
• High performance 13-bit A/D and D/A conversion
• 4-pin serial interface to B-MUPP for vo ice path
• Differential an alog inputs/outputs
• 3 operating modes: Power-down, Active (voice and /or da ta) and Ringing
• Programmable transmit gain for power cut back on short lines
• Automatic gain contro l
• Very low no ise and distortion in whole downstream path
• 5-pin serial inte rface to ALiDD for data path
• BiCMOS technology
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• Standard SMD P-MQFP-100-2 package
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The ALiDD is an ITU-T G.992.2-compliant data pump capable of handling up to 4
channels of G.Lite. The ALiDD has a flexible architecture to ensure compatibility with
future versions and extensions of the standar d.
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• DSP-based ITU-T G.992.2 -co mpliant data pump for 4 channe ls
• Internal RAM elimina tes nee d for extern al RAM and allows software upgradability
• 8/16-bit parallel µC interface with mailbox interface
• 8 bit Utopia-2 interface
• Built-in PLL; CLKO can be used to clock another ALiDD
• Gen eral-purpose I/O pins
• Power-do w n mode
• SMD P-TQFP-144-1 package
• Advanced low-power CMOS technology
ADSL.Lite, also called G.Lite, is a broadband transmission standard for the frequency
range from 25 kHz (0 kHz optional) to 552 kHz. Because of the physical separation into
two different fre quency ranges for voice and data transmission the Frequency Division
Multiplexing (FDM) allows concur rent voice and data transmission without the need for
a splitter. Different frequency ranges are used for POTs band, and upstream and
downstream bands. To ensure proper concurrent transmission of voice and data, a
guard ba nd is imposed between the POTs band and the upstr eam band.
G.Lite specifies DMT (Discrete Multitone Transmission) based on a Fast Fourier
Transform (FFT) and a Inverse FFT to allocate the transmitted bits among many
narrowband QAM-modulated tones. The number of bits depends on the transport
capacity of each tone. Each of these narrowbands has a bandwidth of 4.31 25 kHz.
The different corner fre quencies are shown in Figur e 2-3.
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The data pro cessing of the up str eam and downstream pa th is sho wn in Figure 2-4 . For
detailed infor mation on data processin g, refer to the Data S hee t for the ALiDD (7%').
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Transmit
Power
Frequency
POTS
Band Upstream
Band Do wnstr eam Band
Guard
Band
Carrier 2-5
552
4kHz
25,875 138
Framer
Equalizer
QAM
Decoder
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ver
R/S
Decoder
CRC De-
Scrambler
Inv-
Framer
IFFT
QAM
Encoder
Interleaver
R/S
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CRC
Scrambler
FFT
Sample pre - / post
processing
Payload
data
AOC/EOC
S=1,2,4,8,16
R=0,4,8,16 D=1,...,16 2-15 Bi t s
per tone 128 tones
32 tones
2-15 bits
per tone
D=1,...,8
S=1,2,4,8,16
R=0,4,8,16
Payload
data
AOC/EOC
1,104
kS/s
276
kS/s
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•
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In downstream direction (CO to CPE), the ATM data stream received via the Utopia-2
interface is DMT-modulated and then transferred as a serial bitstream to the analog
frontend B-QAP. The received serial bitstream from the B-QAP is demodulated and sent
to the Utopia-2 interface as ATM cells.
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To simplify communications across the host interface, the ALiDD has a mailbox for
passing messages and control information between itself and the host. The mailbox
consists of 512x16 bits in both read and write directions. Please refer to Section 4.5
ALiDD 8/16-bit Microcontroller Interface .
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The ALiDD has a flexible clock-synthesis circuit. Consequently, the ALiDD can be
clocked internally at 4096 kHz, or with an external crystal. Also, the clock output is
available to feed to other ALiDD chips, thereby eliminating the need for an external
crystal for every other ALiDD on the board.
to
microcontroller
to
ATM Service
TC +
Utopia-2
B-QAP
Interface
Fram
er
Coder
Inter-
leaver
%XV
Pre-
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sing
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The ALiDD has on-chip memory to support all internal processing of the ADSL-Lite
channel. Th e ALiDD is fully software-upg radable.
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To facilitate system integration, the ALiDD has several programmable GPIO pins. These
pins are accessed via the ALiDD parallel µC interface.
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The ALiDD complies with G.992.2, G.Lite.
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The B-MuPP performs the voice processing and controls the B-QAP. The programmable
voice parameters can be contro lled throug h the B -MuPP.
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• Digital chip optimized for con tro l of a 8-channel POTS/G.Lite-based system
• Control of 2 B-Q AP analog frontend s (8 channels)
• Very small amount of glue logic required
• No trimming or ad justmen t re quired
• Specification according to ITU-T Q.552 Z interface, LSSGR, and DTAG
recommendation
• 8-bit parallel microcontroller interface for Intel-, Motorola-like Processors
• Host interface runn ing in multiplexed or demultiplexed mode
• Built-in PLL and clock generation
• PCM- encoded digital voice transmission (A-law, µ-law)
• IOM-2 or PCM highway for voice path
• Programmable digital filter for
– Impedance matching
– Transhybrid balancing
– Frequency response
– Gain
• Advanced test capabilities
– Integrated line and circuit tests
– 2 programmable ton e generators
• Digital pro grammable DC characteristics
– Programmab le constant current from 0 to 50 mA
– Programmable resi stive values from 0 to 2 x 800 Ω
– Programmab le constant voltage
• Programmable integrated Teletax (TTX) injection and filtering during active mode in
onhook and offhook states
– Programmable up to 10 Vrms at tip-and-ring wire of the B-SLIC
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– Programma ble frequency (12/16 kHz)
• Polarity reversal (either hard-coded or software-pro grammable)
• Integrated (balanced) ringing gen eration with zero crossi ng injection
– Programma ble frequency between 16 .6 and 70 Hz
– Programma ble amplitude up to 8 5 Vrms at tip-an d-ring of the B-SLIC
• Offhook detection with programmable thresholds for all operating modes
• Integrate d ring trip detection wi th zero crossing turn-off function
• Ground start and loop start possible
• 4 GPIO pins
• 4 pins for linecard identification
• 3 operating modes: Power-down, active and ringing
• SMD P-MQFP-64 package
• Advanced low-power CMOS technology
•
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The B-MuSL IC chip set has th e following interfaces:
• 8-bit parallel µP interface for multiple processor types (B-MuPP)
• PCM/IOM2 interface B-MuPP
• 8/16-bit parallel µP interface for multiple processor types (ALiDD)
• Utopia-2 Interface (ALiDD)
B-QAP
Interface
µ
C
C
O
N
T
R
O
L
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XI
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-
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C
M
PLL1 PLL2 CLK
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to
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PCM/IOM-2
to B-QAP
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The paral lel µC interfa ce can be set to Intel/Siemens multip lexed mode, Intel/Siemens
demultiplexed mode, or Motoro la demultiple xed mode . The chipset is programmed and
controlled via this interface.
8-bit data traffic is moved through a Utopia-2 interface.
Voice data is moved thro ugh the PCM or IOM2 interface.
Please refer to &KDSWHU for detailed information abou t the interfaces.
3URJUDPPDEOH9RLFHSDWK3DUDPHWHU
The B-MuS LIC forms a co mplete PO TS interface via control loop s for both the A C and
DC paths. The transversal and longitudinal currents on the line are sensed in the B-SLIC
and reported to the B-QAP. The current sense signal is converted to a voltage by an
external resistor. A capacitor separates the transversal line current into DC and AC
components.Th e AC and DC voltage signals are conver ted to dig ital in the B -QAP and
sent to the B-MuPP for processing. The B-MuPP processes the AC and DC signals and
sends them back to the B-QAP where they are converted to analog an d sent to the B-
SLIC. The B-SLIC then combines the AC and DC signals, amplifies them and drives
them onto the subscriber line. Via this path the subscriber line current is sensed,
processed and an appropriate voltage is then applied to the subscriber line. Since all of
the processing is done in the digital domain, it is possible to change the electrical
characteristics of the line by software.
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Conventional linecard designs need a number of external components to adapt the
circuit for us e in different countrie s and application s. The B-MuSLIC chipset in tegrates
the following pro grammable functions on-chip:
• DC (battery) feed characteristics
• AC impedance matching
• Transmit gain
• Receive gain
• Hybrid balance
• Freque ncy respo nse in transmit and receive direction
• Ring frequency and amplitude
• Hook, ring-trip, and ground-key thre sholds
• Test and diagnostic functions
• TTX/Pulse metering
One of the primary challenges of linecard development is to adapt the above-mentioned
functions to country-specific requirements. Because these functions are software
programmable, it is not necessary to change the linecard hardware to meet different
country requirements or parameters. Because signal processing within the B-MuPP is
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completely digital, it is possible to adapt to country-specific requirements by simply
updating the coefficients tha t control the DSP that processes a ll the data. This means,
for example, th at chan gin g impeda nce matching or hybrid balancin g no longer re quires
hardware modifications. The digital nature of the filters and gain stages also assures
high reliability, no drifts due to temperature or time, and minimal variability among
different lines. Also, since each channel is processed independently, it is possible to
configure different channels for different line character istics.
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An analog line circuit provides the voltage and current for subscriber equipment. In
conventional line circuits, extra hardware is needed to adapt the battery feed
characteristics to the requirements for different applications and countries. With the B-
MuSLIC chipset, the battery-feed (DC) characteristics can be programmed in the B-
MuPP itself an d applied to the line via the B-SLIC.
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Reliable overvoltage protection is provided by the robust 170 V SLIC technology
together with a few inexpensive exte rnal pa rts such a s varistors, resistors a nd thyristo r
diod es.
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The ringin g signal is a low-frequen cy, high-voltage signal to the subscriber e quipment.
In conventional line circuits, the ringing voltage (40 to 85 Vrms) is generated in an
external ringing generator and applied to the tip-and-ring lines by a relay. With the B-
MuSLIC chipset, the ringing generator is integrated and no relay is needed (for balanced
ringing o nly). The ringing signal is ge nerated in the low-voltage B -MuPP and amplified
in the hig h-voltage B-SL IC. The B-MuSL IC suppo rts balanced an d unbalan ced ringing.
With balanced ringing, the ringing voltage is applied differentially to the tip-and-ring lines.
With unbalanced ringing, the ringing voltage is applied to either the tip or ring line against
a potential that is near ground by an external ringing generato r with relays.
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A linecard must detect onhook-to-offhook transitions in both non-ringing (hook switch
detection) and ringing states (ring trip detection). With the B-MuSLIC chipset, the
thresholds for offhook and ring trip dete ction ca n b e programmed in the B-MuPP to suit
different appli cations without changing e xter nal components.
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The B-Mu SLIC encod es an analog inp ut signal to a d igital PCM signal, and deco des a
PCM signal to an analog sign al. A-law, µ-law, and 16 -bit linear coding is supported and
is selected via softwa re.
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The subscriber equipment is connected to a 2-wire interface (tip-and-ring) where
information is transmitted full-duplex. For digital transmission through the switching
network, the information must be split into separate transmit and receive paths (4 wires).
To avoid gen erating ech oes, the hybrid fun ction requires a ba lanced ne twork matching
the line impedance. Since the hybrid balance in the B-MuSLIC is performed in the digital
domain, the hybrid balance can be chan ged without altering the external hardware.
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Subscriber loops can have many kinds of faults. Access to the analog loop is necessary
to perform the reg ular measurements involved in mo nitoring the local loop. L ine-circuit
functions must also be tested. In conventional line-circuit solutions, test units have to be
switched to perform loop- and line-circuit tests. A remote testing unit and relays are
normally necessary to perform a full range of tests. The only external component
required by the B-MuSLIC chipset is 1 test relay to measure the reference voltage, all
other functions are provided within the chipset, See “ITDF (Integrated Test and
Diagnostic Functions) with the B-MuSLIC” on page 34 .
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In many countrie s, pulse-metering TTX signals ca n be sent to the subscriber for b illing
purposes. A 12/16-kHz sinusoidal metering burst has to be transmitted. A 12/16-kHz
notch filter is provided in the transmit path to prevent overloading the transmit A/D
converter.
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The B-MuSLIC also supports metering by polarity reversal by changing the polarity of the
tip-and-ring lines. Polarity reversal is user-programmable to be either hard-coded or soft-
coded.
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In applications using ground-start-loop signaling, the B-MuSLIC can be set in the
ground- start mo de . In th is mode, th e tip wire is switched to h igh-impe dance mo de. The
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input voltage to the B-QAP is compared to a programmable threshold value in the B-
MuPP.
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Analog telephones are supplied with a DC current in the offhook state. AC speech
signals in the receive and transmit directions are superimposed on this DC current.
Once the offhook state has been detected, the B-SLIC must supply a DC current to the
subscriber lin e. The curre nt is typical ly in the ra nge of 1 4 to 40 mA, de pendin g o n local
country specifications. Conventional linecard solutions require additional hardware to
adjust th e DC feed curren t to meet d ifferent co untry specifica tions. By comparison, DC
feeding with the B-MuSLIC is fully programmable .
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Transversal and longitudinal currents on the subscriber line are sensed by the B-SLIC
and re por ted to the B-QAP . The curre nts a re separ ated , digi tize d, and fe d to the digital
DC characteristic of the B-Mu PP.
The B-MuSLIC DC-feed characteristic has 3 different zones: The constant-current zone,
the resistive zone, and the constant-voltage zone. A programmable voltage reserve can
be selecte d to avoid clippin g th e high AC signals (e.g. TTX).
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In the offhook state and under normal conditions, the feed current must be kept at a
constant value, independent of load. B-SLIC measures the DC current, and supplies this
I
TIP/RING
I
LIM
Constant
voltage zone
Programmable
voltage reserve V
RES
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information to the B-QAP via the IT pin (input pin for DC control). The B-MuPP compares
the actual current with the programmed value, and adjusts the B-SLIC drivers as
necessary. ITIP/RING in the constant-current zone is prog rammable from 0 to 70 mA.
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The resistive zone is used for very long lines wher e the battery voltage is incapable of
feeding a constant current to the line. In the B-MuSLIC, the resistance is programmable
from 0 to 1600 Ω.
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The constant-voltage zone is used in some applications to supply current through the
line. In this case, VTIP/RING is constant and the current depends on the load between the
tip-and-ring pins.
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If the battery voltage is not sufficient to supply the minimum required current through the
line even in the resistive zone, an auxiliary positive battery voltage, in addition to the
negative battery voltage VBAT, is used to expand the voltage swing between tip-and-ring
(booste d batte ry mod e). With this increa sed voltage range (VH to VBAT), it is possible to
supply the constant current through very long lines.
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Power dissipation is a critical component of all system design. The B-MuSLIC is
optimized to minimize power dissipation while keeping overall systems cost low through
the IVD approach. Power dissip ation in the B -MuSLIC chipset depen ds upo n a numbe r
of system parameters such as VBAT, loop length. and operating mode. ( 7DEOH )
* Dependent on loop length
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Idle 10 60 15 50 135
Data & Voice 2517 300 25 300 3142
Data Only 2550 250 25 300 3125
Voice Only * 850 -2050 150 25 50 1075 - 2275
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8QLW &RPPHQWV
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Hook Indication Active 0 - 50 1.50 mA Hysteresis 2mA
Line Supervision 0 - 50 1.50 mA Hysteresis 2mA
Ground Key Detection 0 - 50 1.50 mA Hig h/low current threshold
Ring trip detection 0 - 50 1.50 mA
Hook indication power down 0 - 5 0.15 mA
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Ringing frequency 0 - 80 2.00 Hz
Ringing offset 0 - 50 1.50 V
Ringing am plitud e:
programmable range I
programmable range II 0 - 20
20 - 90
2.00
1.00 VRMS
VRMS
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Constant current range 0 - 50 0.70 mA
Resistive range 0 - 1600 100.00 ΩExternal protection
excluded
Corner voltage:
programmable range I
programmable range II 0 - 60
60 - 120 1.50
3.00 V
V
Constant voltage:
programmable range I
programmable range II 0 - 60
60 - 120 1.50
3.00 V
V
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Hook indication 1.0 - 16.0 1. 00 ms The signal must be stable
for the given period
Ground key detection 4.0 - 64.0 4. 00 ms
General IO pins 1.0 - 16.0 1. 00 ms
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Impedance matching filters 1 real pole 1 real zero 1st
order WDF,
4th order FIR,
Digital gain factor,
Analog gain factor
Transhybrid filters 2 real poles 2 real zeroes,
2nd order WDF,
6th order FIR,
Digital gain factor
Equalizers 4th order FIR
Absolute gain -15 - +15
-30 - -15
+15 - +30
0.06
0.50
0.50
dB
dB
dB
2 tone generators
Frequency 200 - 2k 40.00 Hz
Amplitude -40 - 3.14 0.50 dB
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Frequency 12/16 kHz
Amplitude 0.5 - 2.5 0 .10 Vrms
1) Worst case stepsize for respective programing range.
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The opera tional descriptio n contains a brief ove rview of the operation of the B-Mu SLIC
chipset. The topics in this chapter are arran ge d as follows:
• 3 Ope rational Description
• 3.1 Active with Concurr ent Data and Voice Transmission
• 3.2 Active-voice -only
• 3.3 Ringing
• 3.4 Power-saving Modes
• 3.5 Subscriber Loo p Modes
• 3.6 Line Testin g
The B-MuSLIC generates an in ternal reset at system power-up to b egin initializing th e
chipset (Figure 3-1). The local controller then downloads setup values to the registers of
the B-MuPP and the ALiDD, and places the B-MuSLIC into powe r-down mode. Power-
down mode allows only essential loop monitoring activities in the B-SLIC to be
operation al. The local controlle r then proceeds to monito r the interrupt vectors of the B-
MuSLIC for loop activity, and respond appropriately for the type of signal and application
.
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Power On
HW Reset Reset
(all channels)
Download ALiDD Firmware
and setup
B-MuPP Registers
Power Down
All Channels
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Key Active Circuitry:
- ALiDD
- B-MuPP
- B-QAP
- B-SLIC DC, POTS AC, and ADSL-Lite AC
Possible Subscriber Activity
- ADSL-Lite Data Transmission
- POTS Signaling
- Voice Band AC Transmission
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Key Active Circuitry:
- B-MuPP
- B-QAP Voice Circuitry
- B-SLIC DC, POTS AC
Possible Subscriber Activity
- POTS Signaling
- Voice Band AC Transmission
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While in the active data and voice mode, the B-MuSLIC chipset can simultaneously
respond to all POTS signalling activity (ringing, hook status, etc.), send and receive voice
band AC transmission, and op erate a G.992.2-complian t AD SL-Lite modem.
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ALiDD supports the always-on state, meaning that there is no need to initiate a data
connection man ually whenever d ata traffic occu rs. The G.Lite data connectio n will stay
active. Different power modes (active, standby, power-down) can be use d.
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ALiDD supp orts the fast-retrain mode. Whe never line condition ch ange (e .g., transition
from onhook to offhook) for a longer period of time, the fast-retrain mode adapts the
G.Lite data connection to the new conditions in order to achieve higher performance and
higher data throughput.
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The active-voice-only mode is designed for linecard operation where the subscriber is
not supplie d with an A DSL-Lite se rvice. In th is mode, the A LiDD and po rtions of the B-
QAP are powered down, the only functional block is the voice path.
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The ringing sine wave is generated in the B-MuPP. The frequency and amplitude are
programmable between 16 and 70 Hz and up to 85 VRMS at the tip-and-ring wires,
respectively. The DC-offset voltage is programmable. When the ring-burst-on command
is sent to the B -MuPP, the sta rt (ring-b urst-on) a nd en d (r ing-pause) of the ring b urst is
automatica lly synchronized at the zero voltage crossing. If the DC current at the IT pin
exceeds the programmed value, offhook is detected within 2 periods of the ringing
signal, and ring burst is switched off. When off-hook is detected, the B-MuSLIC remains
in the ring-pa use mod e.
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The ringing voltage is generated by an external ring generator and connected to the tip-
and-ring line with an external relay. The B-MuSLIC has integrated functionality to control
the exte rnal ring relay with a zero volta ge ring burst and ring trip sign al.
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Preliminary Produ ct Ove rview 30 05.99
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In either power-down mode, power consumption is minimized by disabling all non-
required functions. The B-MuSLIC enters the power-down mode after a reset (including
a Power On reset) or by programming. If power-down is initiated via software, each
separate channel can operate in a different mode.
In power-down mode, the B-MuSLIC’s IOM-2 or µC programming interface is ready to
receive and transmit commands and data. The registers and coefficient RAM can be
loaded and read in this mode. Received voice data on the PCM, IOM-2, or Utopia-2
interface will be ign ored.
There are 2 p ower-down options:
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This power-down mode places 5 kΩ resistors from tip-and-ring to battery ground
(BGND) and the battery voltage (VBAT), respectively. These resistors allow loop activity
monitoring with minimal circuitry for POTS as well as remo te modem requests.
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This power-down mode provides a high impedance at tip-an d-ring.
If the PDNR mode has been selected, line supervision remains active. Any change of
line mode is reported via the hook bit in the IOM-2 data upstream channel or the B-MuPP
µC SCR8 register. To avoid spurious offhook information caused by longitudinal
induction, the hook bit is low-pass fi ltered.
An activate reque st from an ADSL- Lite modem issues an interrupt to the µC which has
to start the activation of that spe cific ADSL channel.
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Signaling in the subscriber loop is supervised internally by the B-MuSLIC chipset.
Supervision is performed by sensing the longitudinal and transverse line currents on the
tip-and-ring wires. The scaled values of these currents are generated in the B-SLIC, and
fed to the B-QAP via the IT an d IL pins.
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Loop-start signaling is the most common type of signaling. The subscriber loop is closed
by the hook switch inside th e subscrib er’s equipment.
In active mode , the transvers al loop curre nt is sensed b y the internal current sensor in
the B-SLIC. The IT pin of the B-SLIC indicates the loop current flow to the B-QAP. An
exte rna l resistor converts the current information to a voltage on th e IT pin.
The analog information is first converted to a digital value. It is then filtered and
processed to suppress line disturbances. If the result exceeds a programmable
threshold, an interrupt is gener ated to indicate off-hook detectio n.
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A similar mechanism is used in power-down mode. In this mode, the internal current
sensor is switched off to minimize power consumption. The loop current is therefore fed
and sensed th rough 5 kΩ resi stor s. The infor mation is ma de available at the IT pin and
interpreted by the B-QAP.
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A common method for ring-trip detection is to add a DC voltage to the ringing signal and
sense the transversal DC loop current. The B-SLIC automatically applies a
programmable DC offset to its internally-generated balanced ringing sign al.
The DC voltage for ring-trip detection can be generated by the B-MuSLIC chipset and
the internal ring-trip fun ctio n, even if an external ringin g generator is prese nt.
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In applications using ground-start-loop signaling, the B-MuSLIC can be set in the
ground-start mode. In this mode, the tip wire is switched to high-impedance mode. Ring-
ground detection is performed by the internal current sensor in the B-SLIC, and
transferre d to the B-QA P via the IT p in. The input voltag e to the B -QA P is compa red to
a progra mmable threshold val ue. After further pr ocessing (for example, de glitching the
status information from tip-and-ring wire through the use of a programmable persistency
counter), this infor mation generates an interru pt, and offhook detection is indicate d.
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Power-down PDNH Open / VBAT Non e None High impedance
PDNR Open / VBAT Of f -hook detect Off-hook,
DC transmit path 0 / VBAT
(via 5 k Ω)
Active ACT-V 0 / VBAT Voice and/or TTX
transmission
( no data )
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AC loop,
TTX generator (opt.)
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transmission
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TTX generator (opt.)
VBAT / 2
BB VH / VBAT Voice and/or TTX
transmission Buffer, sensor, DC+
AC loop,
TTX generator (opt.)
(VH+VBAT) / 2 1)
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Start VH / VBAT Voice and/or TTX
transmission Buffer, sensor, DC+
AC loop,
TTX generator (opt.)
RING:(VH+VBAT) / 2 1)
TIP: High impedance
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signal feed (incl.
DC offset)
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Special
Modes HIRT VH / VBAT e.g., Sensor off set
calibration Sensor, DC transmit
path High impedance
HIR VH / VBAT e.g., Li ne test (TIP) TIP buffer, sensor, DC
transmit path TIP: (VH+VBAT) / 2 1)
RING: high
impedance
HIT VH / VBAT e.g., Line test
(RING) RING buffer, sensor,
DC transmit path RING:(VH+VBAT) / 2 1)
TIP: high impedance
1) Plus diff. AC and DC signals via AC and DC interface
2) Plus diff. ring and DC signals via DC interface
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Subscriber loops are subject to many types of failure, and therefore have to be
monitored. This requires easy access to the subscriber loop to perform regular
measuremen ts. Line testing invol ves measuring resistance, lea kage, and ca pacitance,
and measurements of foreig n curre nts and volta ges.
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Conventional analog line cards in CO applications usually include 3 to 4 relays per
channel. On e relay is normally requ ired to switch an external ring ge nerator to the line,
and some applications need an additional relay for polarity reversal. Two test relays are
used to monitor the local loop (test-out relay) and to verify the line circuit itself (test-in
relay).
The test-out rela y switches an external test unit to the sub scriber line ( Figure 3-2) . The
external test un it measures ca pacitance, resista nce, and lea kage current, to d etect a ny
changes in the line co ndition or to detect any line failures.
The test in rela y makes it p ossible to switch a te st i mpedan ce to the SL IC, and th ereby
separate the subscriber line from the SLIC. With a test tone, it is possible to check the
entire linecard loop fro m the codec through the SLIC.
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By offering integrated test features in silicon, the B-MuSLIC chipset has the capability to
do all these tests without the need for an additional external test unit.
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When testing lin es with an extern al te st unit, e very li ne ha s to b e conne cte d separ ately
to the test unit, and the tests have to be done line-by-line, which can take several hours
for several thousand lines. Du e to the lo ng me asurement time, these tests a re typ ically
done once per week or once per month. Therefore, any failures are usually detected very
late. This drastically reduces the network qua lity for customers.
The absolute error in accuracy of all these line tests is typically 5%-10% or more because
the line para meters ( ε, µ, Z) are us ually unkno wn and can only be roughly estimated.
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The B-MuSL IC offers a variety of unique and flexible test features called ITDF.
ITDF includes:
• Integrate d su bscriber-line testing
• Integrate d co dec self-diagnostics
ITDF reduces testing time, lowers manufacturing cost, accelerates the test flow in the
field, and provides more flexibility for system manufacturers and their customers than
conventional line testing does. All these features are provided RQVLOLFRQ without the
need for a ny additional a nd exp ensive test equipment.
With the B-MuSLIC, usually only one relay is used for separating the line from the B-SLIC
and for switching a test impedance to the B-SLIC. This test impedance can also be used
for calibration. Two integrated tone generators can be used to send test tones to the
reference imp edance.
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Integrated Line Testing functions make it possible to monitor the status of the subscriber
loop remotely without any further test equipment. Compared to traditional testing, all
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these tests can be done in parallel. This shortens the total test time f or several thousand
lines to several seconds. It is therefore possible to perform periodic tests on the
subscriber loop, which means that the test time per line could be increased to several
minutes, for example. Line failures can be detected much earlier, making the network
much more reliable.
The B-MuSLIC has inte grated test functio ns to measure th e following line values:
– Subscriber-loop resistance, e.g., to localize short circuits (0 to 10 KΩ) (Figure 3-4)
– Isolation measurement with boosted battery to detect leakage currents on the line,
and to mon itor line qua lity (10 K Ω to 5 MΩ)
– Ringer capacitance
– Line capacitance (e.g., if the line breaks) (Figure 3-5 )
– Foreig n currents
The absolute error in accuracy is typically in the range of < 5 %, which is comparable to
measurements with external test units.
There are 2 important on-chip integrated test functions that formerly required external
devices. The first is the B-MuSLIC’s integrated ramp generator for testing ringer
capacitance. The second is the TTX signal generator, whose primary function is to
generate h igh frequency (up to 16 kHz) metering pu lses for billing purposes. It can also
be used to measure the onboard capacitance when the subscriber line is disconnected.
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Line testing with the B-MuSLIC is based on a voltage-feeding, current-sensing principle
(Figure 3- 4). An incoming PCM word i s converted to a voltage on the tip-and-ring line.
The load on the line affects the current flowing into it. This current is sensed via the B-
SLIC, and rele vant information is fed to the codec where it is transferred as a PCM-out-
word to the PCM highway. The DC-feed characteristic is switched off in the line-test
mode.
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Preliminary Produ ct Ove rview 36 05.99
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The same principle is also used for capacitance measurements (Figure 3-5). The only
difference is that for feeding the tip-and-ring line, no PCM-in-word is required, but the
internal r amp gen era tor can be use d for produ cing a time-varying trape zoidal sig nal fo r
capacitance mea surements.
.
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The current o n the tip-and-ring line i s proportion al to the derivative of the feed voltage.
The capacitance can be calculated directly by measuring the peak current and the
programmed feed voltage (Figure 3-6):
B-SLIC
Channel A
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B-QAP
PCM out
PCM in
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Preliminary Produ ct Ove rview 37 05.99
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The integrated codec self-diagnostic features can be used to perform a functional in-
spection of a complete analog linecard at the end of the manufacturing process. This
method has 2 important benefits. Test time is drastically reduced, and no additional, ex-
pensive test equipment is required except for 1 reference resistor with relays. The exter-
nal resistor and relay serve as an exte rnal reference.
The B-MuSLIC has inte grated test functio ns to measure th e following codec values:
• Various analog and digital loops to test the analog and digital interfaces of the linecard
• Digita l loop to test interface to codec (e.g. backplane)
• Digital loop for codec self-diag nosis
• Various analog loops to test the codec in pr oduction
• Level-me tering to test ring voltage, mete ring pulses, voice levels, an d noise (S/N).
• Automatic internal ALiDD diagnostics and self-tes t.
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Preliminary Produ ct Ove rview 38 05.99
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The B-MuSLIC chip set has several interfaces. The B-MuPP is controlled through either
an IOM-2 interface, o r a paralle l µC interfa ce . Voice d ata is se nt to/fro m th e B-MuPP in
the IOM-2 structure or though a PCM interface. The ALiDD is also controlled with a
parallel µC interface, and data is sent though a Utopia-2 interface with 8-bit data.
The topics in this chapter are arran ged as follows:
• 4.1 PCM Interface
• 4.2 IOM-2 Interface
• 4.3 Utopia-2 In terface
• 4.4 B-MuPP 8-bit Microcontroller Interface
• 4.5 ALiDD 8/16-bit Microcontroller Interface
• 4.6 Tip-and-r ing Interface
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Two serial P CM highways are us ed to transfer voice data. A PCM interface consists of
8 pins:
The Frame-Sync Clock (FSC) pulse identifies the beginning of a receive and transmit
frame for all 8 channels. The PCLK synchronizes data transfer on both lines DXA (DXB)
and DRA (DRB) to the PCM highways. Bytes in all channels are serialized to 8-bit width
with the MSB first.
The data rate of the interface can va ry from 2*51 2 kb/s to 2*8 192 kb/s (two hig hways).
7DEOH shows sample frequencies for the PCM interfa ce.
PCLK: PCM CLocK, 512 kHz to 8192 kHz
FSC: Frame Synchronization Cloc k, 8 kHz
DRA: Receive Data in put fo r PCM highway A
DRB: Receive Data in put fo r PCM highway B
DXA: Transmit Data output for PCM highway A
DXB: Transmit Data output for PCM highway B
TCA: Transmit Control output for PCM highway A, active low during transmission
TCB: Transmit Control output for PCM highway B, active low during transmission
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Preliminary Produ ct Ove rview 39 05.99
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The IOM-2 interface consists of 2 data lines and 2 clock lines. Data Upstream (DU)
carries data from the B-MuSLIC to a master device. Data Downstream (DD) carries data
from the master device to the B-MuSLIC. An 8-kHz FSC signal and a 4096-kHz Data
CLock (DCL) signal ha ve to be su pplied to the B-MuSLIC. The B-MuSL IC h andles data
as described in the IOM-21) specification fo r ana log devices.
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The ALiDD supports a complete 8-bit Utopia-2 interface as defined by ATM Forum
document UTOPIA Level 2, Version 1.0. The table below describes the pins used to
implement th e Utopia-2 interface on the ALiDD. The Utopia -2 interface allows up to 31
physical layer devices on a single interface. Using a proprietary in-band signaling
protocol, Infineon has added a feature to the standard Utopia-2 interface. This feature
allows connections for up to 124 physical layer devices.
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512 1 8 512
1024 2 8 512
1024 1 16 1024
2048 2 16 1024
2048 1 32 2048
4096 2 32 2048
4096 1 64 4096
8192 2 64 4096
8192 1 128 8192
1) Available on request from your local Infineon office
U_RxData [1:8]: Utopia Data Receive
U_TxData [1:8]: Utopia Data Transmit
U_RxADDR [1:5]: Utopia ADDRess Receive
U_TxADDR [1:5]: Utopia ADDRess Transmit
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Preliminary Produ ct Ove rview 40 05.99
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This parallel µC interface is used to communicate with exter nal master devices such as
lineca rd controllers. Th e B-MuPP µC interface consists of 6 control lines (AL E/DS, CS,
RD/RW, WR, DEMUX/MUX, INT/MOT), 8 bidirectional address/data lines (DIO0 to
DIO7), and 8 address lines (A0 to A7). The interface provides fast parallel data transfer
to a µC (Intel- and Motorola-compatible). It supports a multiplexed/non-multiplexed 8-bit
address/data bus, and connects to µCs of the Intel 8051-(MCS51/251-), Siemens C16X
and Motorola M68HCXX or M683XX families.
The following interface specifications can be selected usin g pin strapping:
• Intel multiplexed mode
• Intel demultip lexed mode
• Motorola mode
U_RxCLAV [0:3]: Receive Interface CelL AVailable
U_TxCLAV[0:3]: Transmit Interface CelL AVailable
U_RxENB: Receive ENaBle
U_TxEN B: Transmit ENaBle
U_RxSOC Receive interface Start Of Cell indication
U_TxSOC Transmit inte rface Star t Of Cell indication
U_RxCLK Receive interface Utopia CLocK
U_TxCLK Transmit inte rface Utopia CLocK
rx_data receive data within serial bypass mode (ATU to TC Logic Interface
according to G.992.2, if no ATM is used as high-layer protocol)
sbp_clk serial bypass clock
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000 00000, 00HChannel Preselect channel for channel-
specific commands BSOP , SO P,
TOP, COPI
000 00001, 01HStatus Status register to control the rea d/
write operations
000 00010, 02HInterrupt Reg ister
(Read Only) Indicates channel an d sources of
pending interrup ts
000 00011, 03HReset Reset the µC interface by writing
0AAH da ta to this address
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Preliminary Produ ct Ove rview 41 05.99
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The parallel interface of the ALiDD is similar to the one in the B-MuPP (Section 4.4), but
also offers a mode with a 16-bit-wide data bus (DIO0 to DIO15). After power-up, the
ALiDD µC interface is in 8-bit mode a nd can be config ured to 16-bit mode via a control
register.
The communication between ALiDD and the µC uses a mailbox interface with 2
mailboxes (send and receive), each 512x1 6 bits (7DEOH).
For communication from µC to ALiDD, e.g., a write operation, a byte or word of data has
to be written to the data register. Then the address has to be written to the write address
register. If additional data has to be sent, the address register is incremented
automatically so that only further data writes are necessary. A read operation is
performed similarly, but uses different registers. The configuration register makes it
possible to configure PLL, 8/16-bit host interface, and reset.
The ALIDD provides three types of µP buses that are selected via pin ALE. T
00000100, 04HReserved
00000101, 05HInterrupt Channel register 1 Indicate pending interrupts on
chan nels 0 to 7
00000110, 06HReserved
00000111, 07HData Data port for all regi ster
read/write operations
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00000000, 00Hread: Mailbox input data from ALiDD
write: Mailbox outp ut data to AL iDD
00000001, 01Hwrite: Mailbox address for write to AL iDD[9:2]
00000010, 02Hwrite: Mailbox address for write to AL iDD[1:0]
00000011, 03Hwrite: Mailbox addre ss for rea d from ALiDD[9:2]
00000100, 04Hwrite: Mailbox addre ss for rea d from ALiDD[1:0]
00000101, 05Hread: Host interrupt acknowle dged by ALiDD
write: Host status to ALiDD
00000110, 06Hread: ALiDD status register
00000111, 07Hread/write: Con figuration register
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Multiplexed A/D Demultip lexed A/D
8 bit Addr: AD(0:7)
Data: AD(0:7) Addr: A(0:7)
Data: AD(0:7)
16 bit Addr: AD(0:7)
Data: AD(0:15) Addr: A(0:7)
Data: AD(0:7
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Transfers addresses and data between the host and the
ALIDD.
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Transfers data between the host an d the ALIDD.
A(0:7) I $GGUHVV%XVQRQPXOWLSOH[HGPRGH
Input address to the ALIDD registers.
RD
DS
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This signal indicates a read operation.
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The rising edge marks the end of a valid read or write operation.
WR
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This signal indicates a write operation.
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A "1" identifies a valid host access as a read operation and a "0"
identifies it as a write operation.
CS I &KLS6HOHFW
A "0" on this line selects the ALIDD for a read/write ope ratio n.
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Preliminary Produ ct Ove rview 43 05.99
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The tip-and -ring interface con nects the subscriber l ine to the B- Mu SLIC. The interface
meets the ITU-T recommendation Q.552 for a Z-interface.
ALE I $GGUHVV/DWFK(QDEOH
A “1” on this line indicates an address on AD (0:7), that is latched
by the ALIDD (multiplexed mode only).
ALE also selects the interface mode (multiplexed or non-
multiplexed).
INT O (OD) ,QWHUUXSW5HTXHVW
This is the interrupt output line to the host for all mailbox interrupt
status requests. It is an open drain output.
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Preliminary Produ ct Overv iew 44 05.99
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The topics in this chapter are:
• 5.1 Typical Application Circuit (Figure 5-1)
• 5.2 Support Tools
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•
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• B-MuSLICOS Coefficient Calculating Software
• SMART3550 8 B-Mu SL IC Evaluation Board
• SMART55504 ALiDD Evaluation Board
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The B-MuSLICOS Coefficient Calculating Software is a project-oriented, Windows-
compatible program. It is designed to assist the user in developing sets of DSP filter
coefficients for different country and PTT requirements. The on-line help and structured
program flow guide the user through the coefficient calculation process.
RESET
ADCL
AFSC
ADD
ADU
IO1
IO2
IO3
IO4
ID0
ID1
ID2
ID3
A0
:
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DIO0
:
DIO7
CSQ
ALE
WRQ
RDQ
INTR
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INTQ/MOT
FSC
MCLK
TC1
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RESET
ADCL
AFSC
ADD
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ADCL
U_RxData 0:7
U_TxData 0:7
U_RxADDR 0:4
U_TxADDR 0:4
U_RxCLAV 0:3
U_TxCLAV 0:3
U_RxENBB
U_TxEMBB
U_TxSOC
U_RxSOC
U_RxCLK
U_TxCLK
rxdata
sbp_clk
GPIO’s
H_DAT 0:15
H_ADR 0:7
H_WR
H_RD
H_INT
H_CS
H_ALE
XTAL1
XTAL2
CLKO
RESET
Testmode
DGND AGND
DGND
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100n
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+2,5V
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Preliminary Produ ct Overv iew 45 05.99
B-MuSLICOS calculate s coe fficients for the following filters.
• AC Filter s
– Impedance matching to adapt the system to the required line impedance of the local
loop (return-loss calcula tion)
– Freque ncy response correctio n for both receive and transmit paths
– Level adjustment for both receive and transmit pa ths
– Transhybrid balancing
– 2 programmable tone generators.
• DC Filters
– DC-Feed characteristic (battery-feed characteristic values such as constant
current, resistive range, and constant range)
– Ringing signal
– Level metering
– TTX signals
– Threshold calculation for offhook and onhook.
After defining the required inputs for B-MuSLICOS, the user can start calculating the filter
coefficients. All calculation results are stored in the result file, which can be displayed by
the B-MuSLICOS program. Some of the calculations are also displayed graphically to
enable the product designer to verify the required behavior quickly, and make any
additional optimizations manu ally. The fo llowing calculations are displayed graphically:
• Return loss
• Input impedance
• Freque ncy respo nses in the receive and transmit paths
• Transhybr id loss
• DC characteristic
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The SMART 3550 8 and SMART 55 504 tool packages inclu de an evaluation board and
intuitive Windows-based software enabling simple configuration and programming of the
B-MuSLIC data and voice functions. Each evaluation tool gives complete access to all
data and voice interfaces, facilitating complete system performance measurements.
Either evaluation system can be connected to test equipment in order to measure the
transfer characteristics and to fine-tune system performance.
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Preliminary Produ ct Ove rview 46 05.99
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(Plastic Metric Quad Flat Package)
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Preliminary Produ ct Ove rview 47 05.99
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(Plastic Metric Quad Flat Package)
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Preliminary Produ ct Ove rview 48 05.99
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(Plastic Thin Quad Flat Packag e)
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Preliminary Produ ct Ove rview 49 05.99
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(Plastic Metric Quad Flat Pa ckage)
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Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information” . Dimensions in mm
SMD = Surface Mounted Device
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Package outlines for tubes, trays etc. are described in our
Data Book “Package Information” . Dimensions in mm
SMD = Surface-Mounted Device
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Preliminary Produ ct Ove rview 50 05.99
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AHV-S LIC Advanced High-Voltage SLIC
BB Boosted Battery
BORSCHT Battery feeding, Ov ervolta ge protection, Ringing, Signaling
(Supervision), Coding, Hybrid for 2/4-wire conversion, Testing
CO Central Office
COP Coefficien t Operation Command
COPI Coefficient Operation Initialize
DCL Data Clock Signal
DD Data Downstream
DRA (B) Receive Data input for PCM highway A (B)
DSP Digital Sign al Pro cessor
DTAG Deutsche Telecom AG
DTMF Dual Tone Multi Frequency
DU Data Upstream
DXA (B) Transmit Data for PCM highway A (B)
FSC Frame Synchro nization Clock
IOM ISDN-Oriented Module
IOM CI IOM Control Interface
ITDF Integrated Test and Diagnostic Functions
LSSGR Local area tra nsport access S witching System Gene ric
Requirements
µC MicroController
MSB Most Significant Bit
B-MuPP Broadband Multichannel Processor for POTS
B-MuSLIC Broadband Multichannel signal-processing Subscriber-Line Interface
Circuit
PBX Private Branch Exchange
PCLK PCM CLocK
PCM Pu lse Code Modulation
POTS Plain Old Telephone System
PSTN Public Switched Telephone Network
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Preliminary Produ ct Ove rview 51 05.99
B-QAP Broadband Qua d Analog frontend Processor
B-SLIC Broadband Subscriber Line Interface Circuit
SMD Surface-Mo un ted Devic e
SOP Status OPeration
TCA (B) Transmit Control outpu t for PCM highway A (B)
TG Tone Generator
TOP Transfer O Per ation
TTX TeleTaX
