PE29100
Document Category: Product Specification
UltraCMOS® High-speed FET Driver, 33 MHz
©2015-2017, Peregrine Semiconductor Corporation. All rights reserved. • Headquarters: 9380 Carroll Park Drive, San Diego, CA, 92121
Product Specification DOC-66216-5 – (02/2017)
www.psemi.com
Features
• High- and Low-side FET drivers
• Dead-time control
• Fast propagation delay, 8 ns
• Tri-state enable mode
• Sub-nanosecond rise and fall time
• 2A/4A peak source/sin k current
• Package – Flip chip
Applications
• DC–DC conversions
• AC–DC conversions
• Wireless power
• Class D amplifiers
Product Description
The PE29100 integrated high-speed driver is designed to control the gates of external power devices, such as
enhancement mode gallium nitride (eGaN®) FETs. The outputs of the PE29100 are capable of providing
switching transition speeds in the sub-nanosecond range for hard switching applications up to 33 MHz. High
switching speeds result in smaller peripheral components and enable new applications like the Rezence A4WP
wireless power transfer. The PE29100 is available in a flip chip package.
The PE29100 is manufactured on Peregrine’s UltraCMOS process, a patented advanced form of silicon-on-
insulator (SOI) technology, offering the performance of GaAs with the economy and integration of conventional
CMOS.
Figure 1 • PE29100 Functional Diagram
RDTL
GND
IN
EN
HSB
VDD
HSGPU
HSGPD
HSS
LSB
LSS
RDTH
LSO
LSGPU
LSGPD
Dead
Time
Controller
Logic
UVLO
Level
Shifter
Output
Driver
Level
Shifter
Output
Driver
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PE29100
High-speed FET Driver
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Absolute Maximum Ratings
Exceeding absolute maximum ratings listed in Table 1 may cause permanent damage. Operation should be
restricted to the limits in Table 2. Operation between operating range maximum and absolute maximum for
extended periods may reduce reliability.
ESD Precautions
When handling this UltraCMOS device, observe the same precautions as with any other ESD-sensitive devices.
Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to
avoid exceeding the rating specified in Table 1.
Latch-up Immunity
Unlike conventional CMOS devices, UltraCMOS devices are immune to latch-up.
Table 1 • Absolute Maximum Ratings for PE29100
Parameter/Condition Min Max Unit
Low-side bias (LSB) to low-side source (LSS) –0.3 6 V
High-side bias (HSB) to high-side source (HSS) –0.3 6 V
Input signal –0.3 6 V
HSS to LSS –1 100 V
ESD voltage HBM(*), all pins 25 V
Note: * Human body mo de l (MIL -STD 883 Method 30 15 ).
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PE29100
High-speed FET Driver
Recommended Operating Conditions
Table 2 lists the recommended operating conditions for the PE29100. Devices should not be operated outside
the recommended operating conditions listed below.
Electrical Specifications
Table 3 provides the key electrical specifications @ +25 °C, VDD = 5V, load = 2. 2Ω resistor in series with 100 pF
capacitor, HSB and LSB bootstrap diode included, unless otherwise specified.
Table 2 • Recommended Operating Conditions for PE29100
Parameter Min Typ Max Unit
Supply for driver front-end, VDD 4.0 5.0 5.5 V
Supply for high-side driver, HSB 3.7 5.0 5.5 V
Supply for low-side driver, LSB 3.7 5.0 5.5 V
Logic HIGH for control input 1.6 5.5 V
Logic LOW for control input 0 0.5 V
HSS range 0 80 V
Minimum input pulse width 10 ns
Operating temperature –40 +105 °C
Junction temperature –40 +125 °C
Table 3 • DC Characteristics
Parameter Condition Min Typ Max Unit
DC Characteristics
VDD quiescent current VDD = 5V 34.0mA
HSB quiescent current VDD = 5V 2.5 3.4 mA
LSB quiescent current VDD = 5V 2.5 3.4 mA
Under Voltage Lockout
Under voltage release (risi ng) 3.1 3.6 4.3 V
Under voltage hysteresis 200 mV
Gate Drivers
HSGPU/LSGPU pull-up resistan ce 1.2 Ω
HSGPD/LSGPD pull-down resistance 0.5 Ω
HSGPU/LSGPU leakage current HSB–HSGPU = 5.5V/LSB–LSGPU = 5.5V 10 µA
HSGPD/LSGPD leakage current HSGPD–HSS = 5.5V/LSGPD–HSS = 5.5V 10 µA
Dead-time Control
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High-speed FET Driver
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Control Logic
Table 4 provides the control logic truth table for the PE29100.
Dead-time control voltages 30k to 80 kΩ resistor to GND 1.2 V
Dead-time from HSG going low to
LSG going high RDHL = 30 kΩ0.8 ns
RDHL = 80 kΩ3.4 ns
Dead-time from LSG going low to
HSG going high RDLH = 30 kΩ0.8 ns
RDLH = 80 kΩ3.2 ns
Switching Characteristics
LSG turn-off propagation delay At min dead time 8.4 ns
HSG rise time 10%–90% 1.0 1.2 ns
10%–90% with 1000 pF load 2.5
LSG rise time 10%–90% 1.0 1.2 ns
10%–90% with 1000 pF load 1.8
HSG fall time 10%–90% 0.9 1.0 ns
10%–90% with 1000 pF load 2.5
LSG fall time 10%–90% 0.9 1.0 ns
10%–90% with 1000 pF load 1.8
Max switching frequency @ 50%
duty cycle RDHL = RDLH = 80 kΩ33 MHz
Table 3 • DC Characteristics (Cont.)
Parameter Condition Min Typ Max Unit
Table 4 • Truth Table for PE29100
EN IN HSGPU–HSS HSGPD–HSS LSGPU–LSS LSGPD–LSS
L L Hi–Z L H Hi–Z
L H H Hi–Z Hi–Z L
H L Hi–Z L Hi–Z L
H H Hi–Z L Hi–Z L
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PE29100
High-speed FET Driver
Typical Performance Data
Figure 2–Figure 4 show the typical performance data @ +25 °C, VDD = 5V, load = 2.2Ω resistor in series with
100 pF capacitor, HSB and LSB bootstrap diode included, unless otherwise specified.
Figure 2 • Quiescent Current vs Temperature
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
-50-25 0 255075100125
Current (mA)
Temperature (°C)
VDDA LSB HSB
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High-speed FET Driver
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Figure 3 • UVLO Threshold vs Temperature
3.40
3.45
3.50
3.55
3.60
3.65
3.70
-50 -25 0 25 50 75 100 125
Threshold (V)
Temperature (°C)
UVLO Rising UVLO Falling
Figure 4 • Dead-time vs Temperature
0
2
4
6
8
10
12
14
-50 -25 0 25 50 75 100 125
Dead-time (ns)
Temperature (°C)
TDLH 30K TDHL 30K TDLH 80.6K
TDHL 80.6K TDLH 255K TDHL 255K
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PE29100
High-speed FET Driver
Test Diagram
Figure 5 shows the test circuit used for obtaining measurements. The two bootstrap diodes shown in the
schematic are used for symmetry purposes in characterization. In practice, only the HSB diode is required.
Removing the LSB diode will result in higher low-side supply voltage since the diode drop is eliminated. As a
result, the dead-time resistor can be adjusted to compensate for any changes in propagation delay.
Figure 5 • Test Circuit for PE29100
RDTL
GND
PWM
EN
HSB
VDD VDD
HSGPU
HSGPD
HSS
LSB
LSS
RDTH
Level
Shifter
LSO
VIN
LSGPU
LSGPD
Dead
Time
Controller
Logic
UVLO
Output
Driver
Level
Shifter
Output
Driver
HSG
LSG
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PE29100
High-speed FET Driver
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Theory of Operation
General
The PE29100 is intended to drive both the high-side (HS) and the low-side (LS) gates of external power FETs,
such as eGaN FETs, for power management applications. The PE29100 favors applications requiring higher
switching speeds due to the reduced parasitic properties of the high resistivity insulating substrate inherent with
Peregrine’s UltraCMOS process.
The driver uses a single-ended pulse width modulation (PWM) input that feeds a dead-time controller, capable
of generating a small and accurate dead-time. The dead-time circuit prevents shoot-through current in the
output stage. The propagation delay of the dead-time controller must be small to meet the fast switching require-
ments when driving eGaN FETs. The differential outputs of the dead-time controller are then level-shifted from a
low-voltage domain to a high-voltage domain required by the output drivers.
Each of the output drivers includes two separate pull-up and pull-down outputs allowing independent control of
the turn-on and turn-off gate loop resistance. The low impedance output of the drivers improves external power
FETs switching speed and efficiency, and minimizes the effects of the voltage rise time (dv/dt) transients.
Under-voltage Lockout
An internal under-voltage lockout (UVLO) feature prevents the PE29100 from powering up before input voltage
rises above the UVLO threshold of 3.6V (typ), and 200 mV (typ) of hysteresis is built in to prevent false
triggering of the UVLO circuit. The UVLO must be cleared and the EN pin must be released before the part will
be enabled.
Dead-time Adjustment
The PE29100 features a dead-time adjustment that allows the user to control the timing of the LS and HS gates
to eliminate any large shoot-through currents, which could dramatically reduce the efficiency of the circuit and
potentially damage the eGaN FETs. Two external resistors control the timing of outputs in the dead-time
controller block. The timing waveforms are illustrated in Figure 6.
The dead-time resistors only affect the LS output; the HS output will always equal the duty-cycle of the input.
The HS FET gate node will track the duty cycle of the PWM input with a shift in the response, as both rising and
falling edges are shifted in the same direction. The LS FET gate node duty cycle can be controlled with the
dead-time resistors as each resistor will move the rising and falling edges in opposite directions. RDLH will
change the dead-time from low-side gate (LSG) falling to high-side gate (HSG) rising and RDHL will change the
dead-time from HSG falling to LSG rising. Figure 7 shows the resulting dead-time versus the external resistor
values with both HS and LS bias diode/capacitors installed as indicated in Figure 2. The LS bias diode and
capacitor is included for symmetry only and is not required for the part to function. Removing the LS bias diode
will increase the LSG voltage by approximately 0.3V, resulting in a wider separation of the tDHL and tDLH curves in
Figure 7.
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PE29100
High-speed FET Driver
Figure 6 and Figure 7 provide the dead-time description for the PE29100.
Figure 6 • Dead-time Description
IN
HSG-HSS
LSG-LSS tDHL
tDLH
Figure 7 • Dead-time vs Dead-time Resistor
0
2
4
6
8
10
12
14
0 50 100 150 200 250 300
Dead-time Between HSG & LSG (ns)
Dead-time Resistance (kΩ)
TDLH TDHL
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PE29100
High-speed FET Driver
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Application Circuit
Figure 8 shows a typical application diagram of the PE29100 and its external components in a half-bridge
configuration(*). The PE29100 is designed to provide a LS gate driver, referenced to ground, and a floating HS
gate driver referenced to the switch node (HSS). A common technique to generate the floating HS gate drive
uses a bootstrap diode in conjunction with a decoupling capacitor. However, if the LS device conducts currents
through its body diode durin g the dead-time period, an overvoltage condition across the b ootstrap capacitor can
result.
A more elegant approach replaces the HS bootstrap diode with an eGaN FET (Q4). The EPC2038 is used as a
synchronous bootstrap FET to prevent overvoltage of the HS device. The EPC2038 includes an internal diode
and prevents the bootstrap capacitor from overcharging during the dead-time periods. This is accomplished by
synchronously switching Q4 using the LSG signal so that Q4 turns on and charges the bo otstrap capacitor wh en
LSG is high, but turns off as soon as LSG turns low so that no inadvertent bootstrap overcharging occurs during
the dead-time periods.
The external gate resistors are required to de-Q the inductance in the gate loop and dampen any ringing on the
FET gates and the SW node.
Dead-time resistors RDHL and RDLH can be adjusted to compensate for any changes in propagation delay.
Note: * For applications greater than 30V in a half-bridge configuration, the PE29100 can be sensitive to high dv/dt conditions on HSS.
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PE29100
High-speed FET Driver
Figure 8 • Applications Diagram for PE29100
RDTL
GND
IN
EN
HSB
VDD
HSGPU
HSGPD
HSS
LSB
LSS
RDTH
Level
Shifter
LSO
LSGPU
LSGPD
Dead
Time
Controller
UVLO
Level
Shifter
Q4
DGINT
Q1
VSW
VDD
Q5
CB
Logic
VIN
Output
Driver
Output
Driver
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PE29100
High-speed FET Driver
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Evaluation Board
The PE29100 evaluation board (EVB) was designed to ease customer evaluation of the PE29100 gate driver.
The EVB is assembled with a PE29100 driver and two EPC8009 eGaN FETs in a half-bridge configuration. VDD
is applied at J1 to bias the driver. VIN is applied to the multipin connector, J3, to supply power to the GaN FETs.
A PWM signal with an adjustable duty cycle is applied to J2 as the input. VIN can be monitored at test points E1
and E2, while the DC output can be monitored at test points E3 and E4. The switched output node can be
observed on an oscilloscope at J3.
Because the PE29100 is capable of generating fast switching speeds, the printed circuit boa rd (PCB) la yout is a
critical component of the design. The layout should occupy a small area with the power FETs and external
bypass capacitors placed as close as possible to the driver to reduce any resonances associated with the gate
loops, common source and power loop inductances. Since the maximum allowable gate-to-source voltage for
eGaN FETs is 6V, resonance in the gate loops can generate ringing that can degrade the performance and
potentially damage the power devices due to high voltage spikes. Additionally, it is important to keep ground
paths short.
The PCB is fabricated on FR4 material, with a total thickness of 0.062 inches. A minimum copper thickness of 1
ounce or more is recommended on the PCB outer layers to limit resistive losses and improve thermal spreading.
Figure 9 • Evaluation Kit Layout for PE29100
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PE29100
High-speed FET Driver
Pin Configuration
This section provides pin information for the
PE29100. Figure 10 shows the pin map of this device
for the available package. Table 5 provides a
description fo r each pin.
Figure 10 • Pin Configuration (Bumps Up)
NCHSBHSSHSGPD
HSGPU
LSGPU
LSG
PD
LSS LSB V
DD
RDHL
GND
INEN
LSO
RDLH
5
8
11
1615141312
9
6
1234
7
10
Table 5 • Pin Descriptions for PE29100
Pin No. Pin
Name Description
1HSGPD High-side gate drive pull-down
2 HSS High-side source
3 HSB High-side bias
4 NC No connect (tie to board ground)
5 RDLH Dead-time control resistor sets LSG
falling to HSG rising delay (external
resistor to GND)
6HSGPU High-side gate drive pull-up
7EN
Enable active low, tri-state outputs
when high
8 IN Control input
9LSGPU Low-side gate drive pull-up
10 LSO Look ahead for LSGPU. LSO pre-
cedes LSGPU and LSGPD by 4 ns.
11 GND Ground
12 LSGPD Low-side gate drive pull-down
13 LSS Low-side source
14 LSB Low-side bias
15 VDD +5V supply voltage
16 RDHL Dead-time control resistor sets HSG
falling to LSG rising delay (external
resistor to ground)
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PE29100
High-speed FET Driver
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Die Mechanical Specifications
This section provides the die mechanical specifications for the PE29100.
Table 6 • Die Mechanical Specifications for PE29100
Parameter Min Typ Max Unit Test Condition
Die size, singulated (x,y) 2040 × 1640 µm Including sapphire,
max tolerance = –20/+30
Wafer thickness 180 200 200 µm
Wafer size µm
Bump pitch 400 µm
Bump height 85 µm
Bump diameter 110 µm max tolerance = ±17
Table 7 • Pin Coordinates for PE29100(*)
Pin # Pin Name Pin Center (µm)
X Y
1HSGPD –800 600
2 HSS –400 600
3HSB0600
4 NC 400 600
5 RDLH 800 600
6HSGPU –800 200
7EN400 200
8 IN 800 200
9LSGPU –800 –200
10 LSO 400 –200
11 GND 800 –200
12 LSGPD –800 –600
13 LSS –400 –600
14 LSB 0 –600
15 VDD 400 –600
16 RDHL 800 –600
Note: * All pin locations originate from the die center and refer to the
center of the pin.
Figure 11 • Pin Layout for PE29100(1)(2)
Notes:
1) Drawings are not drawn to scale.
2) Singulate d die size sh ow n, bu mp side up .
NC
1640 µm (−20 / +30 µm)
2040 µm (−20 / +30 µm)
HSBHSSHSGPD
HSGPU
LSGPU
LSG
PD
LSS LSB V
DD
RDHL
GND
INEN
LSO
RDLH
5
8
11
1615141312
9
6
1234
7
10
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PE29100
High-speed FET Driver
Figure 12 • Recommended Land Pattern for PE29100
BUMPS DOWN
SIDE VIEW
BUMPS UP
2.040+0.03
-0.02
1.640+0.03
-0.02
0.22
(x14)
0.40
0.085±0.013
RECOMMENDED LAND PATTERN
0.40
0.20±0.02
Ø0.090±0.008
(x16)
Ø0.110±0.017
(x16)
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PE29100 High-speed FET Driver
Product Specification www.psemi.com DOC-66216-5 – (02/2017)
Document Categories
Advance Information
The product is in a formative or design stage. The datasheet contains design target specifications for product development. Specifications and
features may change in any manner without notice.
Preliminary Specification
The datasheet contains preliminary data. Additional data may be added at a later date. Peregrine reserves the right to change specifications at any
time without notice in order to supply the best possible product.
Product Specification
The datasheet contains final data. In the event Peregrine decides to change the specifications, Peregrine will notify customers of the intended
changes by issuing a CNF (Customer Notification Form).
Sales Contact
For additional information, contact Sales at sales@psemi.com.
Disclaimers
The information in this document is believed to be reliable. However, Peregrine assumes no liability for the use of this information. Use shall be
entirely at the user’s own risk. No patent rights or licenses to any circuits described in this document are implied or granted to any third party.
Peregrine’s products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to
support or sustain life, or in any application in which the failure of the Peregrine product could create a situation in which personal injury or death
might occur. Peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in
such applications.
Patent Statement
Peregrine products are protected under one or more of the following U.S. patents: patents.psemi.com
Copyright and Trademark
©2015-2017, Peregrine Semiconductor Corporation. All rights reserved. The Peregrine name, logo, UTSi and UltraCMOS are registered trade-
marks and HaRP, MultiSwitch and DuNE are trademarks of Peregrine Semiconductor Corp.
Ordering Information
Table 8 lists the available ordering code for the PE29100.
Table 8 • Order Code for PE29100
Order Codes Description Packaging Shipping Method
PE29100A-X PE29100 flip chip Die on tape and reel 500 units/T&R
PE29100A-Z PE29100 flip chip Die on tape and reel 3000 units/T&R
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