19-1304; Rev 0; 10/97 Low-Power, Dual, 13-Bit Voltage-Output DACs with Configurable Outputs ____________________________Features 13-Bit Dual DAC with Configurable Output Amplifier Single-Supply Operation: +5V (MAX5152) +3V (MAX5153) Rail-to-Rail Output Swing Low Quiescent Current: 500A (normal operation) 2A (shutdown mode) Power-On Reset Clears DAC Outputs to Zero SPI/QSPI and Microwire Compatible Space-Saving 16-Pin QSOP Package Pin-Compatible 12-Bit Versions: MAX5156/MAX5157 ______________Ordering Information PIN-PACKAGE INL (LSB) 0C to +70C 16 Plastic DIP 1/2 0C to +70C 16 Plastic DIP 1 MAX5152ACEE 0C to +70C 16 QSOP 1/2 MAX5152BCEE 0C to +70C 16 QSOP 1 MAX5152BC/D 0C to +70C Dice* 1 PART TEMP. RANGE MAX5152ACPE MAX5152BCPE ________________________Applications Industrial Process Control Motion Control Digital Offset and Gain Adjustment Digitally Programmable 4-20mA Current Loops Remote Industrial Controls Automatic Test Equipment Ordering Information continued at end of data sheet. *Dice are tested at TA = +25C, DC parameters only. Pin Configuration appears at end of data sheet. _________________________________________________________Functional Diagram DOUT CL PDL DECODE CONTROL DGND INPUT REG A AGND VDD DAC REG A 16-BIT SHIFT REGISTER REFA DAC A MAX5152 MAX5153 LOGIC OUTPUT INPUT REG B DAC REG B DAC B DIN FBA OUTB FBB SR CONTROL CS OUTA SCLK UPO REFB Rail-to-Rail is a registered trademark of Nippon Motorola Ltd. SPI and QSPI are trademarks of Motorola, Inc. Microwire is a trademark of National Semiconductor Corp. ________________________________________________________________ Maxim Integrated Products 1 For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. For small orders, phone 408-737-7600 ext. 3468. MAX5152/MAX5153 _______________General Description The MAX5152/MAX5153 low-power, serial, voltage-output, dual 13-bit digital-to-analog converters (DACs) consume only 500A from a single +5V (MAX5152) or +3V (MAX5153) supply. These devices feature Rail-toRail(R) output swing and are available in space-saving 16-pin QSOP and DIP packages. Access to the inverting input allows for specific gain configurations, remote sensing, and high output current capability, making these devices ideally suited for industrial process controls. These devices are also well suited for digitally programmable (4-20mA) current loops. The 3-wire serial interface is SPITM/QSPITM and MicrowireTM compatible. Each DAC has a doublebuffered input organized as an input register followed by a DAC register, which allows the input and DAC registers to be updated independently or simultaneously. Additional features include a programmable shutdown (2A), hardware-shutdown lockout, a separate voltage reference for each DAC, power-on reset, and an activelow clear input (CL) that resets all registers and DACs to zero. The MAX5152/MAX5153 provide a programmable logic output pin for added functionality, and a serial-data output pin for daisy chaining. MAX5152/MAX5153 Low-Power, Dual, 13-Bit Voltage-Output DACs with Configurable Outputs ABSOLUTE MAXIMUM RATINGS VDD to AGND............................................................-0.3V to +6V VDD to DGND ...........................................................-0.3V to +6V AGND to DGND ..................................................................0.3V FBA, FBB to AGND.....................................-0.3V to (VDD + 0.3V) REF_, OUT_ to AGND.................................-0.3V to (VDD + 0.3V) Digital Inputs (SCLK, DIN, CS, CL, PDL) to DGND ................................................................-0.3V to +6V Digital Outputs (DOUT, UPO) to DGND .....-0.3V to (VDD + 0.3V) Maximum Current into Any Pin .........................................20mA Continuous Power Dissipation (TA = +70C) Plastic DIP (derate 10.5mW/C above +70C) .............593mW QSOP (derate 8.30mW/C above +70C) .....................667mW CERDIP (derate 10.00mW/C above +70C) ................800mW Operating Temperature Ranges MAX5152_C_E/MAX5153_C_E ...........................0C to +70C MAX5152_E_E/MAX5153_E_E..........................-40C to +85C MAX5152_MJE/MAX5153_MJE ......................-55C to +125C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10sec) .............................+300C Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS--MAX5152 (VDD = +5V 10%, VREFA = VREFB = 2.5V, RL = 10k, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C, output buffer connected in unity-gain configuration (Figure 9).) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS STATIC PERFORMANCE Resolution N 13 Bits MAX5152A 1/2 MAX5152B 1 Integral Nonlinearity INL (Note 1) Differential Nonlinearity DNL Guaranteed monotonic 1 Offset Error VOS Code = 20 6 Offset Tempco TCVOS Normalized to 2.5V 3 Gain Error -0.5 Gain-Error Tempco VDD Power-Supply Rejection Ratio PSRR Normalized to 2.5V 3 4.5V VDD 5.5V 20 LSB LSB mV ppm/C 6 LSB ppm/C 200 V/V VDD 1.4 V REFERENCE INPUT Reference Input Range REF Reference Input Resistance RREF 0 Minimum with code 1555 hex 14 20 k MULTIPLYING-MODE PERFORMANCE Reference 3dB Bandwidth Input code = 1FFF hex, VREF = 0.67Vp-p at 2.5VDC 600 kHz Reference Feedthrough Input code = 0000 hex, VREF = (VDD - 1.4Vp-p) at 1kHz -85 dB Input code = 1FFF hex, VREF = 1Vp-p at 2.5VDC, f = 25kHz 82 dB Signal-to-Noise plus Distortion Ratio SINAD DIGITAL INPUTS Input High Voltage VIH CL, PDL, CS, DIN, SCLK Input Low Voltage VIL CL, PDL, CS, DIN, SCLK Input Hysteresis VHYS Input Leakage Current IIN Input Capacitance CIN 2 3.0 V 0.8 200 VIN = 0V to VDD 0.001 8 _______________________________________________________________________________________ V mV 1 A pF Low-Power, Dual, 13-Bit Voltage-Output DACs with Configurable Outputs (VDD = +5V 10%, VREFA = VREFB = 2.5V, RL = 10k, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C, output buffer connected in unity-gain configuration (Figure 9).) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DIGITAL OUTPUTS (DOUT, UPO) Output High Voltage VOH ISOURCE = 2mA Output Low Voltage VOL ISINK = 2mA VDD 0.5 V 0.13 0.40 V DYNAMIC PERFORMANCE Voltage Output Slew Rate SR Output Settling Time To 1/2LSB of full-scale, VSTEP = 2.5V Output Voltage Swing Rail-to-rail (Note 2) Current into FBA or FBB V/s 20 s 0 to VDD IFB_ 0 Time Required to Exit Shutdown CS = VDD, fDIN = 100kHz, VSCLK = 5Vp-p Digital Feedthrough 0.75 Digital Crosstalk V 0.1 A 25 s 5 nV-s 5 nV-s POWER SUPPLIES Positive Supply Voltage VDD Power-Supply Current IDD Power-Supply Current in Shutdown 4.5 (Note 3) IDD(SHDN) (Note 3) Reference Current in Shutdown 5.5 V 0.5 0.65 mA 2 10 A 1 A TIMING CHARACTERISTICS SCLK Clock Period tCP 100 ns SCLK Pulse Width High tCH (Note 4) 40 ns SCLK Pulse Width Low tCL 40 ns CS Fall to SCLK Rise Setup Time tCSS 40 ns SCLK Rise to CS Rise Hold Time tCHS 0 ns DIN Setup Time tDS 40 ns DIN Hold Time tDH 0 ns SCLK Rise to DOUT Valid Propagation Delay tDO1 CLOAD = 200pF 80 ns SCLK Fall to DOUT Valid Propagation Delay tDO2 CLOAD = 200pF 80 ns SCLK Rise to CS Fall Delay tCS0 10 ns CS Rise to SCLK Rise Hold tCS1 40 ns CS Pulse Width High tCSW 100 ns Note 1: Accuracy is specified from code 20 to code 8191. Note 2: Accuracy is better than 1LSB for VOUT greater than 6mV and less than VDD - 50mV. Guaranteed by PSRR test at the end points. Note 3: Digital inputs are set to either VDD or DGND, code = 0000 hex, RL = . Note 4: SCLK minimum clock period includes rise and fall times. _______________________________________________________________________________________ 3 MAX5152/MAX5153 ELECTRICAL CHARACTERISTICS--MAX5152 (continued) MAX5152/MAX5153 Low-Power, Dual, 13-Bit Voltage-Output DACs with Configurable Outputs ELECTRICAL CHARACTERISTICS--MAX5153 (VDD = +2.7V to +3.6V, VREFA = VREFB = 1.25V, RL = 10k, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C, output buffer connected in unity-gain configuration (Figure 9).) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS STATIC PERFORMANCE Resolution N 13 Integral Nonlinearity INL (Note 5) Differential Nonlinearity DNL Guaranteed monotonic VOS Code = 40 Offset Error Offset Tempco TCVOS MAX5153A 1 MAX5153B 2 1 6 Normalized to 1.25V 6 Gain Error -0.5 Gain-Error Tempco VDD Power-Supply Rejection Ratio Bits PSRR Normalized to 1.25V 6 2.7V VDD 3.6V 20 LSB LSB mV ppm/C 8 LSB ppm/C 320 V/V VDD 1.4 V REFERENCE INPUT (VREF) Reference Input Range REF Reference Input Resistance RREF 0 Minimum with code 1555 hex 14 k MULTIPLYING-MODE PERFORMANCE Reference 3dB Bandwidth Input code = 1FFF hex, VREF(AC) = 0.67Vp-p at 1.25VDC 600 kHz Reference Feedthrough Input code = 0000 hex, VREF = (VDD - 1.4V) at 1kHz -92 dB Input code = 1FFF hex, VREF = 1Vp-p at 1.25VDC, f = 15kHz 73 dB Signal-to-Noise plus Distortion Ratio SINAD DIGITAL INPUTS Input High Voltage Input Low Voltage Input Hysteresis VIH CL, PDL, CS, DIN, SCLK VIL CL, PDL, CS, DIN, SCLK 2.2 0.8 VHYS Input Leakage Current IIN Input Capacitance CIN V 200 VIN = 0V to VDD 0 V mV 0.1 8 A pF DIGITAL OUTPUTS (DOUT, UPO) Output High Voltage VOH ISOURCE = 2mA Output Low Voltage VOL ISINK = 2mA 4 VDD - 0.5 V 0.13 _______________________________________________________________________________________ 0.4 V Low-Power, Dual, 13-Bit Voltage-Output DACs with Configurable Outputs (VDD = +2.7V to +3.6V, VREFA = VREFB = 1.25V, RL = 10k, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C, output buffer connected in unity-gain configuration (Figure 9).) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DYNAMIC PERFORMANCE Voltage Output Slew Rate SR Output Settling Time To 1/2LSB of full-scale, VSTEP = 1.25V Output Voltage Swing Rail-to-rail (Note 6) Current into FBA or FBB IFB_ V/s 25 s 0 to VDD V 0 Time Required to Exit Shutdown CS = VDD, fDIN = 100kHz, VSCLK = 3Vp-p Digital Feedthrough 0.75 Digital Crosstalk 0.1 A 25 s 5 nV-s 5 nV-s POWER SUPPLIES Positive Supply Voltage VDD Power-Supply Current IDD Power-Supply Current in Shutdown 2.7 (Note 7) IDD(SHDN) (Note 7) Reference Current in Shutdown 3.6 V 0.5 0.6 mA 1 8 A 1 A TIMING CHARACTERISTICS SCLK Clock Period tCP 100 ns SCLK Pulse Width High tCH (Note 4) 40 ns SCLK Pulse Width Low tCL 40 ns CS Fall to SCLK Rise Setup Time tCSS 40 ns SCLK Rise to CS Rise Hold Time tCHS 0 ns DIN Setup Time tDS 50 ns DIN Hold Time tDH 0 ns SCLK Rise to DOUT Valid Propagation Delay tDO1 CLOAD = 200pF 120 ns SCLK Fall to DOUT Valid Propagation Delay tDO2 CLOAD = 200pF 120 ns SCLK Rise to CS Fall Delay tCS0 10 ns CS Rise to SCLK Rise Hold tCS1 40 ns CS Pulse Width High tCSW 100 ns Note 4: SCLK minimum clock period includes rise and fall times. Note 5: Accuracy is specified from code 40 to code 8191. Note 6: Accuracy is better than 1LSB for VOUT greater than 6mV and less than VDD - 100mV. Guaranteed by PSRR test at the end points. Note 7: Digital inputs are set to either VDD or DGND, code = 0000 hex, RL = . _______________________________________________________________________________________ 5 MAX5152/MAX5153 ELECTRICAL CHARACTERISTICS--MAX5153 (continued) __________________________________________Typical Operating Characteristics (VDD = +5V, RL = 10k, CL = 100pF, FB_ tied to OUT_, TA = +25C, unless otherwise noted.) MAX5152 SUPPLY CURRENT vs. TEMPERATURE CODE = 1FFF (HEX) -8 -10 -12 -14 VREF = 1Vp-p AT 2.5VDC CODE = 1FFF (HEX) 10 100 0.55 0.50 CODE = 0000 (HEX) -50 -60 -70 0.45 VREF = 0.67Vp-p AT 2.5VDC CODE = 1FFF (HEX) -18 -80 -20 0.40 1200 1800 2400 3000 -90 -60 FREQUENCY (kHz) -20 20 60 100 140 0 TEMPERATURE (C) FREQUENCY (kHz) POWER-DOWN CURRENT vs. TEMPERATURE REFERENCE FEEDTHROUGH AT 1kHz FULL-SCALE ERROR vs. LOAD -50 MAX5152 TOC04 0 VREF = 2.5V -0.4 -0.6 VREF = 3.6Vp-p AT 1.88VDC CODE = 0000 (HEX) -70 RELATIVE OUTPUT (dB) -0.2 -60 -80 -90 -100 -110 -120 -130 -0.8 3.0 POWER-DOWN CURRENT (A) 600 MAX5152-TOC05 0 MAX5152 TOC06 -16 FULL-SCALE ERROR (LSB) -40 THD + NOISE (dB) -6 -30 MAX5152 TOC02 RL = SUPPLY CURRENT (mA) -4 RELATIVE OUTPUT (dB) 0.60 MAX5152 TOC01 0 -2 TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY MAX5152 TOC03 REFERENCE VOLTAGE INPUT FREQUENCY RESPONSE 2.5 2.0 1.5 1.0 0.5 -140 0.1 1 10 100 1000 OUTPUT FFT PLOT -30 5 25 45 MAX5152 TOC09 CS 5V/div AC COUPLED CS 5V/div AC COUPLED -40 OUT_ 500mV/div -50 OUT_ 500mV/div -60 -70 -80 -90 -100 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 2s/div 2s/div FREQUENCY (kHz) 6 85 105 125 DYNAMIC-RESPONSE FALL TIME DYNAMIC-RESPONSE RISE TIME MAX5152-TOC07 VREF = 3.6Vp-p AT 1.8VDC f = 1kHz CODE = 1FFF (HEX) NOTE: RELATIVE TO FULL SCALE 65 TEMPERATURE (C) MAX5152 TOC08 0 -20 -55 -35 -15 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 FREQUENCY (kHz) LOAD (k) -10 0 -150 -1.0 RELATIVE OUTPUT (dB) MAX5152/MAX5153 Low-Power, Dual, 13-Bit Voltage-Output DACs with Configurable Outputs _______________________________________________________________________________________ Low-Power, Dual, 13-Bit Voltage-Output DACs with Configurable Outputs MAX5153 -8 -10 -12 -14 500 1000 1500 2000 -70 -90 0.40 2500 -60 -20 20 60 100 0 140 100 TEMPERATURE (C) FREQUENCY (kHz) FULL-SCALE ERROR vs. LOAD REFERENCE FEEDTHROUGH AT 1kHz POWER-DOWN CURRENT vs. TEMPERATURE -70 RELATIVE OUTPUT (dB) -0.4 -0.6 -0.8 VREF = 1.6Vp-p AT 0.88VDC CODE = 0000 (HEX) -80 -90 -100 -110 -120 -130 -1.0 3.0 2.5 2.0 1.5 1.0 0.5 -140 VREF = 1.25V 0 -150 -1.2 1 MAX5251 TOC15 -60 POWER-DOWN CURRENT (A) -50 MAX5152 TOC13 -0.2 10 100 1000 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 LOAD (k) FREQUENCY (kHz) OUTPUT FFT PLOT DYNAMIC-RESPONSE RISE TIME 0 VREF = 1.6Vp-p AT 0.88VDC f = 1kHz CODE = 1FFF (HEX) NOTE: RELATIVE TO FULL SCALE -55 -35 -15 5 25 45 65 85 105 125 TEMPERATURE (C) DYNAMIC-RESPONSE FALL TIME MAX5152 TOC18 MAX5152 TOC17 MAX5152-TOC16 0.1 10 FREQUENCY (kHz) 0 FULL-SCALE ERROR (LSB) -60 CODE = 0000 (HEX) MAX5152-TOC14 0 RELATIVE OUTPUT (dB) 0.50 -50 -80 -20 -30 -40 VREF = 0.67Vp-p AT 1.25VDC CODE = 1FFF (HEX) -18 -20 CODE = 1FFF (HEX) 0.45 -16 VREF = 1Vp-p AT 1VDC CODE = 1FFF (HEX) 0.55 THD + NOISE (dB) -6 -30 MAX5152 TOC11 RL = SUPPLY CURRENT (mA) -4 RELATIVE OUTPUT (dB) 0.60 MAX5152 TOC10 0 -2 -10 TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY SUPPLY CURRENT vs. TEMPERATURE MAX5152 TOC12 REFERENCE VOLTAGE INPUT FREQUENCY RESPONSE MAX5152/MAX5153 ____________________________Typical Operating Characteristics (continued) (VDD = +3V, RL = 10k, CL = 100pF, FB_ tied to OUT_, TA = +25C, unless otherwise noted.) CS 2V/div CS 2V/div -40 -50 OUT_ 500mV/div -60 OUT_ 500mV/div -70 -80 -90 -100 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 2s/div 2s/div FREQUENCY (kHz) _______________________________________________________________________________________ 7 ____________________________Typical Operating Characteristics (continued) (VDD = +5V (MAX5152), VDD = +3V (MAX5153), RL = 10k, CL = 100pF, FB_ tied to OUT_, TA = TMIN to TMAX, unless otherwise noted.) MAX5152/MAX5153 MAX5153 SUPPLY CURRENT vs. SUPPLY VOLTAGE MAX5152 SUPPLY CURRENT vs. SUPPLY VOLTAGE 0.50 CODE = 0000 (HEX) 0.45 MAX5152 TOC19a CODE = 1FFF (HEX) 0.50 SUPPLY CURRENT (mA) CODE = 1FFF (HEX) 0.55 0.55 MAX5152 TOC19 0.60 SUPPLY CURRENT (mA) MAX5152/MAX5153 Low-Power, Dual, 13-Bit Voltage-Output DACs with Configurable Outputs 0.40 0.45 CODE = 0000 (HEX) 0.40 0.35 0.35 RL = RL = 0.30 4.50 4.75 5.00 5.25 0.30 2.7 5.50 3.0 3.3 3.6 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) MAX5152 MAJOR-CARRY TRANSITION MAX5152 TOC20 CS 2V/div OUT_ 10mV/div AC COUPLED 2s/div MAX5152 ANALOG CROSSTALK MAX5152 DIGITAL FEEDTHROUGH MAX5152 TOC21 MAX5152 TOC22 SCLK 5V/div OUTA 1V/div OUTA 500V/div AC COUPLED OUTB 200V/div AC COUPLED 200s/div 8 1s/div _______________________________________________________________________________________ Low-Power, Dual, 13-Bit Voltage-Output DACs with Configurable Outputs PIN NAME 1 AGND Analog Ground 2 OUTA DAC A Output Voltage 3 FBA 4 REFA FUNCTION DAC A Output Amplifier Feedback Input. Inverting input of the output amplifier. Reference for DAC A 5 CL Active-Low Clear Input. Resets all registers to zero. DAC outputs go to 0V. 6 CS Chip-Select Input 7 DIN Serial Data Input 8 SCLK Serial Clock Input 9 DGND Digital Ground 10 DOUT Serial Data Output 11 UPO User-Programmable Output 12 PDL Power-Down Lockout. The device cannot be powered down when PDL is low. 13 REFB 14 FBB 15 OUTB DAC B Output Voltage 16 VDD Positive Power Supply Reference Input for DAC B DAC B Output Amplifier Feedback Input. Inverting input of the output amplifier. _______________Detailed Description FB_ The MAX5152/MAX5153 dual, 13-bit, voltage-output DACs are easily configured with a 3-wire serial interface. These devices include a 16-bit data-in/data-out shift register, and each DAC has a double-buffered input comprised of an input register and a DAC register (see Functional Diagram). Both DACs use an inverted R-2R ladder network that produces a weighted voltage proportional to the input voltage value. Each DAC has its own reference input to facilitate independent fullscale values. Figure 1 depicts a simplified circuit diagram of one of the two DACs. REF_ Reference Inputs AGND The reference inputs accept both AC and DC values with a voltage range extending from 0V to (VDD - 1.4V). Determine the output voltage using the following equation: VOUT = VREF x NB / 8192 where NB is the numeric value of the DAC's binary input code (0 to 8191) and VREF is the reference voltage. The reference input impedance ranges from 14k (1555 hex) to several giga ohms (with an input code of 0000 hex). This reference input capacitance is code dependent and typically ranges from 15pF with an input code of all zeros to 50pF with an input code of all ones. R 2R 2R D0 R 2R D10 OUT_ R 2R 2R D11 D12 SHOWN FOR ALL 1s ON DAC Figure 1. Simplified DAC Circuit Diagram Output Amplifier The output amplifier's inverting input is available to the user, allowing force and sense capability for remote sensing and specific gain configurations. The inverting input can be connected to the output to provide a unitygain buffered output. The output amplifiers have a typical slew rate of 0.75V/s and settle to 1/2LSB within 25s, with a load of 10k in parallel to 100pF. Loads less than 2k degrade performance. _______________________________________________________________________________________ 9 MAX5152/MAX5153 ______________________________________________________________Pin Description MAX5152/MAX5153 Low-Power, Dual, 13-Bit Voltage-Output DACs with Configurable Outputs Table 1. Serial-Interface Programming Commands 16-BIT SERIAL WORD FUNCTION A0 C1 C0 D12................D0 MSB LSB 0 0 1 13 bits of DAC data Load input register A; DAC register is unchanged. 1 0 1 13 bits of DAC data Load input register B; DAC register is unchanged. 0 1 0 13 bits of DAC data Load input register A; all DAC registers are updated. 1 1 0 13 bits of DAC data Load input register B; all DAC registers are updated. 0 1 1 13 bits of DAC data Load all DAC registers from the shift register (start up both DACs with new data). 1 0 0 xxxxxxxxxxxxx Update both DAC registers from their respective input registers (start up both DACs with data previously stored in the input registers). 1 1 1 xxxxxxxxxxxxx Shut down both DACs if PDL = 1. 0 0 0 0 0 1 x xxxxxxxxx Update DAC register A from input register A (start up DAC A with data previously stored in input register A). 0 0 0 1 0 1 x xxxxxxxxx Update DAC register B from input register B (start up DAC B with data previously stored in input register B). 0 0 0 1 1 0 x xxxxxxxxx Shut down DAC A when PDL = 1. 0 0 0 1 1 1 x xxxxxxxxx Shut down DAC B when PDL = 1. 0 0 0 0 1 0 x xxxxxxxxx UPO goes low (default). 0 0 0 0 1 1 x xxxxxxxxx UPO goes high. 0 0 0 1 0 0 1 xxxxxxxxx Mode 1, DOUT clocked out on SCLK's rising edge. 0 0 0 1 0 0 0 xxxxxxxxx Mode 0, DOUT clocked out on SCLK's falling edge (default). 0 0 0 0 0 0 x xxxxxxxxx No operation (NOP). "x" = don't care Note: When A0, C1, and C0 = "0", D12, D11, D10, and D9 become control bits. Power-Down Mode Serial Interface The MAX5152/MAX5153 feature a software-programmable shutdown mode that reduces the typical supply current to 2A. The two DACs can be shut down independently or simultaneously by using the appropriate programming word. For instance, enter shutdown mode (for both DACs) by writing an input control word of 111XXXXXXXXXXXXX (Table 1). In shutdown mode, the reference inputs and amplifier outputs become high impedance, and the serial interface remains active. Data in the input registers is saved, allowing the MAX5152/MAX5153 to recall the output state prior to entering shutdown when returning to normal mode. Exit shutdown by recalling the previous condition or by updating the DAC with new information. When returning to normal operation (exiting shutdown), wait 20s for output stabilization. The MAX5152/MAX5153 3-wire serial interface is compatible with both Microwire (Figure 2) and SPI/QSPI (Figure 3) serial-interface standards. The 16-bit serial input word consists of an address bit, two control bits, and 13 bits of data (MSB to LSB) as shown in Figure 4. The address and control bits determines the response of the MAX5152/MAX5153, as outlined in Table 1. 10 The MAX5152/MAX5153's digital inputs are double buffered, which allows any of the following: loading the input register(s) without updating the DAC register(s), updating the DAC register(s) from the input register(s), or updating the input and DAC registers concurrently. The address and control bits allow for the DACs to act independently. ______________________________________________________________________________________ Low-Power, Dual, 13-Bit Voltage-Output DACs with Configurable Outputs MAX5152 MAX5153 SK DIN SO CS I/O MICROWIRE PORT Figure 2. Connections for Microwire VCC SS DIN MAX5152 MAX5153 MOSI SCLK SPI/QSPI PORT SCK CS I/O CPOL = 0, CPHA = 0 * registers to be updated * clock edge on which data is clocked out via the serial data output (DOUT) * state of the user-programmable logic output * configuration of the device after shutdown The general timing diagram in Figure 5 illustrates how data is acquired. Driving CS low enables the device to receive data. Otherwise, the interface control circuitry is disabled. With CS low, data at DIN is clocked into the register on the rising edge of SCLK. As CS goes high, data is latched into the input and/or DAC registers depending on the address and control bits. The maximum clock frequency guaranteed for proper operation is 10MHz. Figure 6 depicts a more detailed timing diagram of the serial interface. Serial Data Output (DOUT) DOUT is the internal shift register's output. It allows for daisy-chaining and data readback. The MAX5152/ MAX5153 can be programmed to shift data out of DOUT on SCLK's falling edge (Mode 0) or rising edge (Mode 1). Mode 0 provides a lag of 16 clock cycles, which maintains compatibility with SPI/QSPI and Microwire interfaces. In Mode 1, the output data lags 15.5 clock cycles. On power-up, the device defaults to Mode 0. User-Programmable Logic Output (UPO) UPO allows an external device to be controlled through the MAX5152/MAX5153 serial interface (Table 1), thereby reducing the number of microcontroller I/O pins required. On power-up, UPO is low. Figure 3. Connections for SPI/QSPI MSB ..................................................................................LSB 16 Bits of Serial Data Address Bits Control Bits MSB.......Data Bits.........LSB A0 C1, C0 D12.................................D0 1 Address/2 Control Bits Figure 4. Serial-Data Format 13 Data Bits Power-Down Lockout Input (PDL) PDL disables software shutdown when low. When in shutdown, transitioning PDL from high to low wakes up the part with the output set to the state prior to shutdown. PDL can also be used to asynchronously wake up the device. Daisy Chaining Devices Any number of MAX5152/MAX5153s can be daisy chained by connecting the DOUT pin of one device to the DIN pin of the following device in the chain (Figure 7). ______________________________________________________________________________________ 11 MAX5152/MAX5153 SCLK Send the 16-bit data as two 8-bit packets (SPI, Microwire) or one 16-bit word (QSPI), with CS low during this period. The address and control bits determine which register will be updated, as well as the state of the registers when exiting shutdown. The 3-bit address/control determines: MAX5152/MAX5153 Low-Power, Dual, 13-Bit Voltage-Output DACs with Configurable Outputs CS COMMAND EXECUTED SCLK 1 DIN 8 C1 A0 C0 D12 D11 D10 D9 9 D8 D7 16 D6 D5 D4 D3 D2 D1 D0 Figure 5. Serial-Interface Timing Diagram tCSW CS tCSS tCSO tCP tCH tCL tCSH tCS1 SCLK tDS tDH DIN Figure 6. Detailed Serial-Interface Timing Diagram SCLK SCLK MAX5152 MAX5153 DIN DOUT CS SCLK MAX5152 MAX5153 DIN DOUT CS MAX5152 MAX5153 DIN CS DOUT TO OTHER SERIAL DEVICES Figure 7. Daisy Chaining MAX5152/MAX5153s Since the MAX5152/MAX5153's DOUT has an internal active pull-up, the DOUT sink/source capability determines the time required to discharge/charge a capacitive load. Refer to the digital output V OH and V OL specifications in the Electrical Characteristics. 12 Figure 8 shows an alternative method of connecting several MAX5152/MAX5153s. In this configuration, the data bus is common to all devices; data is not shifted through a daisy-chain. More I/O lines are required in this configuration because a dedicated chip-select input (CS) is required for each IC. ______________________________________________________________________________________ Low-Power, Dual, 13-Bit Voltage-Output DACs with Configurable Outputs MAX5152/MAX5153 DIN SCLK CS1 CS2 TO OTHER SERIAL DEVICES CS3 CS CS MAX5152 MAX5153 CS MAX5152 MAX5153 MAX5152 MAX5153 SCLK SCLK SCLK DIN DIN DIN Figure 8. Multiple MAX5152/MAX5153s Sharing a Common DIN Line Table 2. Unipolar Code Table (Gain = +1) +5V/+3V DAC CONTENTS MSB LSB REF_ VDD MAX5152 MAX5153 FB_ DAC 11111 1111 1111 8191 +VREF 8192 10000 0000 0001 4097 +VREF 8192 10000 0000 0000 01111 1111 1111 4095 +VREF 8192 00000 0000 0001 1 +VREF 8192 00000 0000 0000 OUT_ AGND DGND Figure 9. Unipolar Output Circuit __________Applications Information Unipolar Output Figure 9 depicts the MAX5152/MAX5153 configured for unity-gain, unipolar operation. Table 2 lists the unipolar output codes. To increase dynamic range, specific gain configurations can be used as shown in Figure 10. ANALOG OUTPUT 4096 VREF +VREF = 2 8192 0V Bipolar Output The MAX5152/MAX5153 can be configured for a bipolar output, as shown in Figure 11. The output voltage is given by the equation: VOUT = VREF [((2 x NB) / 8192) - 1] where NB represents the numeric value of the DAC's binary input code. Table 3 shows digital codes and the corresponding output voltage for Figure 11's circuit. ______________________________________________________________________________________ 13 MAX5152/MAX5153 Low-Power, Dual, 13-Bit Voltage-Output DACs with Configurable Outputs +5V/+3V REF_ +5V/+3V REF_ VDD R2 MAX5152 MAX5153 10k VDD FB_ VOUT V+ FB_ MAX5152 MAX5153 R1 DAC 10k VOUT OUT_ DAC _ DGND OUT_ AGND VDGND AGND ( ) ( )( ) VOUT = 1 + R1 R2 N VREF_ 8192 Figure 10. Configurable Output Gain Figure 11. Bipolar Output Circuit Table 3. Bipolar Code Table +5V/ +3V DAC CONTENTS MSB LSB ANALOG OUTPUT 11111 1111 1111 4095 +VREF 4096 10000 0000 0001 1 +VREF 4096 10000 0000 0000 01111 1111 1111 00000 00000 0000 0000 0001 0000 +5V/+3V 26k AC REFERENCE INPUT 500mVp-p MAX495 10k VDD REF_ FB_ 0V 1 -VREF 4096 DAC_ 4095 -VREF 4096 4096 -VREF = - VREF 4096 DGND OUT_ MAX5152 MAX5153 AGND Figure 12. AC Reference Input Circuit Using an AC Reference In applications where the reference has an AC signal component, the MAX5152/MAX5153 have multiplying capabilities within the reference input voltage range specifications. Figure 12 shows a technique for applying a sinusoidal input to the reference input to REF_, where the AC signal is offset before being applied to the reference input. 14 Harmonic Distortion and Noise The total harmonic distortion plus noise (THD+N) is typically less than -80dB at full scale with a 1Vp-p input swing at 5kHz. The typical -3dB frequency is 600kHz for both devices, as shown in the Typical Operating Characteristics. ______________________________________________________________________________________ Low-Power, Dual, 13-Bit Voltage-Output DACs with Configurable Outputs Figure 13 shows the MAX5152/MAX5153 in a digital calibration application. With a bright value applied to the photodiode (on), the DAC is digitally ramped up until it trips the comparator. The microprocessor stores this high calibration value. Repeat the process with a dim light (off) to obtain the dark current calibration. The microprocessor then programs the DAC to set an output voltage that is the midpoint of the two calibration values. Applications include tachometers, motion sensing, automatic readers, and liquid clarity analysis. V+ REF_ +5V/+3V PHOTODIODE VDD MAX5152 MAX5153 V+ FB_ VOUT OUT_ Digital Control of Gain and Offset P The two DACs can be used to control the offset and gain for curve-fitting nonlinear functions, such as transducer linearization or analog compression/expansion applications. The input signal is used as the reference for the gain-adjust DAC, whose output is summed with the output from the offset-adjust DAC. The relative weight of each DAC output is adjusted by R1, R2, R3, and R4 (Figure 14). DAC _ DIN R DGND V- AGND Figure 13. Digital Calibration +5V/+3V VDD MAX5152 MAX5153 VIN DIN SCLK CL R1 REFA CONTROL/ SHIFT REGISTER CS FBA DACA OUT_A DACB OUT_B R2 VOUT R3 R4 REFB VREF FBB [ ] [ ] = (V NA )( R2 )(1+ R4 ) (V [ 8192 R1+R2 R3 ] [ VOUT = GAIN - OFFSET DGND AGND IN REF NB 8192 )( R4R3 )] NA IS THE NUMERIC VALUE OF THE INPUT CODE FOR DACA. NB IS THE NUMERIC VALUE OF THE INPUT CODE FOR DACB. Figure 14. Digital Control of Gain and Offset ______________________________________________________________________________________ 15 MAX5152/MAX5153 Digital Calibration and Threshold Selection MAX5152/MAX5153 Low-Power, Dual, 13-Bit Voltage-Output DACs with Configurable Outputs Digital Programmable Current Source Figure 15 depicts a digitally programmable, unidirectional current source that can be used in industrial control applications. The output current is: REF_ IOUT = (VREF / R) (NB / 8192) where NB is the DAC code and R is the sense resistor. VL VDD Power-Supply Considerations DAC_ On power-up, the input and DAC registers clear (reset to zero code). For rated performance, VREF_ should be at least 1.4V below VDD. Bypass the power supply with a 4.7F capacitor in parallel with a 0.1F capacitor to GND. Minimize lead lengths to reduce lead inductance. Grounding and Layout Considerations Digital and AC transient signals on AGND can create noise at the output. Connect AGND to the highest quality ground available. Use proper grounding techniques, such as a multilayer board with an unbroken, lowinductance ground plane. Carefully lay out the traces between channels to reduce AC cross-coupling and crosstalk. Wire-wrapped boards and sockets are not recommended. If noise becomes an issue, shielding may be required. 16 +5V/+3V IOUT OUT_ MAX5152 MAX5153 2N3904 FB_ R DGND AGND Figure 15. Digitally Programmable Current Source ______________________________________________________________________________________ Low-Power, Dual, 13-Bit Voltage-Output DACs with Configurable Outputs PART TEMP. RANGE PIN-PACKAGE INL (LSB) MAX5152AEPE -40C to +85C 16 Plastic DIP 1/2 MAX5152BEPE -40C to +85C 16 Plastic DIP 1 MAX5152AEEE -40C to +85C 16 QSOP 1/2 __________________Pin Configuration TOP VIEW AGND 1 16 VDD OUTA 2 15 OUTB 14 FBB FBA 3 REFA 4 MAX5152 MAX5153 13 REFB MAX5152BEEE -40C to +85C 16 QSOP 1 MAX5152BMJE -55C to +125C 16 CERDIP** 1 CL 5 MAX5153ACPE 0C to +70C 16 Plastic DIP 1 CS 6 11 UPO MAX5153BCPE 0C to +70C 16 Plastic DIP 2 DIN 7 10 DOUT MAX5153ACEE 0C to +70C 16 QSOP 1 MAX5153BCEE 0C to +70C 16 QSOP 2 MAX5153BC/D 0C to +70C Dice* 2 MAX5153AEPE -40C to +85C 16 Plastic DIP 1 MAX5153BEPE -40C to +85C 16 Plastic DIP 2 MAX5153AEEE -40C to +85C 16 QSOP 1 MAX5153BEEE -40C to +85C 16 QSOP 2 MAX5153BMJE -55C to +125C 16 CERDIP** 2 12 PDL 9 SCLK 8 DGND DIP/QSOP *Dice are tested at TA = +25C, DC parameters only. **Contact factory for availability. ___________________Chip Information TRANSISTOR COUNT: 3053 SUBSTRATE CONNECTED TO AGND ______________________________________________________________________________________ 17 MAX5152/MAX5153 _Ordering Information (continued) ________________________________________________________Package Information PDIPN.EPS MAX5152/MAX5153 Low-Power, Dual, 13-Bit Voltage-Output DACs with Configurable Outputs 18 ______________________________________________________________________________________ Low-Power, Dual, 13-Bit Voltage-Output DACs with Configurable Outputs QSOP.EPS ______________________________________________________________________________________ 19 MAX5152/MAX5153 ___________________________________________Package Information (continued) ___________________________________________Package Information (continued) CDIPS.EPS MAX5152/MAX5153 Low-Power, Dual, 13-Bit Voltage-Output DACs with Configurable Outputs Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 20 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 1997 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.