1. General description
The 74LV574 is an octal D-type flip–flop featuring separate D-type inputs for each flip-flop
and non-inverting 3-state outputs for bus oriented applications. A clock (CP) and an output
enable (OE) input are common to all flip-flops. It is a low-voltage Si-gate CMOS device
and is pin and functionally compatible with the 74HC574 and 74HCT574.
The eight flip-flops will store the state of their individual D-inputs that meet the set-up and
hold times requirements on the LOW to HIGH CP transition.
When OE is LOW, the contents of the eight flip-flops is available at the outputs. When OE
is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does
not affect the state of the flip-flops.
2. Features
nWide operating voltage: 1.0 V to 5.5 V
nOptimized for low voltage applications: 1.0 V to 3.6 V
nAccepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V
nTypical output ground bounce < 0.8 V at VCC = 3.3 V and Tamb = 25 °C
nTypical HIGH-level output voltage (VOH) undershoot: > 2 V at VCC = 3.3 V and
Tamb =25°C
nESD protection:
uHBM JESD22-A114E exceeds 2000 V
uMM JESD22-A115-A exceeds 200 V
nCommon 3-state output enable input
nMultiple package options
nSpecified from −40 °Cto+85°C and from −40 °C to +125 °C
3. Ordering information
74LV574
Octal D-type flip-flop; positive edge-trigger; 3-state
Rev. 04 — 14 May 2009 Product data sheet
Table 1. Ordering information
Type
number Package
Temperature range Name Description Version
74LV574N −40 °C to +125 °C DIP20 plastic dual in-line package; 20 leads (300 mil) SOT146-1
74LV574D −40 °C to +125 °C SO20 plastic small outline package; 20 leads; body width 7.5 mm SOT163-1
74LV574DB −40 °C to +125 °C SSOP20 plastic shrink small outline package; 20 leads;
body width 5.3 mm SOT339-1
74LV574PW −40 °C to +125 °C TSSOP20 plastic thin shrink small outline package; 20 leads;
body width 4.4 mm SOT360-1
74LV574_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 14 May 2009 2 of 17
NXP Semiconductors 74LV574
Octal D-type flip-flop; positive edge-trigger; 3-state
4. Functional diagram
Fig 1. Logic symbol Fig 2. IEC logic symbol
mna798
D0
D1
D2
D3
D4
D5
D6
D7 OE
CP Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
11
1
12
13
14
15
16
17
18
19
9
8
7
6
5
4
3
2
mna446
12
13
14
15
16
17
18
11 C1
1EN
1D 19
9
8
7
6
5
4
3
2
Fig 3. Functional diagram
mna800
3-STATE
OUTPUTS
FF1
to
FF8
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7 12
13
14
15
16
17
18
19
D0
D1
D2
D3
D4
D5
D6
D7
CP
OE
9
11
1
8
7
6
5
4
3
2
74LV574_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 14 May 2009 3 of 17
NXP Semiconductors 74LV574
Octal D-type flip-flop; positive edge-trigger; 3-state
5. Pinning information
5.1 Pinning
5.2 Pin description
Fig 4. Logic diagram
mna801
Q4
D4
Q3
D3
Q2
D2
Q1
D1
Q0
D0
D
FF1
Q
CP
CP
D
FF2
Q
CP
D
FF3
Q
CP
D
FF4
Q
CP
D
FF5
Q
CP
D
FF6
Q
CP
D
FF7
Q
CP
D
FF8
Q
CP
OE
Q5
D5
Q6
D6
Q7
D7
Fig 5. Pin configuration DIP20, SO20 Fig 6. Pin configuration SSOP20, TSSOP20
74LV574
OE VCC
D0 Q0
D1 Q1
D2 Q2
D3 Q3
D4 Q4
D5 Q5
D6 Q6
D7 Q7
GND CP
001aaj968
1
2
3
4
5
6
7
8
9
10
12
11
14
13
16
15
18
17
20
19
74LV574
OE VCC
D0 Q0
D1 Q1
D2 Q2
D3 Q3
D4 Q4
D5 Q5
D6 Q6
D7 Q7
GND CP
001aaj969
1
2
3
4
5
6
7
8
9
10
12
11
14
13
16
15
18
17
20
19
Table 2. Pin description
Symbol Pin Description
OE 1 output enable input (active LOW)
D0 to D7 2, 3, 4, 5, 6, 7, 8, 9 data input
GND 10 ground (0 V)
CP 11 clock input (LOW to HIGH; edge triggered)
Q0 to Q7 19, 18, 17, 16, 15, 14, 13, 12 data output
VCC 20 supply voltage
74LV574_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 14 May 2009 4 of 17
NXP Semiconductors 74LV574
Octal D-type flip-flop; positive edge-trigger; 3-state
6. Functional description
[1] H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the LOW to HIGH CP transition
L = LOW voltage level
l = LOW voltage level one set-up time prior to the LOW to HIGH CP transition
Z = high-impedance OFF-state
↑= LOW to HIGH clock transition
7. Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For DIP20 packages: above 70 °C the value of Ptot derates linearly with 12 mW/K.
For SO20 packages: above 70 °C the value of Ptot derates linearly with 8 mW/K.
For (T)SSOP20 packages: above 60 °C the value of Ptot derates linearly with 5.5 mW/K.
Table 3. Function table[1]
Operating mode Input Internal flip-flop Output
OE CP Dn Qn
Load and read register L ↑lLL
L↑hHH
Load register and disable
outputs H↑lLZ
H↑hHZ
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage −0.5 +7.0 V
IIK input clamping current VI < −0.5 V or VI>V
CC + 0.5 V [1] -±20 mA
IOK output clamping current VO<−0.5 V or VO>V
CC + 0.5 V [1] -±50 mA
IOoutput current VO = −0.5 V to (VCC + 0.5 V) - ±35 mA
ICC supply current - 70 mA
IGND ground current −70 - mA
Tstg storage temperature −65 +150 °C
Ptot total power dissipation Tamb =−40 °C to +125 °C[2]
DIP20 - 750 mW
SO20, SSOP20 and TSSOP20 - 500 mW
74LV574_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 14 May 2009 5 of 17
NXP Semiconductors 74LV574
Octal D-type flip-flop; positive edge-trigger; 3-state
8. Recommended operating conditions
[1] The static characteristics are guaranteed from VCC = 1.2 V to VCC = 5.5 V, but LV devices are guaranteed to function down to
VCC = 1.0 V (with input levels GND or VCC).
9. Static characteristics
Table 5. Recommended operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ Max Unit
VCC supply voltage[1] 1.0 3.3 5.5 V
VIinput voltage 0 - VCC V
VOoutput voltage 0 - VCC V
Tamb ambient temperature −40 +25 +125 °C
∆t/∆V input transition rise and fall rate VCC = 1.0 V to 2.0 V - - 500 ns/V
VCC = 2.0 V to 2.7 V - - 200 ns/V
VCC = 2.7 V to 3.6 V - - 100 ns/V
VCC = 3.6 V to 5.5 V - - 50 ns/V
Table 6. Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions −40 °C to +85 °C−40 °C to +125 °C Unit
Min Typ[1] Max Min Max
VIH HIGH-level input voltage VCC = 1.2 V 0.9 - - 0.9 - V
VCC = 2.0 V 1.4 - - 1.4 - V
VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - V
VCC = 4.5 V to 5.5 V 0.7VCC - - 0.7VCC -V
VIL LOW-level input voltage VCC = 1.2 V - - 0.3 - 0.3 V
VCC = 2.0 V - - 0.6 - 0.6 V
VCC = 2.7 V to 3.6 V - - 0.8 - 0.8 V
VCC = 4.5 V to 5.5 V - - 0.3VCC - 0.3VCC V
VOH HIGH-level output voltage VI = VIH or VIL
IO = −100 µA; VCC = 1.2 V - 1.2 - - - V
IO = −100 µA; VCC = 2.0 V 1.8 2.0 - 1.8 - V
IO = −100 µA; VCC = 2.7 V 2.5 2.7 - 2.5 - V
IO = −100 µA; VCC = 3.0 V 2.8 3.0 - 2.8 - V
IO = −100 µA; VCC = 4.5 V 4.3 4.5 - 4.3 - V
IO = −8 mA; VCC = 3.0 V 2.4 2.82 - 2.2 - V
IO = −16 mA; VCC = 4.5 V 3.6 4.2 - 3.5 - V
74LV574_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 14 May 2009 6 of 17
NXP Semiconductors 74LV574
Octal D-type flip-flop; positive edge-trigger; 3-state
[1] Typical values are measured at Tamb = 25 °C.
10. Dynamic characteristics
VOL LOW-level output voltage VI = VIH or VIL
IO = 100 µA; VCC = 1.2 V - 0 - - - V
IO = 100 µA; VCC = 2.0 V - 0 0.2 - 0.2 V
IO = 100 µA; VCC = 2.7 V - 0 0.2 - 0.2 V
IO = 100 µA; VCC = 3.0 V - 0 0.2 - 0.2 V
IO = 100 µA; VCC = 4.5 V - 0 0.2 - 0.2 V
IO = 8 mA; VCC = 3.0 V - 0.25 0.40 - 0.50 V
IO = 16 mA; VCC = 4.5 V - 0.35 0.55 - 0.65 V
IIinput leakage current VI=V
CC or GND;
VCC = 5.5 V - - 1.0 - 1.0 µA
IOZ OFF-state output current VI =V
IH or VIL;
VO=V
CC or GND;
VCC = 5.5 V
--5 - 10µA
ICC supply current VI = VCC or GND; IO = 0 A;
VCC = 5.5 V - - 20 - 160 µA
∆ICC additional supply current per input; VI = VCC − 0.6 V;
VCC = 2.7 V to 3.6 V - - 500 - 850 µA
CIinput capacitance - 3.5 - - - pF
Table 6. Static characteristics
…continued
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions −40 °C to +85 °C−40 °C to +125 °C Unit
Min Typ[1] Max Min Max
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 10.
Symbol Parameter Conditions −40 °C to +85 °C−40 °C to +125 °C Unit
Min Typ[1] Max Min Max
tpd propagation delay CP to Qn; see Figure 7 [2]
VCC = 1.2 V - 80 - - - ns
VCC = 2.0 V - 27 34 - 43 ns
VCC = 2.7 V - 20 25 - 31 ns
VCC = 3.0 V to 3.6 V; CL=15pF [3] -13- - -ns
VCC = 3.0 V to 3.6 V [3] - 15 20 - 25 ns
VCC = 4.5 V to 5.5 V - - 17 - 21 ns
ten enable time OE to Qn; see Figure 8 [4]
VCC = 1.2 V - 70 - - - ns
VCC = 2.0 V - 24 34 - 43 ns
VCC = 2.7 V - 18 25 - 31 ns
VCC = 3.0 V to 3.6 V [3] - 13 20 - 25 ns
VCC = 4.5 V to 5.5 V - - 17 - 21 ns
74LV574_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 14 May 2009 7 of 17
NXP Semiconductors 74LV574
Octal D-type flip-flop; positive edge-trigger; 3-state
[1] Typical values are measured at Tamb =25°C.
[2] tpd is the same as tPLH and tPHL.
[3] Typical value measured at VCC = 3.3 V.
[4] ten is the same as tPZH and tPZL.
[5] tdis is the same as tPHZ and tPLZ.
[6] CPD is used to determine the dynamic power dissipation (PDin µW).
PD=C
PD ×VCC2×fi×N+∑(CL×VCC2×fo) where:
fi= input frequency in MHz;
fo= output frequency in MHz;
CL= output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
∑(CL×VCC2×fo) = sum of outputs.
tdis disable time OE to Qn; Figure 8 [5]
VCC = 1.2 V - 75 - - - ns
VCC = 2.0 V - 27 27 - 34 ns
VCC = 2.7 V - 21 21 - 26 ns
VCC = 3.0 V to 3.6 V [3] - 16 17 - 21 ns
VCC = 4.5 V to 5.5 V [3] - - 15 - 18 ns
tWpulse width CP, HIGH or LOW; see Figure 7
VCC = 2.0 V 34 9 - 41 - ns
VCC = 2.7 V 25 6 - 30 - ns
VCC = 3.0 V to 3.6 V [3] 20 5 - 24 - ns
tsu set-up time Dn to CP; see Figure 9
VCC = 1.2 V - 10 - - - ns
VCC = 2.0 V 22 4 - 26 - ns
VCC = 2.7 V 16 3 - 19 - ns
VCC = 3.0 V to 3.6 V [3] 13 2 - 15 - ns
thhold time Dn to CP; see Figure 9
VCC = 1.2 V - −10 - - - ns
VCC = 2.0 V 5 −4- 5 -ns
VCC = 2.7 V 5 −3- 5 -ns
VCC = 3.0 V to 3.6 V [3] 5−2- 5 -ns
fmax maximum
frequency see Figure 7
VCC = 2.0 V 15 40 - 12 - MHz
VCC = 2.7 V 19 58 - 16 - MHz
VCC = 3.0 V to 3.6 V [3] 24 70 - 20 - MHz
CPD power dissipation
capacitance CL= 50 pF; fi = 1 MHz;
VI= GND to VCC
[6] 25 pF
Table 7. Dynamic characteristics
…continued
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 10.
Symbol Parameter Conditions −40 °C to +85 °C−40 °C to +125 °C Unit
Min Typ[1] Max Min Max
74LV574_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 14 May 2009 8 of 17
NXP Semiconductors 74LV574
Octal D-type flip-flop; positive edge-trigger; 3-state
11. Waveforms
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 7. The clock (CP) to output (Qn) propagation delays, the clock pulse (CP) and the maximum
clock pulse frequency
mna894
CP input
Qn output
tPHL tPLH
tW
1/fmax
VM
VOH
VI
GND
VOL
VM
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 8. Enable and disable times
mna644
tPLZ
tPHZ
outputs
disabled outputs
enabled
VY
VX
outputs
enabled
output
LOW-to-OFF
OFF-to-LOW
output
HIGH-to-OFF
OFF-to-HIGH
OE input
VI
VOL
VOH
VCC
VM
GND
GND
tPZL
tPZH
VM
VM
74LV574_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 14 May 2009 9 of 17
NXP Semiconductors 74LV574
Octal D-type flip-flop; positive edge-trigger; 3-state
Measurement points are given in Table 8.
The shaded areas indicate when the input is permitted to change for predictable output performance.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 9. The data set-up and hold times for the Dn input to the CP input)
mna202
GND
GND
thth
tsu
tsu
VM
VM
VM
VI
VOH
VOL
VI
Qn output
CP input
Dn input
Table 8. Measurement points
Supply voltage Input Output
VCC VMVMVxVy
< 2.7 V 0.5VCC 0.5VCC VOL + 0.3 V VOH − 0.3 V
2.7 V to 3.6 V 1.5 V 1.5 V VOL + 0.3 V VOH − 0.3 V
≥ 4.5 V 0.5VCC 0.5VCC VOL + 0.3 V VOH − 0.3 V
74LV574_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 14 May 2009 10 of 17
NXP Semiconductors 74LV574
Octal D-type flip-flop; positive edge-trigger; 3-state
Test data is given in Table 9.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 10. Test circuit for measuring switching times
VMVM
tW
tW
10 %
90 %
0 V
VI
VI
negative
pulse
positive
pulse
0 V
VMVM
90 %
10 %
tf
tr
tr
tf
001aae331
VEXT
VCC
VIVO
DUT
CL
RT
RL
RL
G
Table 9. Test data
Supply voltage Input Load VEXT
VCC VItr, tfCLRLtPHL, tPLH tPZH, tPHZ tPZL, tPLZ
< 2.7 V VCC ≤ 2.5 ns 50 pF 1 kΩopen GND 2VCC
2.7 V to 3.6 V 2.7 V ≤ 2.5 ns 15 pF, 50 pF 1 kΩopen GND 2VCC
≥ 4.5 V VCC ≤ 2.5 ns 50 pF 1 kΩopen GND 2VCC
74LV574_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 14 May 2009 11 of 17
NXP Semiconductors 74LV574
Octal D-type flip-flop; positive edge-trigger; 3-state
12. Package outline
Fig 11. Package outline SOT146-1 (DIP20)
UNIT A
max. 1 2 b1cD E e M
H
L
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm
inches
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
SOT146-1 99-12-27
03-02-13
A
min. A
max. bZ
max.
w
ME
e1
1.73
1.30 0.53
0.38 0.36
0.23 26.92
26.54 6.40
6.22 3.60
3.05 0.2542.54 7.62 8.25
7.80 10.0
8.3 24.2 0.51 3.2
0.068
0.051 0.021
0.015 0.014
0.009 1.060
1.045 0.25
0.24 0.14
0.12 0.010.1 0.3 0.32
0.31 0.39
0.33 0.0780.17 0.02 0.13
SC-603MS-001
MH
c
(e )
1
ME
A
L
seating plane
A1
wM
b1
e
D
A2
Z
20
1
11
10
b
E
pin 1 index
0 5 10 mm
scale
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
(1)
(1) (1)
DIP20: plastic dual in-line package; 20 leads (300 mil) SOT146-1
74LV574_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 14 May 2009 12 of 17
NXP Semiconductors 74LV574
Octal D-type flip-flop; positive edge-trigger; 3-state
Fig 12. Package outline SOT163-1 (SO20)
UNIT A
max. A1A2A3bpcD
(1) E(1) (1)
eH
ELL
pQZ
ywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm
inches
2.65 0.3
0.1 2.45
2.25 0.49
0.36 0.32
0.23 13.0
12.6 7.6
7.4 1.27 10.65
10.00 1.1
1.0 0.9
0.4 8
0
o
o
0.25 0.1
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
1.1
0.4
SOT163-1
10
20
wM
bp
detail X
Z
e
11
1
D
y
0.25
075E04 MS-013
pin 1 index
0.1 0.012
0.004 0.096
0.089 0.019
0.014 0.013
0.009 0.51
0.49 0.30
0.29 0.05
1.4
0.055
0.419
0.394 0.043
0.039 0.035
0.016
0.01
0.25
0.01 0.004
0.043
0.016
0.01
0 5 10 mm
scale
X
θ
A
A1
A2
HE
Lp
Q
E
c
L
vMA
(A )
3
A
SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1
99-12-27
03-02-19
74LV574_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 14 May 2009 13 of 17
NXP Semiconductors 74LV574
Octal D-type flip-flop; positive edge-trigger; 3-state
Fig 13. Package outline SOT339-1 (SSOP20)
UNIT A1A2A3bpcD
(1) E(1) eH
ELL
pQ(1)
Zywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.21
0.05 1.80
1.65 0.38
0.25 0.20
0.09 7.4
7.0 5.4
5.2 0.65 7.9
7.6 0.9
0.7 0.9
0.5 8
0
o
o
0.131.25 0.2 0.1
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.
1.03
0.63
SOT339-1 MO-150 99-12-27
03-02-19
X
wM
θ
A
A1
A2
bp
D
HE
Lp
Q
detail X
E
Z
e
c
L
vMA
(A )
3
A
110
20 11
y
0.25
pin 1 index
0 2.5 5 mm
scale
SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm SOT339-1
A
max.
2
74LV574_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 14 May 2009 14 of 17
NXP Semiconductors 74LV574
Octal D-type flip-flop; positive edge-trigger; 3-state
Fig 14. Package outline SOT360-1 (TSSOP20)
UNIT A1A2A3bpcD
(1) E(2) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
0.05 0.95
0.80 0.30
0.19 0.2
0.1 6.6
6.4 4.5
4.3 0.65 6.6
6.2 0.4
0.3 0.5
0.2 8
0
o
o
0.13 0.10.21
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
0.75
0.50
SOT360-1 MO-153 99-12-27
03-02-19
wM
bp
D
Z
e
0.25
110
20 11
pin 1 index
θ
A
A1
A2
Lp
Q
detail X
L
(A )
3
HE
E
c
vMA
X
A
y
0 2.5 5 mm
scale
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1
A
max.
1.1
74LV574_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 14 May 2009 15 of 17
NXP Semiconductors 74LV574
Octal D-type flip-flop; positive edge-trigger; 3-state
13. Abbreviations
14. Revision history
Table 10. Abbreviations
Acronym Description
CMOS Complementary Metal Oxide Semiconductor
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model
MM Machine Model
TTL Transistor-Transistor Logic
Table 11. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74LV574_4 20090514 Product data sheet - 74LV574_3
Modifications: •Typo removed from Figure 8 and Table 8 adapted accordingly
74LV574_3 20090416 Product data sheet - 74LV574_2
74LV574_2 19970203 Product specification - 74LV574_1
74LV574_1 19980610 Product specification - -
74LV574_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 14 May 2009 16 of 17
NXP Semiconductors 74LV574
Octal D-type flip-flop; positive edge-trigger; 3-state
15. Legal information
15.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
15.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.
NXP Semiconductors 74LV574
Octal D-type flip-flop; positive edge-trigger; 3-state
© NXP B.V. 2009. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 14 May 2009
Document identifier: 74LV574_4
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
17. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 1
4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
6 Functional description . . . . . . . . . . . . . . . . . . . 4
7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
8 Recommended operating conditions. . . . . . . . 5
9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6
11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11
13 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 15
14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 15
15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 16
15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16
15.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
15.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 16
15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 16
16 Contact information. . . . . . . . . . . . . . . . . . . . . 16
17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
