DM74LS160AN - National Semiconductor

TL/F/10177

54LS160A/DM74LS160A, 54LS162A/DM74LS162A

Synchronous Presettable BCD Decade Counters

May 1992

54LS160A/DM74LS160A, 54LS162A/DM74LS162A

Synchronous Presettable BCD Decade Counters

General Description

The ’LS160 and ’LS162 are high speed synchronous dec-

ade counters operating in the BCD (8421) sequence. They

are synchronously presettable for application in programma-

ble dividers and have two types of Count Enable inputs plus

a Terminal Count output for versatility in forming synchro-

nous multistage counters. The ’LS160 has an asynchronous

Master Reset input that overrides all other inputs and forces

the outputs LOW. The ’LS162 has a Synchronous Reset

input that overrides counting and parallel loading and allows

all outputs to be simultaneously reset on the rising edge of

the clock.

Features

YSynchronous counting and loading

YHigh speed synchronous expansion

YTypical count rate of 35 MHz

YFully edge triggered

Connection Diagram

Dual-In-Line Package

TL/F/10177–1

*MR for ’LS160

*SR for ’LS162

Order Number 54LS160ADMQB, 54LS160AFMQB, 54LS160ALMQB,

54LS162ADMQB, 54LS162AFMQB, 54LS162ALMQB, DM74LS160AM,

DM74LS160AN, DM74LS162AM or DM74LS162AN

See NS Package Number E20A, J16A, M16A, N16E or W16A

Pin Description

Names

CEP Count Enable Parallel Input

CET Count Enable Trickle Input

CP Clock Pulse Input (Active Rising Edge)

MR (’160) Asynchronous Master Reset

Input (Active LOW)

SR (’162) Synchronous Reset

Input (Active LOW)

P0– P3 Parallel Data Inputs

PE Parallel Enable Input

(Active LOW)

Q0– Q3 Flip-Flop Outputs

TC Terminal Count Output

Logic Symbol

TL/F/10177–2

VCC ePin 16 *MR for ’LS160

GND ePin 8 *SR for ’LS162

C1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.

Absolute Maximum Ratings (Note)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales

Office/Distributors for availability and specifications.

Supply Voltage 7V

Input Voltage 7V

Operating Free Air Temperature Range

54LS b55§Ctoa

125§C

DM74LS 0§Ctoa

70§C

Storage Temperature Range b65§Ctoa

150§C

Note:

The ‘‘Absolute Maximum Ratings’’ are those values

beyond which the safety of the device cannot be guaran-

teed. The device should not be operated at these limits. The

parametric values defined in the ‘‘Electrical Characteristics’’

table are not guaranteed at the absolute maximum ratings.

The ‘‘Recommended Operating Conditions’’ table will define

the conditions for actual device operation.

Recommended Operating Conditions

Symbol Parameter 54LS160A/162A DM74LS160A/162A Units

Min Nom Max Min Nom Max

VCC Supply Voltage 4.5 5 5.5 4.75 5 5.25 V

VIH High Level Input Voltage 2 2 V

VIL Low Level Input Voltage 0.7 0.8 V

IOH High Level Output Current b0.4 b0.4 mA

IOL Low Level Output Current 4 8 mA

TAFree Air Operating Temperature b55 125 0 70 §C

ts(H) Setup Time, HIGH or LOW 20 20 ns

ts(L) Pnto CP 20 20

th(H) Hold Time, HIGH or LOW 0.0 0.0 ns

th(L) Pnto CP 0.0 0.0

ts(H) Setup Time, HIGH or LOW 20 20 ns

ts(L) PE to CP 20 20

th(H) Hold Time, HIGH or LOW 0 0 ns

th(L) PE to CP 0 0

ts(H) Setup Time, HIGH or LOW 20 20 ns

ts(L) CEP, CET or SR to CP 20 20

th(H) Hold Time, HIGH or LOW 0 0 ns

th(L) CEP, CET or SR to CP 0 0

tw(H) CP Pulse Width, 15 15 ns

tw(L) HIGH or LOW 25 25

tw(L) MR Pulse Width 15 15 ns

LOW (’160)

trec Recovery Time 20 20 ns

MR to CP (’160)

Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)

Symbol Parameter Conditions Min Typ Max Units

(Note 1)

VIInput Clamp Voltage VCC eMin, IIeb

18 mA b1.5 V

VOH High Level Output VCC eMin, IOH eMax, 54LS 2.5 V

Voltage VIL eMax DM74 2.7

VOL Low Level Output VCC eMin, IOL eMax, 54LS 0.4

Voltage VIH eMin DM74 0.5 V

IOL e4 mA, VCC eMin DM74 0.4

Note 1: All typicals are at VCC e5V, TAe25§C.

Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.

Electrical Characteristics

over recommended operating free air temperature range (unless otherwise noted) (Continued)

Symbol Parameter Conditions Min Typ Max Units

(Note 1)

IIInput Current @Max VCC eMax, VIe7V Other 0.1 mA

Input Voltage PE, CET Inputs 0.2

IIH High Level Input Current VCC eMax, VIe2.7V Other 20 mA

PE, CET Inputs 40

IIL Low Level Input Current VCC eMax, VIe0.4V Inputs 54LS b0.4 mA

DM74 b1.6

PE, CET Inputs b0.8 mA

IOS Short Circuit VCC eMax 54LS b20 b100 mA

Output Current (Note 2) DM74 b20 b100

ICCH Supply Current with VCC eMax, PE eGND 31 mA

Outputs HIGH CP eL, Other Inputs e4.5V

ICCL Supply Current with VCC eMax, VIN eGND 31 mA

Outputs LOW CP eL

Switching Characteristics VCC ea

5.0V, TAea

25§C

RLe2kX

Symbol Parameter CLe15 pF Units

Min Max

fmax Maximum Clock Frequency 25 MHz

tPLH Propagation Delay 25 ns

tPHL CP to TC 21

tPLH Propagation Delay 24 ns

tPHL CP to Qn27

tPLH Propagation Delay 14 ns

tPHL CET to TC 23

tPHL Propagation Delay 28 ns

MR to Qn(’160)

Functional Description

The ’LS160 and ’LS162 count modulo-10 in the BCD (8421)

sequence. From state 9 (HLLH) they increment to state 0

(LLLL). The ’161 and ’163 count modulo-16 binary se-

quence. From state 15 (HHHH) they increment to state 0

(LLLL). The clock inputs of all flip-flops are driven in parallel

through a clock buffer. Thus all changes of the Q outputs

(except due to Master Reset of the ’LS160) occur as a re-

sult of, and synchronous with, the LOW-to-HIGH transition

of the CP input signal. The circuits have four fundamental

modes of operation, in order of precedence: asynchronous

reset (’LS160), synchronous reset (’LS162), parallel load,

count-up and hold. Five control inputsÐMaster Reset (MR,

’LS160), Synchronous Reset (SR, ’LS162), Parallel Enable

(PE), Count Enable Parallel (CEP) and Count Enable Trickle

(CET)Ðdetermine the mode of operation, as shown in the

Mode Select Table. A LOW signal on MR overrides all other

inputs and asynchronously forces all outputs LOW. A LOW

signal on SR overrides counting and parallel loading and

allows all outputs to go LOW on the next rising edge of CP.

A LOW signal on PE overrides counting and allows informa-

tion on the Parallel Data (Pn) inputs to be loaded into the

flip-flops on the next rising edge of CP. With PE and MR

(’LS160) or SR (’LS162) HIGH, CEP and CET permit count-

ing when both are HIGH. Conversely, a LOW signal on ei-

ther CEP or CET inhibits counting.

The ’LS160A and ’LS162A use D-type edge-triggered flip-

flops and changing the SR,PE, CEP and CET inputs when

the CP is in either state does not cause errors, provided that

the recommended setup and hold times, with respect to the

rising edge of CP, are observed.

Functional Description (Continued)

The Terminal Count (TC) output is HIGH when CET is HIGH

and the counter is in its maximum count state (9 for the

decade counters, 15 for the binary counters). To implement

synchronous multistage counters, the TC outputs can be

used with the CEP and CET inputs in two different ways.

These two schemes are shown in the 9310 data sheet. The

TC output is subject to decoding spikes due to internal race

conditions and is therefore not recommended for use as a

clock or asynchronous reset for flip-flops, counters or regis-

ters. In the decade counters of the ’LS160, ’LS162, the TC

output is fully decoded and can only be HIGH in state 9.

LOGIC EQUATIONS:

Count Enable eCEP #CET #PE

TC eQ0 #Q1 #Q2 #Q3 #CET

Mode Select Table

*SR PE CET CEP Action on the Rising

Clock Edge (L)

L X X X RESET (Clear)

H L X X LOAD (Pn

Qn)

H H H H COUNT (Increment)

H H L X NO CHANGE (Hold)

H H X L NO CHANGE (Hold)

*For the ’LS162

HeHIGH Voltage Level

LeLOW Voltage Level

XeImmaterial

State Diagrams

’LS160, ’LS162

TL/F/10177–5

Logic Diagrams

’LS160

TL/F/10177–3

’LS162

TL/F/10177–4

Physical Dimensions inches (millimeters)

Ceramic Leadless Chip Carrier Package (E)

Order Number 54LS160ALMQB or 54LS162ALMQB

NS Package Number E20A

Ceramic Dual-In-Line Package (J)

Order Number 54LS160ADMQB or 54LS162ADMQB

NS Package Number J16A

Physical Dimensions inches (millimeters) (Continued)

16-Lead Small Outline Molded Package (M)

Order Number DM74LS160AM DM74LS162AM

NS Package Number M16A

16-Lead Molded Dual-In-Line Package (N)

Order Number DM74LS160AN or DM74LS162AN

NS Package Number N16E

54LS160A/DM74LS160A, 54LS162A/DM74LS162A

Synchronous Presettable BCD Decade Counters

Physical Dimensions inches (millimeters) (Continued)

16-Lead Ceramic Flat Package (W)

Order Number 54LS160AFMQB or 54LS162AFMQB

NS Package Number W16A

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into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life

failure to perform, when properly used in accordance support device or system, or to affect its safety or

with instructions for use provided in the labeling, can effectiveness.

be reasonably expected to result in a significant injury

to the user.

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