1
®
FN7306.7
EL5175, EL5375
550MHz Differential Line Receivers
The EL5175 and EL5375 are single and triple high bandwidth
amplifiers designed to extract the difference signal from noisy
environments. They are primarily targeted for applications such
as receiving signals from twisted-pair lines or any application
where common mode noise injection is likely to occur.
The EL5175 and EL5375 are stable for a gain of one and
requires two external resistors to set the voltage gain for
each channel.
The output common mode level is set by the reference pin
(VREF), which has a -3dB bandwidth of over 450MHz.
Generally, this pin is grounded but it can be tied to any
voltage reference.
The output can deliver a maximum of ±60mA and is short
circuit protected to withstand a temporary overload condition.
The EL5175 is available in the 8 Ld SOIC and 8 Ld MSOP
packages and the EL5375 in the 24 Ld QSOP package. All
are specified for operation over the full -40°C to +85°C
temperature range.
Pinouts
EL5175
(8 LD SOIC, MSOP)
TOP VIEW
EL5375
(24 LD QSOP)
TOP VIEW
Features
• Differential input range ±2.3V
• 550MHz 3dB bandwidth
• 900V/µs slew rate
• 60mA maximum output current
• Single 5V or dual ±5V supplies
• Low power, 9.6mA per channel
• Pb-free available (RoHS compliant)
Applications
• Twisted-pair receivers
• Differential line receivers
• VGA over twisted-pair
• Differential to single-ended amplification
• Reception of analog signals in a noisy environment
1
2
3
4
8
7
6
5
-
+
OUT
VS-
VS+
EN
FB
IN+
IN-
REF
1
2
3
4
16
15
14
13
5
6
7
12
11
9
8
10
20
19
18
17
24
23
22
21
REF1
INP1
INN1
NC
REF2
INP2
INN2
NC
REF3
INP3
INN3
NC
NC
FB1
OUT1
NC
VSP
VSN
NC
FB2
OUT2
EN
FB3
OUT3
-
+
-
+
-
+
Ordering Information
PART
NUMBER
PART
MARKING PACKAGE
PKG.
DWG. #
EL5175IS* 5175IS 8 Ld SOIC (150 mil) MDP0027
EL5175ISZ*
(Note)
5175ISZ 8 Ld SOIC (Pb-free)
(150 mil)
MDP0027
EL5175IY* 5 8 Ld MSOP (3.0mm) MDP0043
EL5175IYZ*
(Note)
BAAAB 8 Ld MSOP (Pb-free)
(3.0mm)
MDP0043
EL5375IU* EL5375IU 24 Ld QSOP (150 mil) MDP0040
EL5375IUZ*
(Note)
EL5375IUZ 24 Ld QSOP (Pb-free)
(150 mil)
MDP0040
*Add “-T7” or “-T13” suffix for tape and reel. Please refer to TB347
for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination
finish, which is RoHS compliant and compatible with both SnPb and
Pb-free soldering operations). Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
Data Sheet August 25, 2010
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2004, 2005, 2007, 2010. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
2FN7306.7
August 25, 2010
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are
at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Absolute Maximum Ratings (TA = +25°C) Thermal Information
Supply Voltage (VS+ to VS-) . . . . . . . . . . . . . . . . . . . . . . . . . . . .12V
Supply Voltage Rate-of-rise (dV/dT) . . . . . . . . . . . . . . . . . . . . 1V/µs
Input Voltage (IN+, IN- to VS+, VS-). . . . . . VS- - 0.3V to VS+ + 0.3V
Differential Input Voltage (IN+ to IN-) . . . . . . . . . . . . . . . . . . . . ±4.8V
Maximum Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . ±60mA
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +135°C
Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
Electrical Specifications VS+ = +5V, VS- = -5V, TA = +25°C, VIN = 0V, RL = 500Ω, RF = 0, RG = OPEN, CL = 2.7pF, Unless Otherwise
Specified.
PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT
AC PERFORMANCE
BW -3dB Bandwidth AV = 1, CL = 2.7pF 550 MHz
AV = 2, RF = 806, CL = 2.7pF 190 MHz
AV = 10, RF = 806, CL = 2.7pF 20 MHz
BW ± 0.1dB Bandwidth AV = 1, CL = 2.7pF 60 MHz
SR Slew Rate
VOUT = 3VP-P
, 20% to 80%, RL = 100Ω600 V/µs
VOUT = 3VP-P
, 20% to 80%, RL = 500Ω900 V/µs
tSTL Settling Time to 0.1% VOUT = 2VP-P 10 ns
tOVR Output Overdrive Recovery Time 20 ns
GBWP Gain Bandwidth Product 200 MHz
VREFBW (-3dB) VREF -3dB Bandwidth AV = 1, CL = 2.7pF 450 MHz
VREFSR VREF Slew Rate VOUT = 2VP-P
, 20% to 80% 1000 V/µs
VNInput Voltage Noise At f = 10kHz 21 nV/√Hz
INInput Current Noise At f = 10kHz 2.7 pA/√Hz
HD2 Second Harmonic Distortion VOUT = 1VP-P
, 5MHz -70 dBc
HD2 Second Harmonic Distortion VOUT = 1VP-P
, 5MHz -66 dBc
HD3 Third Harmonic Distortion VOUT = 1VP-P
, 5MHz -94 dBc
HD3 Third Harmonic Distortion VOUT = 1VP-P
, 5MHz -84 dBc
dG Differential Gain at 3.58MHz RL = 150Ω , AV = 2 0.1 %
dθDifferential Phase at 3.58MHz RL = 150Ω , AV = 2 0.1 °
eSChannel Separation (EL5375) At f = 100kHz 90 dB
INPUT CHARACTERISTICS
VOS Input Referred Offset Voltage EL5175 -3 ±40 mV
EL5375 -3 ±30 mV
IIN Input Bias Current (VIN, VINB, VREF) -25 -12.5 -6 µA
RIN Differential Input Resistance 150 kΩ
CIN Differential Input Capacitance 1 pF
DMIR Differential Mode Input Range ±2.1 ±2.3 ±2.5 V
CMIR Common Mode Input Range at VIN+, VIN- -4.3 +3.3 V
EL5175, EL5375
3FN7306.7
August 25, 2010
VREFIN+ Reference Input - Positive VIN+ = VIN- = 0V 3.3 3.5 V
VREFIN- Reference Input - Negative VIN+ = VIN- = 0V -3.9 -3.6 V
CMRR Input Common Mode Rejection Ratio VIN = ±2.5V 75 95 dB
Gain Gain Accuracy EL5175, VIN = 1V 0.979 0.994 1.009 V
EL5375, VIN = 1V 0.977 0.992 1.007 V
OUTPUT CHARACTERISTICS
VOUT Positive Output Voltage Swing RL = 500Ω to GND 3.3 3.54 V
Negative Output Voltage Swing RL = 500Ω to GND -3.95 -3.6 V
IOUT(Max) Maximum Output Current RL = 10Ω±40 ±67 mA
ROUT Output Impedance 130 mΩ
SUPPLY
VSUPPLY Supply Operating Range VS+ to VS-4.7511V
IS (ON) Power Supply Current Per Channel -
Enabled
89.611mA
IS (OFF)+ Positive Power Supply Current - Disabled EN pin tied to 4.8V, EL5175 80 100 µA
EN pin tied to 4.8V, EL5375 1.7 5 µA
IS (OFF)- Negative Power Supply Current - Disabled -150 -120 -90 µA
PSRR Power Supply Rejection Ratio VS from ±4.5V to ±5.5V 45 56 dB
ENABLE
tEN Enable Time 80 ns
tDS Disable Time 1.2 µs
VIH EN Pin Voltage for Power-up VS+ - 1.5 V
VIL EN Pin Voltage for Shutdown VS+ - 0.5 V
IIH-EN EN Pin Input Current High Per Channel At VEN = 5V 40 60 µA
IIL-EN EN Pin Input Current Low Per Channel At VEN = 0V -10 -3 µA
Electrical Specifications VS+ = +5V, VS- = -5V, TA = +25°C, VIN = 0V, RL = 500Ω, RF = 0, RG = OPEN, CL = 2.7pF, Unless Otherwise
Specified. (Continued)
PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT
EL5175, EL5375
4FN7306.7
August 25, 2010
Pin Descriptions
EL5175 EL5375 PIN NAME PIN FUNCTION
1 FB Feedback input
2 IN+ Non-inverting input
3 IN- Inverting input
4 REF Sets the common mode output voltage level to VREF
5EN
Enabled when this pin is floating or the applied voltage ≤ VS+ - 1.5
6 VS+ Positive supply voltage
7 VS- Negative supply voltage
8 OUT Output voltage
1, 5, 9 REF1, REF2, REF3 Reference input, controls common-mode output voltage
2, 6, 10 INP1, INP2, INP3 Non-inverting inputs
3, 7, 11 INN1, INN2, INN3 Inverting inputs
4, 8, 12, 18, 21, 24 NC No connect, grounded for best crosstalk performance
22, 16, 13 OUT1, OUT2, OUT3 Non-inverting outputs
23, 17, 14 FB1, FB2, FB3 Feedback from outputs
15 EN Enabled when this pin is floating or the applied voltage ≤ VS+ - 1.5
19 VSN Negative supply
20 VSP Positive supply
EL5175, EL5375
5FN7306.7
August 25, 2010
Connection Diagrams
FIGURE 1. EL5175
FIGURE 2. EL5375
FB
INP
INN
REF
OUT
VSN
VSP
EN
1
2
3
4
8
7
6
5
INP
INN
REF
RG
RS2
50Ω
RS3
50Ω
EN
VOUT
-5V
+5V
RS2
50Ω
CL
2.7pF
RL
500Ω
RF = 0Ω
1
2
3
4
16
15
14
13
5
6
7
12
11
9
8
10
20
19
18
17
24
23
22
21
REF1
INP1
INN1
NC
REF2
INP2
INN2
NC
REF3
INP3
INN3
NC
NC
FB1
OUT1
NC
VSP
VSN
NC
FB2
OUT2
EN
FB3
OUT3
RSR3
50Ω
RSN3
50Ω
RSP3
50Ω
RSR2
50Ω
RSN2
50Ω
RSP2
50Ω
RSR1
50Ω
RSN1
50Ω
RSP1
50Ω
REF1
INP1
INN1
REF2
INP2
INN2
REF3
INP3
INN3
+5V
CL2
2.7pF
CL3
2.7pF
OUT3
OUT1
RG
RF
RL1
500Ω
CL1
2.7pF
-5V
OUT2
RG
RF
RL2
500Ω
ENABLE
RL3
500Ω
RG
RF
EL5175, EL5375
6FN7306.7
August 25, 2010
Typical Performance Curves
FIGURE 3. FREQUENCY RESPONSE vs SUPPLY VOLTAGE FIGURE 4. FREQUENCY RESPONSE vs SUPPLY VOLTAGE
FIGURE 5. FREQUENCY RESPONSE vs VARIOUS GAIN FIGURE 6. FREQUENCY RESPONSE vs CL
FIGURE 7. FREQUENCY RESPONSE vs CLFIGURE 8. FREQUENCY RESPONSE FOR VARIOUS RF
AV = 1
RL = 500Ω
CL = 2.7pF
1M 10M 100M 1G
FREQUENCY (Hz)
MAGNITUDE (dB)
4
2
0
-2
-4
-6
VS = ±2.5V
VS = ±5V
AV = 1
RL = 100Ω
CL = 2.7pF
1M 10M 100M 1G
FREQUENCY (Hz)
MAGNITUDE (dB)
4
2
0
-2
-4
-6
VS = ±2.5V
VS = ±5V
VS = ±5V
RL = 500Ω
CL = 2.7pF
1M 10M 100M 1G
FREQUENCY (Hz)
NORMALIZED GAIN (dB)
4
2
0
-2
-4
-6
AV = 10
AV = 5
AV = 2
AV = 1
VS = ±5V
RL = 500Ω
AV = 1
1M 10M 100M 1G
FREQUENCY (Hz)
MAGNITUDE (dB)
5
3
1
-1
-3
-5
CL = 15pF
CL = 2.7pF
CL = 0pF
CL = 10pF
VS = ± 2.5V
RL = 500Ω
AV = 1
1M 10M 100M 1G
FREQUENCY (Hz)
MAGNITUDE (dB)
5
3
1
-1
-3
-5
CL = 15pF
CL = 2.7pF
CL = 0pF
CL = 10pF
1M 10M 100M 1G
FREQUENCY (Hz)
NORMALIZED GAIN (dB)
4
2
0
-2
-4
-6
VS = ±5V
RL = 500Ω
AV = 2
CL = 2.7pF RF = 1kΩ
RF = 500Ω
RF = 806Ω
RF = 200Ω
EL5175, EL5375
7FN7306.7
August 25, 2010
FIGURE 9. FREQUENCY RESPONSE FOR VREF FIGURE 10. OPEN LOOP GAIN
FIGURE 11. OUTPUT IMPEDANCE vs FREQUENCY FIGURE 12. PSRR vs FREQUENCY
FIGURE 13. CMRR vs FREQUENCY FIGURE 14. VOLTAGE AND CURRENT NOISE vs FREQUENCY
Typical Performance Curves (Continued)
1M 10M 100M 1G
FREQUENCY (Hz)
NORMALIZED GAIN (dB)
4
2
0
-2
-4
-6
RL = 500Ω
AV = 1
CL = 2.7pF
VS = ±2.5V
VS = ±5V
GAIN (dB)
60
40
20
0
-20
-40
10k 100k 10M
FREQUENCY (Hz)
1M 100M 1G
PHASE (°)
90
0
-90
-180
-270
-360
10k 100k 1M 100M
FREQUENCY (Hz)
IMPEDANCE (Ω)
100
10
1
0.1
10M
PSRR (dB)
30
10
-10
-50
-70
-90
10k 100k 10M
FREQUENCY (Hz)
1M 100M
PSRR+
PSRR-
-30
CMRR (dB)
120
100
80
40
20
-90
1k 10k 10M
FREQUENCY (Hz)
1M 1G
60
100M100k
EN
IN
VOLTAGE NOISE (nV/√Hz),
CURRENT NOISE (pA/√Hz)
1k
100
10
1
10 100 100k
FREQUENCY (Hz)
10k 10M1M1k
EL5175, EL5375
8FN7306.7
August 25, 2010
FIGURE 15. CHANNEL ISOLATION vs FREQUENCY
(EL5375 ONLY)
FIGURE 16. HARMONIC DISTORTION vs OUTPUT VOLTAGE
FIGURE 17. HARMONIC DISTORTION vs LOAD RESISTANCE FIGURE 18. HARMONIC DISTORTION vs FREQUENCY
FIGURE 19. SMALL SIGNAL TRANSIENT RESPONSE FIGURE 20. LARGE SIGNAL TRANSIENT RESPONSE
Typical Performance Curves (Continued)
GAIN (dB)
0
-20
-60
-80
-100
100k 1M
FREQUENCY (Hz)
100M 1G
-40
10M
CH1 ↔ CH2, CH2 ↔ CH3
CH1 ↔ CH3
VS = ±5V
f = 5MHz
RL = 500Ω
1357
VOP-P (V)
DISTORTION (dB)
-40
-50
-60
-70
-80
-100
HD2 (A
V
= 2)
246
-90
HD2 (A
V
= 1)
HD3 (A
V
= 2)
HD3 (AV = 1)
HD2 (AV = 2)
HD3 (A
V
= 2)
HD3 (A
V
= 1)
100 400 800 1k
RLOAD (Ω)
DISTORTION (dB)
-50
-100
200 600 900500300 700
-60
-70
-80
-90
HD2 (A
V
= 1)
VS = ±5V
f = 5MHz
VOP-P = 1V (AV = 1)
VOP-P = 2V (AV = 2)
HD2 (A
V
= 2)
015 3540
RLOAD (Ω)
DISTORTION (dB)
-50
-100
5252010 30
-60
-70
-80
-90 VS = ±5V
RL = 500Ω
VOP-P = 1V (AV = 1)
VOP-P = 2V (AV = 2)
HD2 (A
V
= 1)
HD3 (A
V
= 2)
HD3 (AV = 1)
10ns/DIV
50mV/DIV
10ns/DIV
0.5V/DIV
EL5175, EL5375
9FN7306.7
August 25, 2010
Simplified Schematic
FIGURE 21. ENABLED RESPONSE FIGURE 22. DISABLED RESPONSE
FIGURE 23. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
FIGURE 24. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
Typical Performance Curves (Continued)
100ns/DIV
CH1
CH2
M = 100ns
CH1 = 200mV/DIV
CH2 = 5V/DIV
400ns/DIV
CH1
CH2
M = 400ns
CH1 = 200mV/DIV
CH2 = 5V/DIV
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
870mW
625mW
486mW
QSOP24
θJA = +115°C/W
MSOP8
θJA = +206°C/W
0
AMBIENT TEMPERATURE (°C)
25 125 15085 10050 75
POWER DISSIPATION (W)
1.2
1.0
0.2
0
0.6
0.4
0.8
SO8
θJA = +160°C/W
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
0
AMBIENT TEMPERATURE (°C)
POWER DISSIPATION (W)
1.4
25 125 15085 10050 75
1.2
0.2
0
0.6
0.4
1.0
0.8
1.136W
909mW
870mW
MSOP8
θJA = +115°C/W
QSOP24
θJA = +88°C/W
SO8
θJA = +110°C/W
R2
R1
R4
R3
RD2
RD1
Q8
FB
Q4
VREF
Q3
VIN-
Q2
VIN+
Q1
Q6
VS+
I4
I3
I2
I1
Q7VB1
VS-
25
Q9
VB2
x1 VOUT
CC
EL5175, EL5375
10 FN7306.7
August 25, 2010
Description of Operation and Application
Information
Product Description
The EL5175 and EL5375 are wide bandwidth, low power
and single/differential ended to single-ended output
amplifiers. The EL5175 is a single channel differential to
single-ended amplifier. The EL5375 is a triple channel
differential to single ended amplifier. The EL5175 and
EL5375 are internally compensated for closed loop gain of
+1 orgreater. Connected in gain of 1 and driving a 500Ω
load, the EL5175 and EL5375 have a -3dB bandwidth of
550MHz. Driving a 150Ω load at gain of 2, the bandwidth is
about 130MHz. The bandwidth at the REF input is about
450MHz. The EL5175 and EL5375 is available with a
power-down feature to reduce the power while the amplifier
is disabled.
Input, Output and Supply Voltage Range
The EL5175 and EL5375 have been designed to operate
with a single supply voltage of 5V to 10V or a split supplies
with its total voltage from 5V to 10V. The amplifiers have an
input common mode voltage range from -4.3V to 3.3V for
±5V supply. The differential mode input range (DMIR)
between the two inputs is approximately -2.3V to +2.3V. The
input voltage range at the REF pin is from -3.6V to 3.3V. If
the input common mode or differential mode signal is outside
the above-specified ranges, it will cause the output signal to
become distorted.
The output of the EL5175 and EL5375 can swing from -3.9V
to 3.5V at 500Ω load at ±5V supply. As the load resistance
becomes lower, the output swing is reduced respectively.
Overall Gain Settings
The gain setting for the EL5175 and EL5375 is similar to the
conventional operational amplifier. The output voltage is
equal to the difference of the inputs plus VREF and then
times the gain.
Choice of Feedback Resistor and Gain Bandwidth
Product
For applications that require a gain of +1, no feedback
resistor is required. Just short the OUT+ pin to FBP pin and
OUT- pin to FBN pin. For gains greater than +1, the
feedback resistor forms a pole with the parasitic capacitance
at the inverting input. As this pole becomes smaller, the
amplifier's phase margin is reduced. This causes ringing in
the time domain and peaking in the frequency domain.
Therefore, RF has some maximum value that should not be
exceeded for optimum performance. If a large value of RF
must be used, a small capacitor in the few Pico farad range
in parallel with RF can help to reduce the ringing and
peaking at the expense of reducing the bandwidth.
The bandwidth of the EL5175 and EL5375 depends on the
load and the feedback network. RF and RG appear in
parallel with the load for gains other than +1. As this
combination gets smaller, the bandwidth falls off.
Consequently, RF also has a minimum value that should not
be exceeded for optimum bandwidth performance. For gain
of +1, RF = 0 is optimum. For the gains other than +1,
optimum response is obtained with RF between 500Ω to
1kΩ. For AV = 2 and RF = RG = 806Ω, the BW is about
190MHz and the frequency response is very flat.
The EL5175 and EL5375 have a gain bandwidth product of
200MHz. For gains ≥5, its bandwidth can be predicted by
using Equation 2:
Driving Capacitive Loads and Cables
The EL5175 and EL5375 can drive 15pF capacitance in
parallel with 500Ω load to ground with less than 4.5dB of
peaking at a gain of +1. If less peaking is desired in
applications, a small series resistor (usually between 5Ω to
50Ω) can be placed in series with each output to eliminate
most peaking. However, this will reduce the gain slightly. If
the gain setting is greater than 1, the gain resistor RG can
then be chosen to make up for any gain loss, which may be
created by the additional series resistor at the output.
When used as a cable driver, double termination is always
recommended for reflection-free performance. For those
applications, a back-termination series resistor at the
amplifier's output will isolate the amplifier from the cable and
allow extensive capacitive drive. However, other applications
may have high capacitive loads without a back-termination
resistor. Again, a small series resistor at the output can help
to reduce peaking.
Disable/Power-Down
The EL5175 and EL5375 can be disabled and its outputs
placed in a high impedance state. The turn-off time is about
1.2µs and the turn-on time is about 80ns. When disabled,
the amplifier's supply current is reduced to 80µA for IS+ and
120µA for IS- typically, thereby effectively eliminating the
VOV(IN+V
IN-V
REF
+)1
RF
RG
--------
+
⎝⎠
⎜⎟
⎛⎞
×–= (EQ. 1)
-
+
-
+
ΣG/B VO
EN
VIN+
VIN-
VREF
FB
RG
RF
FIGURE 25.
Gain BW 200MHz=×(EQ. 2)
EL5175, EL5375
11 FN7306.7
August 25, 2010
power consumption. The amplifier's power-down can be
controlled by standard CMOS signal levels at the ENABLE
pin. The applied logic signal is relative to the VS+ pin. Letting
the EN pin float or applying a signal that is less than 1.5V
below VS+ will enable the amplifier. The amplifier will be
disabled when the signal at the EN pin is above VS+ - 0.5V.
If a TTL signal is used to control the enabled/disabled
function, Figure 26 could be used to convert the TTL signal
to CMOS signal.
Output Drive Capability
The EL5175 and EL5375 have internal short circuit
protection. Its typical short circuit current is ±67mA. If the
output is shorted indefinitely, the power dissipation could
easily increase such that the part will be destroyed.
Maximum reliability is maintained if the output current never
exceeds ±60mA. This limit is set by the design of the internal
metal interconnections.
Power Dissipation
With the high output drive capability of the EL5175 and
EL5375, it is possible to exceed the +135°C absolute
maximum junction temperature under certain load current
conditions. Therefore, it is important to calculate the
maximum junction temperature for the application to
determine if the load conditions or package types need to be
modified for the amplifier to remain in the safe operating
area.
The maximum power dissipation allowed in a package is
determined according to Equation 3:
•T
JMAX = Maximum junction temperature
•T
AMAX = Maximum ambient temperature
•θJA = Thermal resistance of the package
Assume the REF pin is tired to GND for VS = ±5V
application, the maximum power dissipation actually
produced by an IC is the total quiescent supply current times
the total power supply voltage, plus the power in the IC due
to the load, or:
For sourcing, see Equation 4:
For sinking, see Equation 5:
Where:
•V
S = Total supply voltage
•I
SMAX = Maximum quiescent supply current per channel
•V
OUT = Maximum output voltage of the application
•R
LOAD = Load resistance
•I
LOAD = Load current
• i = Number of channels
By setting the two PDMAX equations equal to each other, we
can solve the output current and RLOAD to avoid the device
overheat.
Power Supply Bypassing and Printed Circuit
Board Layout
As with any high frequency device, a good printed circuit
board layout is necessary for optimum performance. Lead
lengths should be as short as possible. The power supply
pin must be well bypassed to reduce the risk of oscillation.
For normal single supply operation, where the VS- pin is
connected to the ground plane, a single 4.7µF tantalum
capacitor in parallel with a 0.1µF ceramic capacitor from VS+
to GND will suffice. This same capacitor combination should
be placed at each supply pin to ground if split supplies are to
be used. In this case, the VS- pin becomes the negative
supply rail.
For good AC performance, parasitic capacitance should be
kept to a minimum. Use of wire-wound resistors should be
avoided because of their additional series inductance. Use
of sockets should also be avoided if possible. Sockets add
parasitic inductance and capacitance that can result in
compromised performance. Minimizing parasitic capacitance
at the amplifier's inverting input pin is very important. The
feedback resistor should be placed very close to the
inverting input pin. Strip line design techniques are
recommended for the signal traces.
1k
10k
5V
EN
CMOS/TTL
FIGURE 26. CONVERSION OF TTL SIGNAL TO CMOS SIGNAL
PDMAX
TJMAX TAMAX
–
ΘJA
---------------------------------------------
=(EQ. 3)
PDMAX VSISMAX VS+(VOUT)VOUT
RLOAD
--------------------i××–+×=(EQ. 4)
PDMAX VSISMAX VOUT
(VS-)ILOAD]i××–+×[=(EQ. 5)
EL5175, EL5375
12 FN7306.7
August 25, 2010
Typical Applications
As the signal is transmitted through a cable, the high
frequency signal will be attenuated. One way to compensate
this loss is to boost the high frequency gain at the receiver
side.
Level Shifter and Signal Summer
The EL5175 and EL5375 contains two pairs of differential
pair input stages. It makes the inputs all high impedance. To
take advantage of the two high impedance inputs, the
EL5175 and EL5375 can be used as a signal summer to add
two signals together. One signal can be applied to VIN+; the
second signal can be applied to REF and VIN- is ground.
The output is equal to Equation 6:
Also, the EL5175 and EL5375 can be used as a level shifter
by applying a level control signal to the REF input.
0Ω
VFB
VINB
VREF
EL5175/
EL5375
EL5173,
EL5373 VOUT
50
50
ZO = 100Ω
VIN
50Ω
50Ω
FIGURE 27. TWISTED PAIR CABLE RECEIVER
R2
VFB
VINB
VREF
EL5175,
EL5375 VOUT
VIN
50Ω
50Ω
R1
R3
C1
ZO = 100Ω
fAfCf
GAIN
(dB)
1 + R2/R1
1 + R2 / (R1 + R3)
FIGURE 28. COMPENSATED LINE RECEIVER
VOVIN
(+V
REF)Gain×+= (EQ. 6)
EL5175, EL5375
13 FN7306.7
August 25, 2010
EL5175, EL5375
Small Outline Package Family (SO)
GAUGE
PLANE
A2
A1 L
L1
DETAIL X
4° ±4°
SEATING
PLANE
eH
b
C
0.010 BMCA
0.004 C
0.010 BMCA
B
D
(N/2)
1
E1
E
NN (N/2)+1
A
PIN #1
I.D. MARK
h X 45°
A
SEE DETAIL “X”
c
0.010
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO)
SYMBOL
INCHES
TOLERANCE NOTESSO-8 SO-14
SO16
(0.150”)
SO16 (0.300”)
(SOL-16)
SO20
(SOL-20)
SO24
(SOL-24)
SO28
(SOL-28)
A 0.068 0.068 0.068 0.104 0.104 0.104 0.104 MAX -
A1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 ±0.003 -
A2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 ±0.002 -
b 0.017 0.017 0.017 0.017 0.017 0.017 0.017 ±0.003 -
c 0.009 0.009 0.009 0.011 0.011 0.011 0.011 ±0.001 -
D 0.193 0.341 0.390 0.406 0.504 0.606 0.704 ±0.004 1, 3
E 0.236 0.236 0.236 0.406 0.406 0.406 0.406 ±0.008 -
E1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 ±0.004 2, 3
e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 Basic -
L 0.025 0.025 0.025 0.030 0.030 0.030 0.030 ±0.009 -
L1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 Basic -
h 0.013 0.013 0.013 0.020 0.020 0.020 0.020 Reference -
N 8 14 16 16 20 24 28 Reference -
Rev. M 2/07
NOTES:
1. Plastic or metal protrusions of 0.006” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994
14 FN7306.7
August 25, 2010
EL5175, EL5375
Mini SO Package Family (MSOP)
1
(N/2)
(N/2)+1
N
PLANE
SEATING
N LEADS
0.10 C
PIN #1
I.D.
E1E
b
DETAIL X
3° ±3°
GAUGE
PLANE
SEE DETAIL "X"
c
A
0.25
A2
A1 L
0.25 C A B
D
A
M
B
e
C
0.08 C A B
M
H
L1
MDP0043
MINI SO PACKAGE FAMILY
SYMBOL
MILLIMETERS
TOLERANCE NOTESMSOP8 MSOP10
A1.101.10 Max. -
A1 0.10 0.10 ±0.05 -
A2 0.86 0.86 ±0.09 -
b 0.33 0.23 +0.07/-0.08 -
c0.180.18 ±0.05 -
D 3.00 3.00 ±0.10 1, 3
E4.904.90 ±0.15 -
E1 3.00 3.00 ±0.10 2, 3
e0.650.50 Basic -
L0.550.55 ±0.15 -
L1 0.95 0.95 Basic -
N 8 10 Reference -
Rev. D 2/07
NOTES:
1. Plastic or metal protrusions of 0.15mm maximum per side are not
included.
2. Plastic interlead protrusions of 0.25mm maximum per side are
not included.
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
15
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN7306.7
August 25, 2010
EL5175, EL5375
Quarter Size Outline Plastic Packages Family (QSOP)
0.010 CAB
SEATING
PLANE
DETAIL X
EE1
1(N/2)
(N/2)+1
N
PIN #1
I.D. MARK
b
0.004 C
c
A
SEE DETAIL "X"
A2
4°±4°
GAUGE
PLANE
0.010
L
A1
D
B
H
C
e
A
0.007 CAB
L1
MDP0040
QUARTER SIZE OUTLINE PLASTIC PACKAGES FAMILY
SYMBOL
INCHES
TOLERANCE NOTESQSOP16 QSOP24 QSOP28
A 0.068 0.068 0.068 Max. -
A1 0.006 0.006 0.006 ±0.002 -
A2 0.056 0.056 0.056 ±0.004 -
b 0.010 0.010 0.010 ±0.002 -
c 0.008 0.008 0.008 ±0.001 -
D 0.193 0.341 0.390 ±0.004 1, 3
E 0.236 0.236 0.236 ±0.008 -
E1 0.154 0.154 0.154 ±0.004 2, 3
e 0.025 0.025 0.025 Basic -
L 0.025 0.025 0.025 ±0.009 -
L1 0.041 0.041 0.041 Basic -
N 16 24 28 Reference -
Rev. F 2/07
NOTES:
1. Plastic or metal protrusions of 0.006” maximum per side are not
included.
2. Plastic interlead protrusions of 0.010” maximum per side are not
included.
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
