MM74HC74N - National Semiconductor

TL/F/5106

MM54HC74A/MM74HC74A Dual D Flip-Flop with Preset and Clear

January 1988

MM54HC74A/MM74HC74A

Dual D Flip-Flop with Preset and Clear

General Description

The MM54HC74A/MM74HC74A utilizes advanced silicon-

gate CMOS technology to achieve operating speeds similar

to the equivalent LS-TTL part. It possesses the high noise

immunity and low power consumption of standard CMOS

integrated circuits, along with the ability to drive 10 LS-TTL

loads.

This flip-flop has independent data, preset, clear, and clock

inputs and Q and Q outputs. The logic level present at the

data input is transferred to the output during the positive-go-

ing transition of the clock pulse. Preset and clear are inde-

pendent of the clock and accomplished by a low level at the

appropriate input.

The 54HC/74HC logic family is functionally and pinout com-

patible with the standard 54LS/74LS logic family. All inputs

are protected from damage due to static discharge by inter-

nal diode clamps to VCC and ground.

Features

YTypical propagation delay: 20 ns

YWide power supply range: 2–6V

YLow quiescent current: 40 mA maximum (74HC Series)

YLow input current: 1 mA maximum

YFanout of 10 LS-TTL loads

Connection and Logic Diagrams

Dual-In-Line Package

TL/F/5106–1

Order Number MM54HC74A or MM74HC74A

Truth Table

Inputs Outputs

PR CLR CLK D Q Q

LH XXHL

HL XXLH

LL XXH*H*

HH L

LL H

H H L X Q0 Q0

Note: Q0ethe level of Q before the indicated input condi-

tions were established.

*This configuration is nonstable; that is, it will not persist

when preset and clear inputs return to their inactive (high)

level.

TL/F/5106– 2

C1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.

Absolute Maximum Ratings (Notes1&2)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales

Office/Distributors for availability and specifications.

Supply Voltage (VCC)b0.5 to a7.0V

DC Input Voltage (VIN)b1.5 to VCCa1.5V

DC Output Voltage (VOUT)b0.5 to VCCa0.5V

Clamp Diode Current (IIK,I

OK)g20 mA

DC Output Current, per pin (IOUT)g25 mA

DC VCC or GND Current, per pin (ICC)g50 mA

Storage Temperature Range (TSTG)b65§Ctoa

150§C

Power Dissipation (PD)

(Note 3) 600 mW

S.O. Package only 500 mW

Lead Temp. (TL) (Soldering 10 seconds) 260§C

Operating Conditions

Min Max Units

Supply Voltage (VCC)26V

DC Input or Output Voltage 0 VCC V

(VIN,OUT)

Operating Temp. Range (TA)

MM74HC b40 a85 §C

MM54HC b55 a125 §C

Input Rise or Fall Times

VCCe2.0V(tr,t

) 1000 ns

VCCe4.5V 500 ns

VCCe6.0V 400 ns

DC Electrical Characteristics (Note 4)

TAe25§C74HC 54HC

Symbol Parameter Conditions VCC TAeb40 to 85§CT

eb55 to 125§CUnits

Typ Guaranteed Limits

VIH Minimum High Level 2.0V 1.5 1.5 1.5 V

Input Voltage 4.5V 3.15 3.15 3.15 V

6.0V 4.2 4.2 4.2 V

VIL Maximum Low Level 2.0V 0.5 0.5 0.5 V

Input Voltage** 4.5V 1.35 1.35 1.35 V

6.0V 1.8 1.8 1.8 V

VOH Minimum High Level VINeVIH or VIL

Output Voltage

IOUT

s20 mA 2.0V 2.0 1.9 1.9 1.9 V

4.5V 4.5 4.4 4.4 4.4 V

6.0V 6.0 5.9 5.9 5.9 V

VINeVIH or VIL

IOUT

s4.0 mA 4.5V 4.3 3.98 3.84 3.7 V

IOUT

s5.2 mA 6.0V 5.2 5.48 5.34 5.2 V

VOL Maximum Low Level VINeVIH or VIL

Output Voltage

IOUT

s20 mA 2.0V 0 0.1 0.1 0.1 V

4.5V 0 0.1 0.1 0.1 V

6.0V 0 0.1 0.1 0.1 V

VINeVIH or VIL

IOUT

s4.0 mA 4.5V 0.2 0.26 0.33 0.4 V

IOUT

s5.2 mA 6.0V 0.2 0.26 0.33 0.4 V

IIN Maximum Input VINeVCC or GND 6.0V g0.1 g1.0 g1.0 mA

Current

ICC Maximum Quiescent VINeVCC or GND 6.0V 4.0 40 80 mA

Supply Current IOUTe0mA

Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.

Note 2: Unless otherwise specified all voltages are referenced to ground.

Note 3: Power Dissipation temperature derating Ð plastic ‘‘N’’ package: b12 mW/§C from 65§Cto85

C; ceramic ‘‘J’’ package: b12 mW/§C from 100§Cto125

Note 4: For a power supply of 5V g10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing

with this supply. Worst case VIH and VIL occur at VCCe5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN,I

CC, and

IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used.

**VIL limits are currently tested at 20% of VCC. The above VIL specification (30% of VCC) will be implemented no later than Q1, CY’89.

AC Electrical Characteristics VCCe5V, TAe25§C, CLe15 pF, tretfe6ns

Symbol Parameter Conditions Typ Guaranteed Units

Limit

fMAX Maximum Operating 72 30 MHz

Frequency

tPHL,t

PLH Maximum Propagation 10 30 ns

Delay Clock to Q or Q

tPHL,t

PLH Maximum Propagation 17 40 ns

Delay Preset or Clear to Q or Q

tREM Minimum Removal Time, 6 5 ns

Preset or Clear to Clock

tsMinimum Setup Time 10 20 ns

Data to Clock

tHMinimum Hold Time 0 0 ns

Clock to Data

tWMinimum Pulse Width 8 16 ns

Clock, Preset or Clear

AC Electrical Characteristics CLe50 pF, tretfe6 ns (unless otherwise specified)

TAe25§C74HC 54HC

Symbol Parameter Conditions VCC TAeb40 to 85§CT

eb55 to 125§CUnits

Typ Guaranteed Limits

fMAX Maximum Operating 2.0V 22 6 5 4 MHz

Frequency 4.5V 72 30 24 20 MHz

6.0V 94 35 28 24 MHz

tPHL,t

PLH Maximum Propagation 2.0V 34 110 140 165 ns

Delay Clock to Q or Q 4.5V 12 22 28 33 ns

6.0V 10 19 24 28 ns

tPHL,t

PLH Maximum Propagation 2.0V 66 150 190 225 ns

Delay Preset or Clear 4.5V 20 30 38 45 ns

ToQorQ 6.0V 16 26 33 38 ns

tREM Minimum Removal Time 2.0V 20 50 65 75 ns

Preset or Clear 4.5V 6 10 13 15 ns

To Clock 6.0V 5 9 11 13 ns

tsMinimum Setup Time 2.0V 35 80 100 120 ns

Data to Clock 4.5V 10 16 20 24 ns

6.0V 8 14 17 20 ns

tHMinimum Hold Time 2.0V 0 0 0 ns

Clock to Data 4.5V 0 0 0 ns

6.0V 0 0 0 ns

tWMinimum, Pulse Width 2.0V 30 80 101 119 ns

Clock, Preset or Clear 4.5V 9 16 20 24 ns

6.0V 8 14 17 20 ns

tTLH,t

THL Maximum Output 2.0V 25 75 95 110 ns

Rise and Fall Time 4.5V 7 15 19 22 ns

6.0V 6 13 16 19 ns

tr,t

fMaximum Input Rise and 2.0V 1000 1000 1000 ns

Fall Time 4.5V 500 500 500 ns

6.0V 400 400 400 ns

CPD Power Dissipation (per flip-flop) 80 pF

Capacitance (Note 5)

CIN Maximum Input 5 10 10 10 pF

Capacitance

Note 5: CPD determines the no load dynamic power consumption, PDeCPD VCC2faICC VCC, and the no load dynamic current consumption, ISeCPD VCC faICC.

MM54HC74A/MM74HC74A Dual D Flip-Flop with Preset and Clear

Physical Dimensions inches (millimeters)

Order Number MM54HC74J or MM74HC74J

NS Package J14A

Order Number MM74HC74N

NS Package N14A

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