MF1114-02 CMOS 4-BIT SINGLE CHIP MICROCOMPUTER S1C60N06 Technical Manual S1C60N06 Technical Hardware NOTICE No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export license from the Ministry of International Trade and Industry or other approval from another government agency. (c) SEIKO EPSON CORPORATION 2001 All rights reserved. The information of the product number change Starting April 1, 2001, the product number will be changed as listed below. To order from April 1, 2001 please use the new product number. For further information, please contact Epson sales representative. Configuration of product number Devices S1 C 60N01 F 0A01 00 Packing specification Specification Package (D: die form; F: QFP) Model number Model name (C: microcomputer, digital products) Product classification (S1: semiconductor) Development tools C 60R08 S5U1 D1 1 00 Packing specification Version (1: Version 1 2) Tool type (D1: Development Tool 1) Corresponding model number (60R08: for S1C60R08) Tool classification (C: microcomputer use) Product classification (S5U1: development tool for semiconductor products) 1: For details about tool types, see the tables below. (In some manuals, tool types are represented by one digit.) 2: Actual versions are not written in the manuals. Comparison table between new and previous number S1C60 Family processors Previous No. E0C6001 E0C6002 E0C6003 E0C6004 E0C6005 E0C6006 E0C6007 E0C6008 E0C6009 E0C6011 E0C6013 E0C6014 E0C60R08 New No. S1C60N01 S1C60N02 S1C60N03 S1C60N04 S1C60N05 S1C60N06 S1C60N07 S1C60N08 S1C60N09 S1C60N11 S1C60N13 S1C60140 S1C60R08 S1C62 Family processors Previous No. E0C621A E0C6215 E0C621C E0C6S27 E0C6S37 E0C623A E0C623E E0C6S32 E0C6233 E0C6235 E0C623B E0C6244 E0C624A E0C6S46 New No. S1C621A0 S1C62150 S1C621C0 S1C6S2N7 S1C6S3N7 S1C6N3A0 S1C6N3E0 S1C6S3N2 S1C62N33 S1C62N35 S1C6N3B0 S1C62440 S1C624A0 S1C6S460 Previous No. E0C6247 E0C6248 E0C6S48 E0C624C E0C6251 E0C6256 E0C6292 E0C6262 E0C6266 E0C6274 E0C6281 E0C6282 E0C62M2 E0C62T3 New No. S1C62470 S1C62480 S1C6S480 S1C624C0 S1C62N51 S1C62560 S1C62920 S1C62N62 S1C62660 S1C62740 S1C62N81 S1C62N82 S1C62M20 S1C62T30 Comparison table between new and previous number of development tools Development tools for the S1C60/62 Family Previous No. ASM62 DEV6001 DEV6002 DEV6003 DEV6004 DEV6005 DEV6006 DEV6007 DEV6008 DEV6009 DEV6011 DEV60R08 DEV621A DEV621C DEV623B DEV6244 DEV624A DEV624C DEV6248 DEV6247 New No. S5U1C62000A S5U1C60N01D S5U1C60N02D S5U1C60N03D S5U1C60N04D S5U1C60N05D S5U1C60N06D S5U1C60N07D S5U1C60N08D S5U1C60N09D S5U1C60N11D S5U1C60R08D S5U1C621A0D S5U1C621C0D S5U1C623B0D S5U1C62440D S5U1C624A0D S5U1C624C0D S5U1C62480D S5U1C62470D Previous No. DEV6262 DEV6266 DEV6274 DEV6292 DEV62M2 DEV6233 DEV6235 DEV6251 DEV6256 DEV6281 DEV6282 DEV6S27 DEV6S32 DEV6S37 EVA6008 EVA6011 EVA621AR EVA621C EVA6237 EVA623A New No. S5U1C62620D S5U1C62660D S5U1C62740D S5U1C62920D S5U1C62M20D S5U1C62N33D S5U1C62N35D S5U1C62N51D S5U1C62560D S5U1C62N81D S5U1C62N82D S5U1C6S2N7D S5U1C6S3N2D S5U1C6S3N7D S5U1C60N08E S5U1C60N11E S5U1C621A0E2 S5U1C621C0E S5U1C62N37E S5U1C623A0E Previous No. EVA623B EVA623E EVA6247 EVA6248 EVA6251R EVA6256 EVA6262 EVA6266 EVA6274 EVA6281 EVA6282 EVA62M1 EVA62T3 EVA6S27 EVA6S32R ICE62R KIT6003 KIT6004 KIT6007 New No. S5U1C623B0E S5U1C623E0E S5U1C62470E S5U1C62480E S5U1C62N51E1 S5U1C62N56E S5U1C62620E S5U1C62660E S5U1C62740E S5U1C62N81E S5U1C62N82E S5U1C62M10E S5U1C62T30E S5U1C6S2N7E S5U1C6S3N2E2 S5U1C62000H S5U1C60N03K S5U1C60N04K S5U1C60N07K CONTENTS CONTENTS CHAPTER 1 INTRODUCTION ____________________________________________ 1 1.1 1.2 1.3 1.4 CHAPTER Features ......................................................................................................... 1 Block Diagram .............................................................................................. 2 Pin Layout ..................................................................................................... 3 Pin Description ............................................................................................. 4 2 POWER SUPPLY AND INITIAL RESET ____________________________ 5 2.1 Power Supply ................................................................................................ 5 2.1.1 Voltage <VS1> for oscillation circuit and internal circuits ...................... 5 2.1.2 Voltage <VL1-VL3> for LCD driving ......................................................... 5 2.2 Initial Reset ................................................................................................... 6 2.2.1 Reset at power-on ....................................................................................... 6 2.2.2 RESET pin .................................................................................................. 6 2.2.3 Oscillation detection circuit ....................................................................... 7 2.2.4 Watchdog timer ........................................................................................... 7 2.2.5 Initialization by initial reset ....................................................................... 7 2.3 CHAPTER 3 CPU, ROM, RAM ________________________________________ 8 3.1 3.2 3.3 CHAPTER Test Input Pin (TEST) ................................................................................... 7 CPU ............................................................................................................... 8 ROM .............................................................................................................. 8 RAM .............................................................................................................. 8 4 PERIPHERAL CIRCUITS AND OPERATION __________________________ 9 4.1 4.2 Memory Map ................................................................................................. 9 Watchdog Timer ........................................................................................... 11 4.2.1 Configuration of watchdog timer .............................................................. 11 4.2.2 I/O memory of watchdog timer ................................................................. 11 4.2.3 Programming note ..................................................................................... 11 4.3 Oscillation Circuit ....................................................................................... 12 4.3.1 Configuration of oscillation circuit .......................................................... 12 4.3.2 OSC1 oscillation circuit ............................................................................ 12 4.3.3 OSC3 oscillation circuit ............................................................................ 12 4.3.4 Switching the system clock ........................................................................ 13 4.3.5 Clock frequency and instruction execution time ....................................... 13 4.3.6 I/O memory of oscillation circuit .............................................................. 14 4.3.7 Programming notes ................................................................................... 14 4.4 Input Ports (K00-K03, K10-K13) ............................................................... 15 4.4.1 Configuration of input port ....................................................................... 15 4.4.2 Interrupt function ...................................................................................... 15 4.4.3 Mask option ............................................................................................... 16 4.4.4 I/O memory of input port .......................................................................... 16 4.4.5 Programming notes ................................................................................... 17 4.5 Output Ports (R00-R03) .............................................................................. 18 4.5.1 Configuration of output port ..................................................................... 18 4.5.2 Mask option ............................................................................................... 18 4.5.3 Special output ............................................................................................ 19 4.5.4 I/O memory of output ports ....................................................................... 21 4.5.5 Programming note ..................................................................................... 21 S1C60N06 TECHNICAL MANUAL EPSON i CONTENTS 4.6 I/O Ports (P00-P03) .................................................................................... 22 4.6.1 Configuration of I/O port .......................................................................... 22 4.6.2 I/O control register and I/O mode ............................................................ 22 4.6.3 I/O memory of I/O port ............................................................................. 22 4.6.4 Programming notes ................................................................................... 23 4.7 LCD Driver .................................................................................................. 24 4.7.1 Configuration of LCD driver .................................................................... 24 4.7.2 Mask option ............................................................................................... 26 4.7.3 Programming note ..................................................................................... 26 4.8 Clock Timer .................................................................................................. 27 4.8.1 Configuration of clock timer ..................................................................... 27 4.8.2 Interrupt function ...................................................................................... 27 4.8.3 I/O memory of clock timer ........................................................................ 28 4.8.4 Programming notes ................................................................................... 29 4.9 Remote Controller (REM) ............................................................................ 30 4.9.1 Configuration of remote controller ........................................................... 30 4.9.2 Carrier ....................................................................................................... 31 4.9.3 Soft-timer mode ......................................................................................... 33 4.9.4 Hard-timer mode and REM interrupt ....................................................... 34 4.9.5 I/O memory of remote controller .............................................................. 38 4.9.6 Programming notes ................................................................................... 41 4.10 Interrupt and HALT ..................................................................................... 42 4.10.1 Interrupt request ...................................................................................... 42 4.10.2 Interrupt mask register ............................................................................ 44 4.10.3 Interrupt vector ....................................................................................... 44 4.10.4 Programming notes ................................................................................. 45 4.11 Lower Current Dissipation .......................................................................... 46 CHAPTER 5 BASIC EXTERNAL WIRING DIAGRAM ____________________________ 47 CHAPTER 6 ELECTRICAL CHARACTERISTICS ________________________________ 48 6.1 6.2 6.3 6.4 6.5 6.6 6.7 CHAPTER 7 PACKAGE ________________________________________________ 52 7.1 7.2 CHAPTER ii Plastic Package ............................................................................................ 52 Ceramic Package for Test Samples .............................................................. 53 8 PAD LAYOUT _____________________________________________ 54 8.1 8.2 CHAPTER Absolute Maximum Rating ........................................................................... 48 Recommended Operating Conditions .......................................................... 48 DC Characteristics ...................................................................................... 48 Analog Circuit Characteristics and Power Current Consumption ............. 49 Oscillation Characteristics .......................................................................... 49 Input Current Characteristics (For Reference) .......................................... 50 Output Current Characteristics (For Reference) ....................................... 51 Diagram of Pad Layout ................................................................................ 54 Pad Coordinates .......................................................................................... 54 9 PRECAUTIONS ON MOUNTING _________________________________ 55 EPSON S1C60N06 TECHNICAL MANUAL CHAPTER 1: INTRODUCTION CHAPTER 1 INTRODUCTION The S1C60N06 is a single-chip microcomputer which uses an S1C6200B CMOS 4-bit CPU as the core. It contains a 2,048 (words) x 12 (bits) ROM, 128 (words) x 4 (bits) RAM, LCD driver circuit, remote-control carrier output circuit, time base counter and watchdog timer. The S1C60N06 offers a superb solution to infrared remote controller and other applications requiring low power consumption. 1.1 Features Core CPU ........................................... S1C6200B ROM size .......................................... 2,048 words x 12 bits RAM size ........................................... 128 words x 4 bits Clock .................................................. 32.768 kHz crystal oscillation circuit 455 kHz ceramic or CR oscillation circuit (selectable by mask option) Instruction execution time ............ 32 kHz operation: 153, 214 or 366 sec (depending on instructions) 455 kHz operation: 11, 15 or 26 sec (depending on instructions) Instruction set .................................. 100 instructions Input port .......................................... 8 ports (with or without pull-up resistor) Output ports ..................................... 4 ports (clock and buzzer outputs are possible by mask option) I/O port .............................................. 4 ports Infrared remote-control output .... 1 output LCD driver ........................................ 20 segments x 3 or 4 commons (1/3 or 1/4 duty are selectable by mask option) Clock timer ....................................... Built-in Watchdog timer ................................ Built-in Interrupt ............................................ External: 2 input interrupts Internal: 3 timer interrupts (32 Hz, 8 Hz or 2 Hz) 1 remote control output control interrupt Supply voltage ................................. 3 V (2.2 V to 3.5 V) Current consumption (Typ.) ......... 32 kHz operation: 2 A in halt mode 9 A in full run mode 455 kHz operation: 130 A Supply form ..................................... Die form, QFP6-60pin plastic package or QFP13-64pin plastic package S1C60N06 TECHNICAL MANUAL EPSON 1 CHAPTER 1: INTRODUCTION 1.2 Block Diagram ROM System Reset Control 2,048 words x 12 bits RESET Core CPU S1C6200B OSC1 OSC2 OSC3 OSC4 OSC Interrupt Generator RAM Input Port K00-K03 K10-K13 TEST I/O Port P00-P03 128 words x 4 bits COM0-3 SEG0-19 VDD, VSS VL1-VL3, VADJ CA, CB VS1 LCD Driver 20 SEG x 4 COM Power Controller Output Port Watchdog Timer FOUT & Buzzer Clock Timer REM R00, R01 R02 (FOUT, BZ)1 R03 (BZ)1 R33 (REM) 1: Terminal specifications can be selected by mask option. Fig. 1.2.1 S1C60N06 block diagram 2 EPSON S1C60N06 TECHNICAL MANUAL CHAPTER 1: INTRODUCTION 1.3 Pin Layout QFP6-60pin 45 31 46 30 INDEX 60 16 1 15 No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Pin name N.C. N.C. N.C. K00 K01 K02 K03 K10 K11 K12 K13 R00 R01 R02 R03 No. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Pin name R33(REM) SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 N.C. SEG11 TEST No. 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 Pin name No. Pin name RESET 46 VL3 SEG12 47 VADJ SEG13 48 CA SEG14 49 CB SEG15 50 VSS SEG16 51 OSC4 SEG17 52 OSC3 SEG18 53 VS1 SEG19 54 OSC2 COM3 55 OSC1 COM2 56 VDD COM1 57 P03 COM0 58 P02 VL1 59 P01 60 P00 VL2 N.C. = No connection No. 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Pin name No. Pin name RESET 49 N.C. SEG12 50 VADJ SEG13 51 CA SEG14 52 CB SEG15 53 VSS SEG16 54 OSC4 SEG17 55 OSC3 SEG18 56 VS1 SEG19 57 OSC2 COM3 58 OSC1 COM2 59 VDD COM1 60 P03 COM0 61 P02 VL1 62 P01 VL2 63 P00 VL3 64 N.C. N.C. = No connection Fig. 1.3.1 S1C60N06 pin layout (QFP6-60pin) QFP13-64pin 48 33 32 49 INDEX 17 64 1 16 No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pin name N.C. N.C. N.C. N.C. K00 K01 K02 K03 K10 K11 K12 K13 R00 R01 R02 R03 No. 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Pin name N.C. R33(REM) SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 N.C. TEST Fig. 1.3.2 S1C60N06 pin layout (QFP13-64pin) S1C60N06 TECHNICAL MANUAL EPSON 3 CHAPTER 1: INTRODUCTION 1.4 Pin Description Table 1.4.1 Pin description Pin name Pin No. QFP6-60 QFP13-64 56 50 59 53 53 VL1 VL2 VDD I/O Function (I) Power supply pin (+) 56 (I) - Power supply pin (-) Oscillation and internal logic system voltage output pin 44 46 - LCD drive voltage output pin 45 46 47 48 - LCD drive voltage output pin 48, 49 51, 52 - - LCD drive voltage output pin Boost capacitor connecting pin VADJ OSC1 OSC2 47 55 50 58 VL1 adjustment input pin 54 57 I I O OSC3 OSC4 52 51 55 54 K00-K03 K10-K13 P00-P03 4-7 5-8 8-11 60-57 12, 13 9-12 63-60 13, 14 14 15 16 15 16 18 SEG0-19 17-27, 29, 32-39 19-30, 34-41 COM0-3 43-40 31 30 45-42 33 32 VSS VS1 VL3 CA, CB R00, R01 R02 R03 R33(REM) RESET TEST Oscillation input pin (crystal) I Oscillation output pin (crystal) Oscillation input pin (ceramic or CR *) O I I Oscillation output pin (ceramic or CR *) Input port pin Input port pin I/O O O O O O I/O port pin Output port pin Output port pin, BZ or FOUT output pin * Output port pin or BZ output pin * Remote control carrier output port pin LCD segment output pin or DC output pin * O I I LCD common output pin (1/3 duty or 1/4 duty are selectable *) Initial reset input pin Input pin for test Can be selected by mask option 4 EPSON S1C60N06 TECHNICAL MANUAL CHAPTER 2: POWER SUPPLY AND INITIAL RESET CHAPTER 2 POWER SUPPLY AND INITIAL RESET 2.1 Power Supply With a single external power supply () supplied to VDD through VSS, the S1C60N06 generates the necessary internal voltages with the regulated voltage circuit (<VS1> for oscillator and internal circuit) and the LCD voltage circuit (<VL2 and VL3 or VL1 and VL3> for LCD). Supply voltage: 3 V (2.2 to 3.5 V) Note: External loads cannot be driven by the output voltage of the regulated voltage circuit and LCD voltage circuit. 2.1.1 Voltage <VS1> for oscillation circuit and internal circuits VS1 is a voltage for the oscillation circuit and the internal logic circuits, and is generated by the voltage regulator for stabilizing the oscillation. 2.1.2 Voltage <VL1-VL3> for LCD driving The on-chip LCD voltage circuit generates the voltage levels (VDD, VL1, VL2 and VL3) needed to drive the LCD panel. Figure 2.1.2.1 shows the external connection diagram. VDD VS1 VL1 VL2 VL3 CA 3V CB VSS Fig. 2.1.2.1 External connection in each LCD operation mode For LCD driving, the internal voltage regulator generates the VL1 voltage. The VL2 and VL3 voltage levels are generated by boosting the VL1 voltage. The VL1 voltage can be adjusted by feeding it back to the VADJ pin through RA1 and RA2 as shown in Figure 2.1.2.2. VL ( VDD - VL1) is defined by following equation: VL 1 x (RA1 + RA2) / RA1 Example: VL 1V 1.5 V RA1 2 M RA2 0 1 M RA1 (2 M) RA2 (1 M) VADJ VL1 VADJ VL1 An LCD driving voltage suited to each LCD panel can be obtained by adjusting VL at the VADJ pin. Fig. 2.1.2.2 LCD voltage adjustment circuit S1C60N06 TECHNICAL MANUAL EPSON 5 CHAPTER 2: POWER SUPPLY AND INITIAL RESET 2.2 Initial Reset The S1C60N06 must be initially reset to initialize its circuits. Initial reset is triggered by an external reset (RESET) signal, oscillation detector signal, or watchdog timer signal. The RESET input is needed for initialization at power-on. OSC1 oscillation circuit OSC1 OSC2 fOSC1 Watchdog timer WDRST VDD Oscillation detector Initial reset RESET S1C60N06 Fig. 2.2.1 Initial reset circuit configuration 2.2.1 Reset at power-on At power-on, the initial reset signal has two functions. One function is to initialize a circuit and the other to sustain the initializing function until the OSC3 oscillation is stabilized. Thus, the RESET input must be held at low level for at least 0.5 second after power-on. After the RESET input reaches the high level and the OSC1 oscillation circuit starts operating, several milliseconds later, the system is released from internal reset and starts to operate. VDD OSC3 RESET Detect oscillation Watchdog timer Internal initial reset (Vss : GND) Fig. 2.2.1.1 Initial reset sequence at power-on 2.2.2 RESET pin The RESET signal directly initializes the S1C60N06. The system is reset when RESET = L, and released from the reset state when RESET = H. As the RESET pin is pulled up and receives a schmitt trigger input, it can be used as a power-on reset circuit if the RESET pin is connected with the VSS pin via a capacitor as shown in Figure 2.2.2.1. A reset switch must be provided to obtain an assured reset effect at power-on without being influenced by possible power. This is especially important for a reset operation without the use of the OSC3 oscillation circuit, in which case the system clock (OSC1) must be ON before the system is released from the reset state. VDD RESET To reset circuit CSR VSS VSS S1C60N06 Fig. 2.2.2.1 Power-on reset circuit 6 EPSON S1C60N06 TECHNICAL MANUAL CHAPTER 2: POWER SUPPLY AND INITIAL RESET 2.2.3 Oscillation detection circuit With RESET = H, the oscillation detection circuit receives fOSC1 and makes a f-V conversion. If the OSC1 frequency is greater than a certain value, the oscillation output goes to L to clear the reset state. The time required for f-V conversion depends on fOSC1, and is several milliseconds with fOSC1 = 32 kHz. This time gives a delay for clearing the reset state from the RESET input going to H. The oscillation detection circuit may sometimes not operate normally with the initial resetting due to the circuit, depending on the method of making the power, you should utilize the initial resetting method by the RESET pin. 2.2.4 Watchdog timer The watchdog timer guards the CPU against an unexpected overrun. It uses the OSC1 clock as the source oscillation frequency to perform the increment operation. If the watchdog timer fails to be reset in 3-4 seconds with fOSC1 = 32 kHz, the CPU will be initialized at initial reset. See Section 4.2, "Watchdog Timer", for details. 2.2.5 Initialization by initial reset When the S1C60N06 is initially reset, its internal registers are set as follows: Table 2.2.5.1 Initial status CPU Core Name Symbol Bit size Program counter step PCS 8 Program counter page PCP 4 New page pointer NPP 4 Stack pointer SP 8 Index register X X 8 Index register Y Y 8 Register pointer RP 4 General-purpose register A A 4 General-purpose register B B 4 Interrupt flag I 1 Decimal flag D 1 Zero flag Z 1 Carry flag C 1 Initial value 00H 1H 1H Undefined Undefined Undefined Undefined Undefined Undefined 0 0 Undefined Undefined Peripheral Circuits Bit size Initial value RAM 128 x 4 Undefined Display memory 20 x 4 Undefined Other peripheral circuits - See Section 4.1, "Memory Map". Name 2.3 Test Input Pin (TEST) This pin is used when IC is inspected for shipment. During normal operation connect it to VDD. S1C60N06 TECHNICAL MANUAL EPSON 7 CHAPTER 3: CPU, ROM, RAM CHAPTER 3 CPU, ROM, RAM 3.1 CPU The S1C60N06 employs the S1C6200B core CPU, so that register configuration, instructions, and so forth are virtually identical to those in other processors in the family using the S1C6200/6200A/6200B. Refer to the "S1C6200/6200A Core CPU Manual" for details of the S1C6200B. Note the following points with regard to the S1C60N06: (1) The S1C60N06 does not support the SLEEP function, therefore the SLP instruction cannot be used. (2) Because the ROM capacity is 2,048 words, 12 bits per word, bank bits are unnecessary, and PCB and NBP are not used. (3) The RAM page is set to 0 only, so the page part (XP, YP) of the index register that specifies addresses is invalid. PUSH XP POP XP LD XP,r LD r,XP PUSH YP POP YP LD YP,r LD r,YP 3.2 ROM The built-in ROM, a mask ROM for the program, has a capacity of 2,048 x 12-bit steps. The program area is 8 pages (0-7), each consisting of 256 steps (00H-FFH). After an initial reset, the program start address is set to page 1, step 00H. The interrupt vectors are allocated to page 1, steps 01H-07H. Bank 0 Step 00H Page 0 Step 01H Interrupt vector area Page 1 Page 2 Page 3 Program start address Step 07H Step 08H Page 4 Page 5 Program area Page 6 Page 7 Step FFH 12 bits Fig. 3.2.1 ROM configuration 3.3 RAM The RAM, a data memory for storing a variety of data, has a capacity of 128 words, 4-bit words. When programming, keep the following points in mind: (1) Part of the data memory is used as stack area when saving subroutine return addresses and registers, so be careful not to overlap the data area and stack area. (2) Subroutine calls and interrupts take up three words on the stack. (3) Data memory 000H-00FH is the memory area pointed by the register pointer (RP). 8 EPSON S1C60N06 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map) CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Peripheral circuits (timer, I/O, and so on) of the S1C60N06 are memory mapped. Thus, all the peripheral circuits can be controlled by using memory operations to access the I/O memory. The following sections describe how the peripheral circuits operate. 4.1 Memory Map The data memory of the S1C60N06 has an address space of 175 words, of which 32 words are allocated to display memory and 15 words, to I/O memory. Figure 4.1.1 show the overall memory map for the S1C60N06, and Table 4.1.1, the memory maps for the peripheral circuits (I/O space). Address Low 0 Page 1 2 3 4 5 6 7 8 9 A B C D E F High 0 M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF 1 2 3 4 RAM area (000H-07FH) 128 words x 4 bits (R/W) 5 6 0 7 8 9 A B C D E F Display memory area (0D0H-0EFH) 32 words x 4 bits (W only) I/O memory See Table 4.1.1 Unused area Fig. 4.1.1 Memory map Note: Memory is not mounted in unused area within the memory map and in memory area not indicated in this chapter. For this reason, normal operation cannot be assured for programs that have been prepared with access to these areas. S1C60N06 TECHNICAL MANUAL EPSON 9 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map) Table 4.1.1 I/O memory map Address Register D3 D2 D1 D0 REMSO IREM IK1 IK0 0F0H R/W R WDRST IT2 IT8 IT32 0F1H W R REMC EIREM EIK1 EIK0 EIT8 EIT32 TM01 TM00 TM11 TM10 0F2H R/W TMRUN EIT2 0F3H R/W TM03 TM02 0F4H R TM13 TM12 0F5H R 0 0 CLKCHG OSCC 0F6H R R/W RCDIV RCDUTY RT1 RT0 RIC1 RIC0 MF91 MF90 0F7H R/W RIC3 RIC2 0F8H W ROUT1 ROUT0 0F9H R/W K03 K02 K01 K00 K11 K10 R01 R00 P01 P00 IOC 0 R/W R 0FAH R K13 K12 0FBH R R02 BZ FOUT R03 BZ 0FCH R/W P03 P02 0FEH R/W 0 0 0FFH R 1 Initial value at initial reset 2 Not set in the circuit 10 Comment 1 0 Name Init 1 REMSO 0 Forced REM output (on/off) On Off IREM 4 - 5 Interrupt factor flag (REM) Yes No IK1 4 0 Interrupt factor flag (K10-K13) Yes No IK0 4 0 Interrupt factor flag (K00-K03) Yes No WDRST Reset Reset Watchdog timer reset - IT2 4 0 Interrupt factor flag (clock timer 2 Hz) Yes No IT8 4 0 Interrupt factor flag (clock timer 8 Hz) Yes No IT32 4 0 Interrupt factor flag (clock timer 32 Hz) Yes No REMC REM carrier generation on/off 1 On Off EIREM 0 Enable Mask Interrupt mask register (REM) EIK1 0 Enable Mask Interrupt mask register (K10-K13) EIK0 0 Enable Mask Interrupt mask register (K00-K03) TMRUN 0 Run Reset,Stop Timer run/reset & stop EIT2 0 Enable Mask Interrupt mask register (clock timer 2 Hz) EIT8 0 Enable Mask Interrupt mask register (clock timer 8 Hz) EIT32 0 Enable Mask Interrupt mask register (clock timer 32 Hz) TM03 Timer data (16 Hz) 0 TM02 Timer data (32 Hz) 0 TM01 Timer data (64 Hz) 0 TM00 Timer data (128 Hz) 0 TM13 Timer data (1 Hz) 0 TM12 Timer data (2 Hz) 0 TM11 Timer data (4 Hz) 0 TM10 Timer data (8 Hz) 0 0 3 Unused - 2 - - 0 3 - 2 Unused - - CLKCHG 0 OSC1 OSC3 CPU clock change OSCC 1 OSC3 oscillation on/off On Off D3 D2 Div. ratio RCDIV REM carrier interval - 5 1/8 0 0 - 5 RCDUTY and duty ratio setting 1/8 0 1 - 5 RT1 cycle (division ratio) setting 1/12 1 0 1/12 1 1 - 5 RT0 0: 1/12, 1: 1/16, 2: 1/20, 3: 1/32 RIC3 - 5 - 5 RIC2 REM interrupt counter (0 to 14) - 5 RIC1 - 5 RIC0 ROUT1 0 REM output duration setting (0 to 3) ROUT0 0 MF91 General-purpose register - 5 - 5 MF90 General-purpose register K03 - 2 High Low - 2 High K02 Low K0 input port data - 2 High K01 Low - 2 High K00 Low K13 - 2 High Low - 2 High K12 Low K1 input port data - 2 High K11 Low - 2 High K10 Low 0 R03 High Low R03 output port data 0 BZ On Low Signal on/off when BZ is selected. (mask option) 0 R02 High Low R02 output port data BZ/FOUT 0 On Low Signal on/off when BZ/FOUT is selected. (mask option) R01 0 High Low R01 output port data R00 0 High Low R00 output port data P03 - 2 High Low - 2 High P02 Low P0 I/O port data - 2 High P01 Low - 2 High P00 Low 0 3 - 2 - Unused - 0 3 - 2 - Unused - IOC 0 Output Input I/O port I/O control 0 3 - 2 - Unused - 3 Always "0" being read 5 Undefined 4 Reset (0) immediately after being read EPSON Duty 1/4 3/8 1/3 1/4 S1C60N06 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Watchdog Timer) 4.2 Watchdog Timer 4.2.1 Configuration of watchdog timer The S1C60N06 has a built-in watchdog timer that operates with a divided clock from the OSC1 as the source clock. The watchdog timer must be reset cyclically by the software while it operates. If the watchdog timer is not reset in at least 3-4 seconds (when fOSC1 is 32.768 kHz), it resets the CPU. Figure 4.2.1.1 is the block diagram of the watchdog timer. OSC1 dividing clock Watchdog timer Initial reset signal Watchdog timer reset signal Fig. 4.2.1.1 Watchdog timer block diagram Watchdog timer reset processing in the program's main routine enables detection of program overrun, such as when the main routine's watchdog timer processing is bypassed. Ordinarily this routine is incorporated where periodic processing takes place, just as for the timer interrupt routine. The watchdog timer operates in the HALT mode. If a HALT status continues for 3-4 seconds, the watchdog timer generates a CPU reset signal. The watchdog timer function can be nullified by using the mask option. 4.2.2 I/O memory of watchdog timer Table 4.2.2.1 shows the I/O address and control bit for the watchdog timer. Table 4.2.2.1 Control bit of watchdog timer Address Register D3 D2 D1 D0 WDRST IT2 IT8 IT32 0F1H W R 1 Initial value at initial reset 2 Not set in the circuit Comment 1 0 Name Init 1 WDRST Reset Reset Watchdog timer reset - IT2 4 0 Interrupt factor flag (clock timer 2 Hz) Yes No IT8 4 0 Interrupt factor flag (clock timer 8 Hz) Yes No IT32 4 0 Interrupt factor flag (clock timer 32 Hz) Yes No 3 Always "0" being read 5 Undefined 4 Reset (0) immediately after being read WDRST: Watchdog timer reset (0F1H*D3) Resets the watchdog timer. When "1" is written: Watchdog timer is reset When "0" is written: No operation Reading: Always "0" When "1" is written to WDRST, the watchdog timer is reset and restarts immediately after that. When "0" is written, no operation results. This bit is dedicated for writing, and is always "0" for reading. 4.2.3 Programming note When the watchdog timer is being used, the software must reset it within 3-second cycles. S1C60N06 TECHNICAL MANUAL EPSON 11 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit) 4.3 Oscillation Circuit 4.3.1 Configuration of oscillation circuit The S1C60N06 has two oscillation circuits (OSC1 and OSC3). OSC1 is a crystal oscillation circuit that supplies the operating clock to the CPU and peripheral circuits. OSC3 is either a CR or a ceramic oscillation circuit. When processing with the S1C60N06 requires high-speed operation, the CPU operating clock can be switched from OSC1 to OSC3 by the software. Figure 4.3.1.1 is the block diagram of this oscillation system. OSC1 oscillation circuit Divider To peripheral circuits Clock switch OSC3 oscillation circuit To CPU CPU clock selection signal Oscillation circuit control signal Fig. 4.3.1.1 Oscillation system block diagram 4.3.2 OSC1 oscillation circuit The OSC1 crystal oscillation circuit generates the main clock for the CPU and the peripheral circuits. The oscillation frequency is 32.768 kHz (Typ.). Figure 4.3.2.1 is the block diagram of the OSC1 oscillation circuit. VDD RFX CGX RDX OSC1 X'tal To CPU and peripheral circuits CDX VDD OSC2 Fig. 4.3.2.1 OSC1 oscillation circuit (crystal) As shown in Figure 4.3.2.1, the crystal oscillation circuit can be configured simply by connecting the crystal oscillator (X'tal) of 32.768 kHz (Typ.) between the OSC1 and OSC2 terminals and the trimmer capacitor (CGX) between the OSC1 and VDD terminals. 4.3.3 OSC3 oscillation circuit The S1C60N06 has built-in the OSC3 oscillation circuit that generates the CPU's sub-clock (Typ. 455 kHz) for high speed operation and the source clock for peripheral circuits needing a high speed clock (REM circuit). The mask option enables selection of either the CR or ceramic oscillation circuit. When CR oscillation is selected, only a resistance is required as an external element. When ceramic oscillation is selected, a ceramic oscillator and two capacitors (gate and drain capacitance) are required. Figure 4.3.3.1 is the block diagram of the OSC3 oscillation circuit. CCR OSC3 RCR To CPU and REM circuit OSC4 OSCC (a) CR oscillation circuit 12 EPSON S1C60N06 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit) VDD CGC Ceramic CDC To CPU and REM circuit RDC RFC OSC3 OSC4 OSCC (b) Ceramic oscillation circuit VDD OSC3 OSC4 VS1 (c) When "Not Use" is selected by mask option Fig. 4.3.3.1 OSC3 oscillation circuit As shown in Figure 4.3.3.1, the CR oscillation circuit can be configured simply by connecting the resistor RCR between the OSC3 and OSC4 terminals when CR oscillation is selected. See Chapter 6, "Electrical Characteristics" for resistance value of RCR. When ceramic oscillation is selected, the ceramic oscillation circuit can be configured by connecting the ceramic oscillator (Typ. 455 kHz) between the OSC3 and OSC4 terminals, capacitor CGC between the OSC3 and VDD terminals, and capacitor CDC between the OSC4 and VDD terminals. For both CGC and CDC, connect capacitors that are about 100 pF. The OSC3 ocsillation circuit can be controlled (on and off) using the OSCC register. To reduce current consumption, the OSC3 oscillation circuit should be stopped by the software (OSCC register) if unnecessary. When "Not Use" is selected by mask option, do not connect anything to the OSC3 and OSC4 terminals. 4.3.4 Switching the system clock The CPU system clock is switched to OSC1 or OSC3 by the software (CLKCHG register). When OSC3 is to be used as the CPU clock, it should be done as the following procedure using the software: turn the OSC3 oscillation ON and wait at least 5 msec for oscillation stabilization, then switch the CPU clock after waiting 5 msec or more. When switching from OSC3 to OSC1, switch the CPU clock, then turn the OSC3 oscillation circuit off. OSC1 OSC3 1. Set OSCC to "1" (OSC3 oscillation ON). 2. Maintain 5 msec or more. 3. Set CLKCHG to "1" (OSC1 OSC3). OSC3 OSC1 1. Set CLKCHG to "0" (OSC3 OSC1). 2. Set OSCC to "0" (OSC3 oscillation OFF). 4.3.5 Clock frequency and instruction execution time Table 4.3.5.1 shows the instruction execution time according to each frequency of the system clock. Table 4.3.5.1 Clock frequency and instruction execution time Instruction execution time (sec) 5-clock instruction 7-clock instruction 12-clock instruction OSC1: 32.768 kHz 152.6 213.6 366.2 OSC3: 455 kHz 11.0 15.4 26.4 Clock frequency S1C60N06 TECHNICAL MANUAL EPSON 13 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit) 4.3.6 I/O memory of oscillation circuit Table 4.3.6.1 shows the I/O address and the control bits for the oscillation circuit. Table 4.3.6.1 Control bits of oscillation circuit Address Register Comment Name Init 1 1 0 0 3 Unused - 2 - - 0 0 CLKCHG OSCC 0 3 - 2 Unused - - 0F6H CLKCHG 0 OSC1 OSC3 CPU clock change R R/W OSCC 1 OSC3 oscillation on/off On Off 1 Initial value at initial reset 3 Always "0" being read 5 Undefined 2 Not set in the circuit 4 Reset (0) immediately after being read D3 D2 D1 D0 OSCC: OSC3 oscillation control register (0F6H*D0) Controls oscillation for the OSC3 oscillation circuit. When "1" is written: OSC3 oscillation ON When "0" is written: OSC3 oscillation OFF Reading: Valid When it is necessary to operate the CPU at high speed or output a remote control carrier signal, set OSCC to "1". At other times, set it to "0" to reduce current consumption. At initial reset, this register is set to "1". CLKCHG: CPU system clock switching register (0F6H*D1) The CPU's operation clock is selected with this register. When "1" is written: OSC1 clock is selected When "0" is written: OSC3 clock is selected Reading: Valid When the CPU clock is to be OSC3, set CLKCHG to "0"; for OSC1, set CLKCHG to "1". After turning the OSC3 oscillation ON (OSCC = "1"), switching of the clock should be done after waiting 5 msec or more. At initial reset, this register is set to "0". 4.3.7 Programming notes (1) It takes at least 5 msec from the time the OSC3 oscillation circuit goes on until the oscillation stabilizes. Consequently, when switching the CPU operation clock from OSC1 to OSC3, do this after a minimum of 5 msec have elapsed since the OSC3 oscillation went on. Further, the oscillation stabilization time varies depending on the external oscillator characteristics and conditions of use, so allow ample margin when setting the wait time. (2) When switching the clock from OSC3 to OSC1, use a separate instruction for switching the OSC3 oscillation off. An error in the CPU operation can result if this processing is performed at the same time by the one instruction. 14 EPSON S1C60N06 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports) 4.4 Input Ports (K00-K03, K10-K13) 4.4.1 Configuration of input port The S1C60N06 has two 4-bit general-purpose input ports (K00-K03 and K10-K13). As shown in Figure 4.4.1.1, each input port terminal is provided with a pull-up and a feedback pull-up so that the port is suitable for push switch or key matrix switch input. As the pull-up can be removed by using mask option, the input port can also be used for slide switch input or interface with another LSI. VDD Interrupt request K nm Data bus Mask option Input control V SS Fig. 4.4.1.1 Configuration of input port Input port data can be read on a 4-bit basis (K00-K03, K10-K13) addressed 0FAH and 0FBH. 4.4.2 Interrupt function All input port bits (K00-K03, K10-K13) provide the interrupt function. The interrupt mask registers (EIK0, EIK1) enable the interrupt mask to be selected individually for K0 and K1 terminal groups. An interrupt occurs at the falling edge of an input signal which is not masked and the interrupt factor flags (IK0, IK1) is set to "1". Input interrupt programming related precautions K port input Active status Mask register Factor flag is set Not set When the content of the mask register is rewritten, while the port K input is in the active status. The input interrupt factor flag is set at . Fig. 4.4.2.1 Input interrupt timing When using an input interrupt, if you rewrite the content of the mask register, when the value of the input terminal which becomes the interrupt input is in the active status (input terminal = low status), the factor flag for input interrupt may be set. For example, a factor flag is set with the timing of shown in Figure 4.4.2.1. However, when clearing the content of the mask register with the input terminal kept in the low status and then setting it, the factor flag of the input interrupt is again set at the timing that has been set. Consequently, when the input terminal is in the active status (low status), do not rewrite the mask register (clearing, then setting the mask register), so that a factor flag will only set at the falling edge in this case. When clearing, then setting the mask register, set the mask register, when the input terminal is not in the active status (high status). S1C60N06 TECHNICAL MANUAL EPSON 15 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports) 4.4.3 Mask option An internal pull-up resistor can be selected for each of the eight bits of the input ports (K00-K03, K10- K13). Having selected "pull-up resistor disabled", take care that the input does not float. Select "pull-up resistor enabled" for input ports that are not being used. 4.4.4 I/O memory of input port Table 4.4.4.1 shows the I/O addresses and the control bits for the input port. Table 4.4.4.1 Control bits of input port Address Register D3 D2 D1 D0 REMSO IREM IK1 IK0 0F0H R/W REMC R EIREM EIK1 EIK0 K01 K00 K11 K10 0F2H R/W K03 K02 0FAH R K13 K12 0FBH R 1 Initial value at initial reset 2 Not set in the circuit Comment Name Init 1 1 0 REMSO 0 Forced REM output (on/off) On Off IREM 4 - 5 Interrupt factor flag (REM) Yes No IK1 4 0 Interrupt factor flag (K10-K13) Yes No IK0 4 0 Interrupt factor flag (K00-K03) Yes No REMC REM carrier generation on/off 1 On Off EIREM 0 Enable Mask Interrupt mask register (REM) EIK1 0 Enable Mask Interrupt mask register (K10-K13) EIK0 0 Enable Mask Interrupt mask register (K00-K03) K03 - 2 High Low - 2 High K02 Low K0 input port data - 2 High K01 Low - 2 High K00 Low K13 - 2 High Low - 2 High K12 Low K1 input port data - 2 High K11 Low - 2 High K10 Low 3 Always "0" being read 5 Undefined 4 Reset (0) immediately after being read K00-K03: Input port data (0FAH) K10-K13: Input port data (0FBH) The input data of the input port terminals can be read with these registers. When "1" is read: High level When "0" is read: Low level Writing: Invalid The value read is "1" when the terminal voltage of the input port (K00-K03, K10-K13) goes high (VDD), and "0" when the voltage goes low (VSS). These bits are reading only, so writing cannot be done. EIK0, EIK1: Interrupt mask registers (0F2H*D0, D1) Masking the interrupt of the input port terminal groups can be done with these registers. When "1" is written: Enabled When "0" is written: Masked Reading: Valid With these registers, masking of the input port bits can be done for each of the four-bit terminal groups. At initial reset, these registers are all set to "0". 16 EPSON S1C60N06 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports) IK0, IK1: Interrupt factor flags (0F0H*D0, D1) These flags indicate the occurrence of an input interrupt. When "1" is read: Interrupt has occurred When "0" is read: Interrupt has not occurred Writing: Invalid IK0 and IK1 are the interrupt factor flags corresponding to the input ports K00-K03 and K10-K13, respectively. They are set to "1" at the falling edge of the input signal. From the status of this flag, the software can decide whether an input interrupt has occurred or not. These flags are reset when the software has read them. Reading of interrupt factor flag is available at EI, but be careful in the following cases. If the interrupt mask register value corresponding to the interrupt factor flag to be read is set to "1", an interrupt request will be generated by the interrupt factor flag set timing, or an interrupt request will not be generated. Be very careful when interrupt factor flags are in the same address. At initial reset, this flag is set to "0". 4.4.5 Programming notes (1) When modifying the input port from low level to high level with pull-up resistor, a delay will occur at the rise of the waveform due to time constant of the pull-up resistor and input gate capacities. Provide appropriate waiting time in the program when reading an input port. (2) Reading of the interrupt factor flag is available at EI, but be careful in the following cases. If the interrupt mask register value corresponding to the interrupt factor flag to be read is set to "1", an interrupt request will be generated by the interrupt factor flag set timing, or an interrupt request will not be generated. Be very careful when interrupt factor flags are in the same address. S1C60N06 TECHNICAL MANUAL EPSON 17 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports) 4.5 Output Ports (R00-R03) 4.5.1 Configuration of output port The S1C60N06 has 4 bits of general output ports (R00-R03). Output specifications of the output ports can be selected individually with the mask option. Two kinds of output specifications are available: complementary output and Nch open drain output. Also, the mask option enables the output ports R02 and R03 to be used as special output ports. Figure 4.5.1.1 shows the configuration of the output port. VDD Data bus Mask option Data register R0x Address VSS Fig. 4.5.1.1 Configuration of output ports In the DC output mode, the output terminal goes high (VDD) when "1" is written to the data register and goes low (VSS) when "0" is written. At initial reset, the output terminal goes low. 4.5.2 Mask option The mask option enables the following output port selection. (1) Output specifications of output ports The output specifications for the output port (R00-R03) can be selected from complementary output and Nch open drain output for each of the four bits. However, even when Nch open drain output is selected, a voltage exceeding the power voltage must not be supplied to the output port. (2) Special output In addition to the regular DC output, special output clock signal can be selected for output ports R02 and R03, as shown in Table 4.5.2.1. Table 4.5.2.1 Special output Output port R02 R03 Special output FOUT or BZ output BZ output The signal frequencies can also be selected by mask option. 18 EPSON S1C60N06 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports) 4.5.3 Special output Data bus Figure 4.5.3.1 shows the structure of output ports R00-R03. As shown in the previous section, the R02 terminal and the R03 terminal can be used as special output ports by selecting mask option. Register R00 R00 Register R01 R01 BZ Register R02 R02 FOUT BZ R03 Register R03 Address 0FCH Mask option Fig. 4.5.3.1 Structure of output port R00-R03 FOUT (R02) When the output port R02 is set as the FOUT output port, the R02 will output the clock generated from the OSC1 oscillation clock (fOSC1). The clock frequency can be selected from among 8 types by mask option Table 4.5.3.1 FOUT clock frequency No. Dividing ratio Frequency * 1 fOSC1 32768 Hz 2 fOSC1/2 16384 Hz 3 fOSC1/4 8192 Hz 4 fOSC1/8 4096 Hz 5 fOSC1/16 2048 Hz 6 fOSC1/32 1024 Hz 7 fOSC1/64 512 Hz 8 fOSC1/128 256 Hz When fOSC1 = 32.768 kHz When "1" is written to the FOUT (R02) register, the FOUT (R02) terminal outputs the clock with the selected frequency. When "0" is written, the FOUT (R02) terminal goes low. Figure 4.5.3.2 shows the output waveform of the FOUT output. R02 register 0 1 0 FOUT output waveform Fig. 4.5.3.2 FOUT output waveform Note: A hazard may occur when the FOUT signal is turned on or off. S1C60N06 TECHNICAL MANUAL EPSON 19 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports) BZ, BZ (R03, R02) The output ports R03 and R02 can be set to BZ output port and BZ output (BZ reverse output) port, respectively. However, when FOUT output is selected for the R02 terminal, BZ output cannot be selected. Direct driving of piezo-electric buzzer By setting the R03 to the BZ output port and the R02 to the BZ output port, these two terminals can directly drive a piezo-electric buzzer. The BZ output (R02) can only be set if the R03 is set to the BZ output. At initial reset, the output terminals go low. When "1" is written to the BZ (R03)/BZ (R02) registers, the output terminals output the buzzer signals. When "0" is written, the terminals go low. Figure 4.5.3.3 shows the buzzer direct drive waveform. R03/R02 register 0 1 0 BZ output waveform BZ output waveform Fig. 4.5.3.3 Buzzer output waveform (direct driving) Single terminal driving of piezo-electric buzzer The piezo-electric buzzer can be driven with one terminal by setting the R03 to the BZ output terminal. At initial reset, the BZ output goes off and the output terminal (R03) is set to low level. When "1" is written to the BZ (R03) register, the output terminal output the BZ signal. Figure 4.5.3.4 shows the BZ output waveform in single terminal driving. R03 register 0 1 0 BZ output waveform Fig. 4.5.3.4 Buzzer output waveform (single terminal driving) Busser signal frequency The buzzer signal frequency can be selected from 2 types (fOSC1/8, fOSC1/16) by the mask option. When the OSC1 oscillation frequency is 32.768 kHz, they becomes 4 kHz and 2 kHz, respectively. 20 EPSON S1C60N06 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports) 4.5.4 I/O memory of output ports Table 4.5.4.1 shows the I/O address and the control bits for the output port. Table 4.5.4.1 Control bits of output port Address Register D3 D2 D1 D0 R03 BZ R02 BZ FOUT R01 R00 0FCH R/W 1 Initial value at initial reset 2 Not set in the circuit Comment 1 0 Name Init 1 0 R03 High Low R03 output port data 0 BZ On Low Signal on/off when BZ is selected. (mask option) 0 R02 High Low R02 output port data BZ/FOUT 0 On Low Signal on/off when BZ/FOUT is selected. (mask option) R01 0 High Low R01 output port data R00 0 High Low R00 output port data 3 Always "0" being read 5 Undefined 4 Reset (0) immediately after being read R00-R03: Output port data (0FCH) Sets the output data for the output ports. When "1" is written: High output When "0" is written: Low output Reading: Valid The output port terminals output the data written to the corresponding registers (R00-R03) without changing it. When "1" is written to the register, the output port terminal goes high (VDD), and when "0" is written, the output port terminal goes low (VSS). At initial reset, these registers are all set to "0". R02 (when FOUT is selected): Special output control (0FCH*D2) Controls the FOUT (clock) output. When "1" is written: Clock output When "0" is written: Low level (DC) output Reading: Valid When "1" is written to the FOUT (R02) register, the FOUT (R02) terminal outputs the FOUT signal. When "0" is written, the terminal goes low. At initial reset, this register is set to "0". R02, R03 (when buzzer output is selected): Special output port data (0FCH*D2, D3) Controls the buzzer output. When "1" is written: Buzzer output When "0" is written: Low level (DC) output Reading: Valid The BZ and BZ outputs can be controlled by writing data to the R02 and R03 registers. At initial reset, these registers are set to "0". 4.5.5 Programming note The FOUT and buzzer output signals may produce hazards when the output ports R02 and R03 are turned on or off. S1C60N06 TECHNICAL MANUAL EPSON 21 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports) 4.6 I/O Ports (P00-P03) 4.6.1 Configuration of I/O port The S1C60N06 has 4 bits of general-purpose I/O ports. Figure 4.6.1.1 shows the configuration of the I/O ports. The I/O ports P00-P03 can be set to either input mode or output mode by writing data to the I/O control register (IOC). VDD Data bus Input control Data register Address P0x I/O control register Address Fig. 4.6.1.1 Configuration of I/O port 4.6.2 I/O control register and I/O mode Input or output mode can be set for the I/O ports P00-P03 by writing data to the I/O control register IOC. To set the input mode, write "0" to the I/O control register (IOC). When the I/O ports are set to the input mode, the terminals become high impedance and they work as input ports. The input line is pulled up during read operation. The output mode is set when "1" is written to the I/O control register (IOC). When the I/O ports are set to the output mode, they work as output ports and output a high signal (VDD) when the port output data is "1", and a low signal (VSS) when the port output data is "0". If perform the read out in each mode; when output mode, the register value is read out, and when input mode, the port value is read out. At initial reset, the I/O control register is set to "0", and the I/O ports enter the input mode. 4.6.3 I/O memory of I/O port Table 4.6.3.1 shows the I/O addresses and the control bits for the I/O port. Table 4.6.3.1 Control bits of I/O port Address Register D3 D2 D1 D0 P03 P02 P01 P00 IOC 0 R/W R 0FEH R/W 0 0 0FFH R 1 Initial value at initial reset 2 Not set in the circuit 22 Name P03 P02 P01 P00 0 3 0 3 IOC 0 3 Init 1 1 0 - 2 High Low - 2 High Low P0 I/O port data - 2 High Low - 2 High Low - 2 - Unused - - 2 - Unused - 0 Output Input I/O port I/O control - 2 - Unused - 3 Always "0" being read 4 Reset (0) immediately after being read EPSON Comment 5 Undefined S1C60N06 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports) P00-P03: I/O port data register (0FEH) I/O port data can be read and output data can be written through this register. * Writing When "1" is written: High level When "0" is written: Low level When the I/O port is set to the output mode, the written data is output from the I/O port terminal unchanged. When "1" is written as the port data, the port terminal goes high (VDD), and when "0" is written, the level goes low (VSS). Port data can also be written in the input mode. * Reading When "1" is read: High level When "0" is read: Low level The terminal voltage level of the I/O port is read. When the I/O port is in the input mode the voltage level being input to the port terminal can be read; in the output mode the output voltage level can be read. When the terminal voltage is high (VDD) the port data read is "1", and when the terminal voltage is low (VSS) the data is "0". When the port data is read, the built-in pull-up resistors go on and the I/O port terminals are pulled up. IOC: I/O control register (0FFH*D1) The input or output mode can be set with this register. When "1" is written: Output mode When "0" is written: Input mode Reading: Valid When "1" is written to the I/O control register, the I/O ports enter the output mode, and when "0" is written, the I/O ports enter the input mode. At initial reset, this register is set to "0". 4.6.4 Programming notes (1) When the I/O port is set to the output mode and a low-impedance load is connected to the port terminal, the data written to the register may differ from the data read. (2) When the I/O port is set to the input mode and the input level changed from low (VSS) to high (VDD) through the built-in pull-up resistor, an erroneous input results if the time constant of the capacitive load of the input line and the built-in pull-up resistor is greater than the read-out time. When the input data is being read, the time that the input line is pulled up is equivalent to 0.5 cycles of the CPU system clock. Hence, the electric potential of the terminals must settle within 0.5 cycles. If this condition cannot be met, some measure must be devised, such as arranging a pull-up resistor externally, or performing multiple read-outs. S1C60N06 TECHNICAL MANUAL EPSON 23 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) 4.7 LCD Driver 4.7.1 Configuration of LCD driver The S1C60N06 has four common terminals (COM0-COM3) and 20 segment terminals (SEG0-SEG19), so that an LCD with a maximum of 80 (20 x 4) segments can be driven. The driving method is 1/4 duty (1/3 duty can also be selected by mask option) dynamic drive, adopting the four types of potential, VDD, VL1, VL2 and VL3. The power for driving the LCD is generated by the internal circuit so that there is no need to apply power especially from outside. The frame frequency is 32 Hz for 1/4 duty and 42.7 Hz for 1/3 duty (in the case of fOSC1 = 32.768 kHz). Figures 4.7.1.1 and 4.7.1.2 show the drive waveform for 1/3 duty and 1/4 duty. Table 4.7.1.1 LCD drive mode options Duty COM used 1/4 COM0-COM3 1/3 COM0-COM2 Max. number of segments Frame frequency * 80 (20 x 4) 32 Hz 60 (20 x 3) 42.7 Hz When fOSC1 = 32 kHz VDD VL1 VL2 VL3 COM0 COM1 LCD status COM0 COM1 COM2 SEG0-19 COM2 COM3 VDD VL1 VL2 VL3 Off On SEG0 -SEG19 Frame frequency Fig. 4.7.1.1 Drive waveform for 1/3 duty 24 EPSON S1C60N06 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) VDD VL1 VL2 VL3 COM0 COM1 LCD status COM0 COM1 COM2 COM3 COM2 SEG0-19 COM3 Off On VDD VL1 VL2 VL3 SEG0 -SEG19 Frame frequency Fig. 4.7.1.2 Drive waveform for 1/4 duty S1C60N06 TECHNICAL MANUAL EPSON 25 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) 4.7.2 Mask option (1) Segment allocation The segment data is decided by the display data written to the display memory at address "0D0H- 0EFH". Writing "1" to the display memory turns the associated LCD segment on, and writing "0" turns the LCD segment off. The addresses and bits of the display memory can be made to correspond to the segment terminals (SEG0-SEG19) in any combination by mask option. This simplifies design by increasing the degree of freedom with which the liquid crystal panel can be designed. Figure 4.7.2.1 shows an example of the relationship between the LCD segments (on the panel) and the display memory in the case of 1/3 duty. Common 0 Common 1 Common 2 EC, D0 ED, D1 ED, D0 (a) (f) (e) SEG11 EC, D1 ED, D2 EC, D3 (b) (g) (d) SEG12 EF, D1 EC, D2 ED, D3 (f') (c) (p) Data Address D3 D2 D1 D0 0ECH d c b a 0EDH p g f e 0EEH d' c' b' a' 0EFH p' g' f' e' SEG10 Display memory allocation Pin address allocation a a' b f e g' c c' e' p d SEG10 b' f' g SEG11 p' d' SEG12 Common 0 Common 1 Common 2 Fig. 4.7.2.1 Segment allocation (2) Drive duty Either 1/4 or 1/3 duty can be selected as the LCD drive duty. 4.7.3 Programming note Because the display memory is for writing only, re-writing the contents with logical instructions (e.g., AND, OR, etc.) which come with read-out operations is not possible. To perform bit operations, a buffer to hold the display data is required on the RAM. 26 EPSON S1C60N06 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer) 4.8 Clock Timer 4.8.1 Configuration of clock timer The S1C60N06 has a built-in clock timer that uses the OSC1 oscillation circuit as the clock source. The clock timer is configured as a 8-bit binary counter that counts with a 256 Hz source clock from the divider. The 8 bits of the counter (128 Hz-1 Hz) can be read by the software in 4-bit units. Figure 4.8.1.1 is the block diagram of the clock timer. Data bus Oscillation circuit 256 Hz 128 Hz-16 Hz 8 Hz-1 Hz 32 Hz, 8 Hz, 2 Hz Clock timer control signal Interrupt control Interrupt request Fig. 4.8.1.1 Block diagram of clock timer Normally, this clock timer is used for all kinds of timing purpose, such as clocks. Note: The information given in this section is based on fOSC1 = 32.768 kHz. For a system which uses an oscillator having any other frequency at OSC1, substitute the appropriate value for 32.768 kHz throughout this section. 4.8.2 Interrupt function The clock timer can generate interrupts at the falling edge of the 32 Hz, 8 Hz, and 2 Hz signals. The software can mask any of these interrupt signals. Figure 4.8.2.1 is the timing chart of the clock timer. Address Bit Frequency D0 128 Hz D1 64 Hz D2 32 Hz D3 16 Hz D0 8 Hz D1 4 Hz D2 2 Hz D3 1 Hz Clock timer timing chart 0F4H 0F5H 32 Hz interrupt request 8 Hz interrupt request 2 Hz interrupt request Fig. 4.8.2.1 Timing chart of the clock timer As shown in Figure 4.8.2.1, an interrupt is generated at the falling edge of the 32 Hz, 8 Hz, and 2 Hz signals. At this point, the corresponding interrupt factor flag (IT32, IT8, IT2) is set to "1". The interrupts can be masked individually with the interrupt mask register (EIT32, EIT8, EIT2). However, regardless of the interrupt mask register setting, the interrupt factor flags will be set to "1" at the falling edge of their corresponding signal (e.g. the falling edge of the 2 Hz signal sets the 2 Hz interrupt factor flag to "1"). S1C60N06 TECHNICAL MANUAL EPSON 27 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer) 4.8.3 I/O memory of clock timer Table 4.8.3.1 shows the I/O addresses and the control bits for the clock timer. Table 4.8.3.1 Control bits of clock timer Address Register D3 D2 D1 WDRST IT2 IT8 0F1H W TMRUN R EIT2 EIT8 0F3H R/W TM03 TM02 TM01 0F4H R TM13 TM12 TM11 0F5H R 1 Initial value at initial reset 2 Not set in the circuit Comment 1 0 Name Init 1 WDRST Reset Reset Watchdog timer reset - IT32 IT2 4 0 Interrupt factor flag (clock timer 2 Hz) Yes No IT8 4 0 Interrupt factor flag (clock timer 8 Hz) Yes No IT32 4 0 Interrupt factor flag (clock timer 32 Hz) Yes No TMRUN 0 Run Reset,Stop Timer run/reset & stop EIT32 EIT2 0 Enable Mask Interrupt mask register (clock timer 2 Hz) EIT8 0 Enable Mask Interrupt mask register (clock timer 8 Hz) EIT32 0 Enable Mask Interrupt mask register (clock timer 32 Hz) TM03 Timer data (16 Hz) 0 TM00 TM02 Timer data (32 Hz) 0 TM01 Timer data (64 Hz) 0 TM00 Timer data (128 Hz) 0 TM13 Timer data (1 Hz) 0 TM10 TM12 Timer data (2 Hz) 0 TM11 Timer data (4 Hz) 0 TM10 Timer data (8 Hz) 0 3 Always "0" being read 5 Undefined 4 Reset (0) immediately after being read D0 TM00-TM03: Timer low-order data (0F4H) TM10-TM13: Timer high-order data (0F5H) The l28 Hz to 16 Hz timer data of the clock timer can be read from the TM00-TM03 register and 8 Hz to 1 Hz data can be read from the TM10-TM13 register. These eight bits are read-only, and write operations are invalid. At initial reset, the timer data is initialized to "00H". TMRUN: Clock timer control (0F3H*D3) Starts, stops and resets the clock timer. When "1" is written: Run When "0" is written: Reset and stop Reading: Valid The clock timer starts counting by writing "1" to the TMRUN register. When "0" is written, the clock timer clears the count data and stops counting. At initial reset, this register is set to "0". EIT32, EIT8, EIT2: Interrupt mask registers (0F3H*D0-D2) These registers are used to mask the clock timer interrupt. When "1" is written: Enabled When "0" is written: Masked Reading: Valid The interrupt mask registers (EIT32, EIT8, EIT2) mask the corresponding interrupt frequencies (32 Hz, 8 Hz, 2 Hz). At initial reset, these registers are all set to "0". 28 EPSON S1C60N06 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer) IT32, IT8, IT2: Interrupt factor flags (0F1H*D0-D2) These flags indicate the status of the clock timer interrupt. When "1" is read: Interrupt has occurred When "0" is read: Interrupt has not occurred Writing: Invalid The interrupt factor flags (IT32, IT8, IT2) correspond to the clock timer interrupts (32 Hz, 8 Hz, 2 Hz). The software can determine from these flags whether there is a clock timer interrupt. However, even if the interrupt is masked, the flags are set to "1" at the falling edge of the signal. These flags can be reset when the register is read by the software. Reading of interrupt factor flags is available at EI, but be careful in the following cases. If the interrupt mask register value corresponding to the interrupt factor flag to be read is set to "1", an interrupt request will be generated by the interrupt factor flag set timing, or an interrupt request will not be generated. Be very careful when interrupt factor flags are in the same address. At initial reset, these flags are set to "0". 4.8.4 Programming notes (1) Note that the frequencies and times differ from the description in this section when the oscillation frequency is not 32.768 kHz. (2) Reading of interrupt factor flags is available at EI, but be careful in the following cases. If the interrupt mask register value corresponding to the interrupt factor flag to be read is set to "1", an interrupt request will be generated by the interrupt factor flag set timing, or an interrupt request will not be generated. Be very careful when interrupt factor flags are in the same address. S1C60N06 TECHNICAL MANUAL EPSON 29 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Remote Controller) 4.9 Remote Controller (REM) 4.9.1 Configuration of remote controller The S1C60N06 has a remote controller (REM circuit) built-in. It can easily adapt to various remote controllers by connecting an infrared remote LED and a transistor as shown in Figure 4.9.1.1. VDD S1C60N06 REM circuit REM (R33) VSS Fig. 4.9.1.1 Remote LED control circuit Figure 4.9.1.2 shows the configuration of the REM circuit. Carrier REMSO MPX RCDIV RCDUTY fOSC3 OSC3 oscillation circuit RT1, RT0 REM (R33) ROUT1, ROUT0 Carrier (Reference cycle) generation Carrier generation circuit waveform circuit REMC REMOUT time generator REMOUT RIC3-RIC0 Interrupt counter Interrupt control circuit Interrupt request Fig. 4.9.1.2 Configuration of REM circuit The generally used infrared remote controllers employ a method that generates transmission waveforms in pulse modulation as shown in Figure 4.9.1.3 and transmits the signal. First the transmission code is modulated in a pulse phase modulation (PPM) method to generate the modulation signal, and the carrier that has constant frequency is amplitude-modulated (AM) using the modulation signal. As a result, transmission waveforms are generated. Transmission is done by driving the infrared LED using the transmission waveform. Transmission code 0101 0 1 0 1 PPM REM output Carrier AM Fig. 4.9.1.3 Remote transmission method In this remote controller, the carrier generated from the carrier generation circuit is controlled to turn the output ON and OFF and the transmission waveform is generated. This transmission waveform can be output from the REM (R33) terminal. At initial reset and while remote output stops, the REM terminal goes low level (VSS). The carrier frequency and duty ratio can be selected by the software from among 4 types. (details are explained later) 30 EPSON S1C60N06 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Remote Controller) This remote controller supports the following two modes for controlling the modulation signal (carrier ON/OFF). * Soft-timer mode (Software timer control mode) * Hard-timer mode (Hardware timer control mode) In the soft-timer mode, the carrier ON/OFF timing and the time are controlled by the software. The optional ON/OFF time can be set within the range that is controlled by the software. In the hard-timer mode, the carrier ON/OFF timing and the output time are controlled by the REMOUT time generator based on the reference cycle () that is generated by the (reference cycle) generation circuit dividing the carrier. For the reference cycle (), the carrier dividing ratio can be selected by the software from 4 types. The REMOUT (REM output) time can be selected by the software from 4 types, 0 to 3 times as long as the reference cycle (). The ON/OFF time is limited to some extent in comparison with the soft-timer mode, but the software's share is decreased because the interrupt can be used. Features of the soft-timer mode and hard-timer mode are shown in Table 4.9.1.1. Table 4.9.1.1 Features of soft-timer mode and hard-timer mode Item Processing of other routines during REM output Reference cycle () sway during REM transmission Setting of REM output width Relation between REM reference cycle and modulation frequency cycle Carrier waveform Soft-timer mode Difficult Source oscillation sway and errors caused by instruction cycles Variable to any width Variable Hard-timer mode Possible Source oscillation sway only Duty slightly disturbed before and after ON time Stabilized at setting Fixed to several widths Fixed to several cycles 4.9.2 Carrier The carrier is generated by the carrier generation circuit using the OSC3 clock as the source clock. Note: If an option is selected without use of OSC3, the OSC1 clock (instead of the OSC3 clock) is introduced into the REM circuit. For an option selected without using OSC3, the term "OSC3" should read "OSC1" in the description that follows. The carrier cycle and duty ratio selections and the carrier generation circuit ON/OFF control can be done by the software. The control for the carrier is same procedure for both the soft-timer mode and the hard-timer mode. Perform the carrier settings before starting the transmission in each mode. The carrier cycle (selection as the dividing ratio of the OSC3 clock) and the duty ratio can be set using the RCDIV register (F7H*D3) and RCDUTY register (F7H*D2) as shown in Table 4.9.2.1. Table 4.9.2.1 Carrier dividing ratio and duty ratio RCDIV 0 0 1 1 RCDUTY Carrier dividing ratio 0 fOSC3 / 8 1 fOSC3 / 8 0 fOSC3 / 12 1 fOSC3 / 12 Carrier duty ratio 1/4 3/8 1/3 1/4 fOSC3: OSC3 oscillation frequency Carrier settings can be done even when the OSC3 oscillation circuit is in OFF status. Furthermore, when these are set once, the set contents are maintained until an initial reset is performed. Note: The setting of the RCDIV register and the RCDUTY register should be done when the REM circuit is OFF (REMC = "0") before starting remote transmission. If changing the contents when the REM circuit is ON, it may cause a malfunction. S1C60N06 TECHNICAL MANUAL EPSON 31 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Remote Controller) The carrier generation circuit is switched to ON/OFF by the REMC register. By writing "1" to the register, the carrier generation circuit goes ON and generates the carrier. When the register is set to "0" by writing, the carrier generation circuit goes OFF and the carrier generation stops. The OSC3 clock is divided to generate the carrier. Therefore, the OSC3 oscillation circuit must be ON before starting remote output. Remote output should be done when the OSC3 oscillation has stabilized. Note: It takes at least 5 msec from the time the OSC3 oscillation circuit goes ON until the oscillation stabilizes. Consequently, when starting a remote output, secure 5 msec or more waiting time for oscillation stabilization after turning the OSC3 oscillation ON. Further, the oscillation stabilization time varies depending on the external oscillator characteristics and conditions of use, so allow ample margin when setting the waiting time. Figure 4.9.2.1 shows the carrier waveform. OSC3 clock Carrier waveform 1/8 division 1/4 duty 1/8 division 3/8 duty 1/12 division 1/3 duty 1/12 division 1/4 duty Fig. 4.9.2.1 Carrier waveform The carrier generation circuit starts carrier output by writing "1" to the REMC register. When the REMC register is set to "0", the carrier output stops. Note: Except when outputting the remote control waveform, REMC register should be fixed at "0" to prevent outputting unnecessary waveforms and to reduce current consumption. However at initial reset, the REMC register is set to "1" for initializing the carrier generation circuit. The register must not be set to "0" until after initialization (within 32 machine cycles). 32 EPSON S1C60N06 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Remote Controller) 4.9.3 Soft-timer mode In the soft-timer mode, software controls the ON/OFF time and timing of the carrier output. This mode does not use the (reference cycle) generation circuit, REMOUT time generator and interrupt control circuit that are used in the hard-timer mode, and operates with the configuration as shown in Figure 4.9.3.1. RCDIV RCDUTY fOSC3 OSC3 oscillation circuit Carrier Carrier generation circuit REM (R33) REMC REMSO Fig. 4.9.3.1 REM circuit configuration in soft-timer mode The ON/OFF control of the carrier output is done using the REMSO register (F0H*D3). By writing "1" to the REMSO register, the carrier is output to the REM terminal and when "0" is written, the REM terminal goes low level (VSS). However, the carrier must be generated by writing "1" to the REMC register before writing "1" to the REMSO register. Figure 4.9.3.2 shows the timing chart in the soft-timer mode. REMC register Carrier REMSO register REM (R33) output Fig. 4.9.3.2 Timing chart (soft-timer mode) Note: * Writing to the REMSO register without synchronization with the carrier generation circuit, therefore when turning the carrier output ON/OFF using the REMSO register, the duty ratio of the carrier will not be the value set by the software. (Figure 4.9.3.3) REMSO register REM (R33) output Carrier duty ratio will be different from the value set by the software at the time the signal turns ON/OFF using the REMSO register. Fig. 4.9.3.3 Carrier ON/OFF by REMSO register * Be sure to control the carrier output using the REMSO register. Do not control the carrier output using the REMC register by setting the REMSO register to "1". S1C60N06 TECHNICAL MANUAL EPSON 33 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Remote Controller) 4.9.4 Hard-timer mode and REM interrupt In the soft-timer mode, the CPU is occupied for the remote output processing so that it has no flexibility for execution of other routines. To alleviate this problem, the S1C60N06 supports the hard-timer mode explained below. In the hard-timer mode, the carrier ON/OFF, that is controlled using the REMSO register in the soft-timer mode, is done in the hardware by using the (reference cycle) generation circuit and the REMOUT time generator. (reference cycle) is generated from the carrier by dividing, and is used for reference of the carrier ON/OFF time in the hard-timer mode. The dividing ratio of (reference cycle) is selected from 4 types by the software. The carrier ON/OFF time can be set for each transmission data bit by the software using (reference cycle) as reference. Furthermore, the interrupt function is provided so that the setting can be done without synchronizing with the timing of the carrier output. The interrupt timing can also be set by the software using (reference cycle) as the reference same as the ON/OFF time. The circuit in the hard-timer mode is configured as shown in Figure 4.9.1.2, and all the REM circuit is used. However, the REMSO register that is used to control the carrier output in the soft-timer mode should be fixed at "0". If "1" is written to the REMSO register, REM output are forcibly done regardless of the control of the hard-timer mode. (1) (reference cycle) (reference cycle) is used as reference for the carrier output ON time and interrupt timing specified by the software, and is generated by the (reference cycle) generation circuit by dividing carrier. This dividing ratio can be selected using the RT1-RT0 register (F7H*D1, D0) from 4 types as shown in Table 4.9.4.1. Table 4.9.4.1 (reference cycle) setting RT1 0 0 1 1 dividing ratio fcarrier / 12 fcarrier / 16 fcarrier / 20 fcarrier / 32 RT0 0 1 0 1 * fcarrier indicates carrier frequency. It is selected with the RCDIV register (F7H*D3). The actual time of (reference cycle) can be found using the following expression according to the OSC3 oscillation frequency, carrier cycle selection and the above selection. (reference cycle) [sec] = 1 / (fOSC3 x DIV1 x DIV2) fOSC3: OSC3 oscillation frequency DIV1: Content of carrier dividing ratio set with the RCDIV register (1/8 or 1/12) DIV2: Content of dividing ratio set with the RT1 and RT0 registers (1/12, 1/16, 1/20 or 1/32) Table 4.9.4.2 shows the examples of (reference cycle) when fOSC3 is 455 kHz. Table 4.9.4.2 (reference cycle) examples Register settings RCDIV RT0 RT1 0 0 0 0 0 0 1 1 1 1 0 1 1 0 0 1 1 (reference cycle) fOSC3 = 455 kHz 0.211 msec (4739.6 Hz) 1 0 1 0.281 msec (3554.7 Hz) 0.352 msec (2843.8 Hz) 0.563 msec (1777.3 Hz) 0 1 0.316 msec (3159.7 Hz) 0.422 msec (2369.8 Hz) 0 1 0.527 msec (1895.8 Hz) 0.844 msec (1184.9 Hz) The carrier output ON time can be set to 4 types (0 to 3) based on the (reference cycle) set, so set the (reference cycle) after due consideration. 34 EPSON S1C60N06 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Remote Controller) Figure 4.9.4.1 shows the waveform when fcarrier /12 has been selected. waveform is kept on outputting from the (reference cycle) generation circuit according to the set dividing ratio while the REMC register is "1". Carrier waveform Fig. 4.9.4.1 waveform (when fcarrier /12 is selected) It is possible to set (reference cycle) even if the OSC3 oscillation circuit is in OFF status. Furthermore, when it is set once, the set contents are maintained until an initial reset is performed. When the REMC is set to "0", the REM circuit stops synchronously with . This timing is shown in Figure 4.9.4.2. REMC Carrier waveform Stop synchronously with Fig. 4.9.4.2 REM circuit stop timing Maximum of 384 machine cycles* are required until the REM circuit stops after the REMC is set to "0". Even if the CPU clock is changed from OSC3 to OSC1 after the REMC = "0", OSC3 must not be turned OFF before the REM circuit stops. This time depends on the value of the set cycle. If a shorter cycle is set, the maximum time required for the REM circuit to stop after REMC = "0" is shortened. If the REM circuit is restarted from OFF state with REMC = "0", the timing of the waveform rises one carrier before the set division ratio. REMC Carrier waveform Fig. 4.9.4.3 generation circuit restart timing Note: The setting of the RT register should be done when the REM circuit is OFF (REMC = "0") before starting remote transmission. Changing the contents when the REM circuit is ON may cause a malfunction. S1C60N06 TECHNICAL MANUAL EPSON 35 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Remote Controller) (2) Setting of carrier output width In the soft-timer mode, the carrier output width (carrier output ON time) is controlled by writing to the REMSO register, but in the hard-timer mode, it can be specified with values 0 to 3, which mean the number of cycles described above, in each transmission data bit. Since the carrier output ON/OFF is controlled by the hardware in synchronizing with waveform, it is unnecessary to watch the ON time and to specify the OFF timing by the software. The carrier output width can be selected by writing data to the ROUT1-ROUT0 register (F9H*D3, D2) from among 4 types as shown in Table 4.9.4.3. Table 4.9.4.3 Setting of carrier output width ROUT1 ROUT0 Carrier output width 0 0 0 0 1 1 0 1 2 1 1 3 The carrier is output in synchronizing with the rising edge of the waveform after writing data to ROUT register. Data written to the ROUT register is maintained while the REM circuit is ON until the next data is written. The carrier output starts using the write signal for this register and the carrier output will be ON from the rising edge of the waveform immediately after that until the period set in the register has passed. In other words, the register data is valid only one time after writing. Consequently, data must be written every time even when outputting the same data successively. The ROUT register is set to "0H" at initial reset and when the REMC register is set to "0". Consequently, after turning the REM circuit ON ("1" is written to the REMC register), REM output becomes low level (VSS) until a value other than "0H" is written to the ROUT register. Figure 4.9.4.4 shows the timing of data writing to the ROUT register and the carrier output. Register writing ROUT1-0 2 0 2 1 waveform REMOUT REM terminal Fig. 4.9.4.4 Carrier output timing Note: The values set in the ROUT register is taken into the REMOUT time generator synchronously with the rise of a waveform. For this reason, avoid writing data into the ROUT register during one carrier cycle immediately before and after the rise of the waveform. (3) Remote controller (REM) interrupt The carrier output ON time for one transmission data bit is controlled by writing data to the above mentioned ROUT register. The OFF time is from when the output is turned OFF to when the next carrier output starts by writing to the same register. Since the carrier output is turned ON at the rising edge of the waveform after writing data, the next data must be written during the last cycle in the carrier OFF period of the current transmission data. To decide its timing, an interrupt is used in the hard-timer mode. By using the interrupt, the CPU is released from the processing such as a timing watch, and can execute other processing. The timing to generate interrupt can be set by the software using cycle as reference the same as the carrier output width. The interrupt timing can be selected by writing data to the RIC3-RIC0 register (F8H). 36 EPSON S1C60N06 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Remote Controller) The time until an interrupt request occurs (tRI) is given by: tRI = tRIC + (1 1 instruction cycle) Where tRIC is the time set by the RIC register. The relation between the RIC register and tRIC is: tRIC = (RIC3 x 23 + RIC2 x 22 + RIC1 x 2 + RIC0) x As with the REMOUT time generator, the REM interrupt counter starts counting synchronously with the rising edge of the waveform. The interrupt control circuit generates a REM interrupt synchronously with the pulse when the count is completed. ROUT register writing RIC register writing ROUT1-0 1 1 RIC3-0 1 2 Carrier waveform REM output Interrupt signal Interrupt request Fig. 4.9.4.5 REM interrupt timing The waveform is counted at every rising edge. When the count becomes the number set in the RIC register, the interrupt factor flag IREM (F0H*D2) is set to "1" and an interrupt occurs in synchronization with that riging edge. Set the next carrier output width and the interrupt timing using this interrupt. The REM interrupt can be masked through the interrupt mask register EIREM (F2H*D2). However, regardless of the setting of the interrupt mask register, the interrupt factor flag IREM is set to "1" when the counting of the interrupt cycles are completed. The interrupt factor flag is reset to "0" by the reading. Data written to the RIC register is maintained while the REM circuit is ON until the next data is written. However, the counting of waveform starts using the write signal for the RIC register the same as the ROUT register, so this register data is valid only one time after writing. Consequently, data must be written every time even when generating the next interrupt in the same cycle count. The RIC register is undefined at initial reset. However, the counting of cycles is not performed until the RIC register is written after that. Note: * Once data has been written in the RIC register, avoid writing other data into the register before a REM interrupt occurs (which would otherwise cause an invalid interrupt). * The values allowed for the RIC register are 0 to 0EH. * Reading of the interrupt factor flag is available at EI, but be careful in the following cases. If the interrupt mask register value corresponding to the interrupt factor flag to be read is set to "1", an interrupt request will be generated by the interrupt factor flag set timing, or an interrupt request will not be generated. S1C60N06 TECHNICAL MANUAL EPSON 37 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Remote Controller) 4.9.5 I/O memory of remote controller Table 4.9.5.1 shows the I/O addresses and the control bits for the remote controller. Table 4.9.5.1 Control bits of remote controller Address Register D3 D2 D1 REMSO IREM IK1 0F0H R/W REMC R EIREM EIK1 0F2H R/W RCDIV RCDUTY RT1 0F7H R/W RIC3 RIC2 RIC1 0F8H W ROUT1 ROUT0 MF91 0F9H R/W 1 Initial value at initial reset 2 Not set in the circuit Comment Name Init 1 1 0 REMSO 0 Forced REM output (on/off) On Off IK0 IREM 4 - 5 Interrupt factor flag (REM) Yes No IK1 4 0 Interrupt factor flag (K10-K13) Yes No IK0 4 0 Interrupt factor flag (K00-K03) Yes No REMC REM carrier generation on/off 1 On Off EIK0 EIREM 0 Enable Mask Interrupt mask register (REM) EIK1 0 Enable Mask Interrupt mask register (K10-K13) EIK0 0 Enable Mask Interrupt mask register (K00-K03) D3 RCDIV REM carrier interval - 5 RT0 0 - 5 RCDUTY and duty ratio setting 0 - 5 RT1 cycle (division ratio) setting 1 1 - 5 RT0 0: 1/12, 1: 1/16, 2: 1/20, 3: 1/32 RIC3 - 5 RIC0 - 5 RIC2 REM interrupt counter (0 to 14) - 5 RIC1 5 - RIC0 ROUT1 0 MF90 REM output duration setting (0 to 3) ROUT0 0 5 MF91 General-purpose register - - 5 MF90 General-purpose register 3 Always "0" being read 5 Undefined 4 Reset (0) immediately after being read D0 D2 Div. ratio 1/8 0 1/8 1 1/12 0 1/12 1 Duty 1/4 3/8 1/3 1/4 REMC: REM carrier generation control (0F2H*D3) Turns the carrier generation on and off. When "1" is written: On When "0" is written: Off Reading: Valid When "1" is written to the REMC register, the carrier generation circuit turns ON. Writing "0" turns the carrier generation circuit OFF. At initial reset, this register is set to "1". REMSO: Soft-timer output control (0F0H*D3) Controls the carrier output in the soft-timer mode. When "1" is written: Carrier output ON When "0" is written: Carrier output OFF Reading: Valid By writing "1" to the REMSO register when the REMC registre has been set to "1", carrier is output from the REM (R33) terminal. When "0" is written, the REM (R33) terminal goes to low level (VSS). At initial reset, this register is set to "0". Note: The REMSO register is for the exclusive use of the soft-timer mode. When controlling with the hard-timer mode, the REMSO register should be fixed at "0". RCDIV: Carrier cycle selection (0F7H*D3) Selects the carrier cycle. When "1" is written: fOSC3/12 When "0" is written: fOSC3/8 Reading: Valid When "1" is written to the RCDIV register, the carrier frequency is set to fOSC3/12. When "0" is written, it is set to fOSC3/8. This setting must be done when the remote controller is OFF (REMC = "0") status. At initial reset, this register is undefined. 38 EPSON S1C60N06 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Remote Controller) RCDUTY: Carrier duty ratio selection (0F7H*D2) Selects the duty ratio of the carrier. Duty ratio set by RCDUTY varies according to the carrier cycle set by RCDIV as the follows: Table 4.9.5.2 Selection of carrier duty ratio RCDIV 0 0 1 1 RCDUTY Carrier dividing ratio 0 fOSC3 / 8 1 fOSC3 / 8 0 fOSC3 / 12 1 fOSC3 / 12 Carrier duty ratio 1/4 3/8 1/3 1/4 fOSC3: OSC3 oscillation frequency This setting must be done when the remote controller is OFF (REMC = "0") status. At initial reset, this register is undefined. RT1, RT0: cycle selection (0F7H*D1, D0) Selects the (reference cycle). When controlling in the hard-timer mode, select the (reference cycle) that is used as a reference for the timing generation. Table 4.9.5.3 (reference cycle) setting RT1 0 0 1 1 dividing ratio fcarrier / 12 fcarrier / 16 fcarrier / 20 fcarrier / 32 RT0 0 1 0 1 * fcarrier indicates carrier frequency. It is selected by RCDIV (F7H*D3). This setting must be done when the remote controller is in OFF (REMC = "0") status. At initial reset, this register is undefined. ROUT1, ROUT0: Carrier output width selection (0F9H*D3, D2) When controlling in the hard-timer mode, select the carrier output width. Table 4.9.5.4 Setting of carrier output width ROUT1 0 0 1 1 ROUT0 0 1 0 1 Carrier output width 0 1 2 3 By writing data to this register, the carrier for set cycles is output from the REM (R33) terminal in synchronization with the rising edge of the waveform immediately after that. The setting (writing) of carrier output width must be done at every bit of the transmission data. At initial reset and when the REMC register is set to "0", this register is set to "0". Note: The ROUT register is for the exclusive use of the hard-timer mode. When controlling with the softtimer mode, be sure not to write data to this register to prevent malfunction. RIC3-RIC0: Interrupt cycle selection (0F8H) The cycle count for generating a REM interrupt is set to this register. By writing data to this register when the REM circuit has been ON (REMC = "1"), the counting of waveform is started by synchronizing with the rising edge of the waveform immediately after that. When the count becomes the number set in this register, an interrupt occurs. Set the next transmission data and interrupt timing using this interrupt. Do not set "0FH" in this register. The setting (writing) of interrupt cycle must be done at every bit of the transmission data. At initial reset, this register is undefined. Note: The RIC register is for the exclusive use of the hard-timer mode. When controlling with the softtimer mode, be sure not to write data to this register to prevent malfunction. S1C60N06 TECHNICAL MANUAL EPSON 39 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Remote Controller) EIREM: Interrupt mask register (0F2H*D2) This register is used to select whether to mask the remote controller interrupt. When "1" is written: Enabled When "0" is written: Masked Reading: Valid When "1" is written to EIREM, the remote controller interrupt is enabled. When "0" is written, it is masked. At initial reset, this register is set to "0". IREM: Interrupt factor flag (0F0H*D2) This is the interrupt factor flag of the remote controller. When "1" is read: Interrupt has occurred When "0" is read: Interrupt has not occurred Writing: Invalid This flag is set to "1" when the interrupt cycle set with the RIC register has passed (counting of the waveform has completed). From the status of this flag, the software can decide the remote controller interrupt. Note, however, that even if the interrupt is masked, this flag will be set to "1" when the counting of the interrupt cycle is completed. This flag is reset when read out by the software. Reading of the interrupt factor flag is available at EI, but be careful in the following cases. If the interrupt mask register value corresponding to the interrupt factor flag to be read is set to "1", an interrupt request will be generated by the interrupt factor flag set timing, or an interrupt request will not be generated. At initial reset, this flag is set to "0". 40 EPSON S1C60N06 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Remote Controller) 4.9.6 Programming notes (1) The following programming steps are needed to initialize the REM circuit ( clock, REM interrupt circuit): * Write data at addresses 0F7H and 0F8H in that order within 80 machine clocks (equivalent to eleven 7-clock instructions) after release from initial reset. * With REMC = "0" (0F2H*D3), the REM circuit must not be stopped within cycle of 1 after data has been written at address 0F8H. * To initialize the REM interrupt circuit, read the REM interrupt factor flag (address 0F0H) to clear it at least an interval of 2 after data has been written at address 0F8H. (2) After initial reset, the REMC register stays at "1" to initialize the carrier generation circuit. The REMC register can only be reset to "0" after initialization (at least 32 machine cycles later). (3) The REM circuit does not stop immediately after the REMC register is reset to "0". It stops synchronously with the interval , during which OSC3 must be held ON. (4) With the REM circuit in operation, do not write data at addresses 0F8H and 0F9H (REM interrupt counter and REMOUT time setting register) during an interval of one carrier before and after the rise of . (5) With the REM circuit in operation, do not write data at addresses 0F7H (-setting register). (6) During the operation under hard-timer mode, the REMSO register must be fixed at "0". (7) Reading of interrupt factor flag is available at EI, but be careful in the following cases. If the interrupt mask register value corresponding to the interrupt factor flag to be read is set to "1", an interrupt request will be generated by the interrupt factor flag set timing, or an interrupt request will not be generated. Be very careful when interrupt factor flags are in the same address. (8) If the RIC register is set again before a REM interrupt occurs with the RIC register set, an invalid interrupt may occur. (9) The values that can be set in the REM interrupt counter (0F8H) are from 0 to 0EH. Remember, writing 0FH into the counter may cause an error. (10) Soft-timer mode cannot coexist with hard-timer mode. To use them in combination, stop the REM circuit before selecting either. S1C60N06 TECHNICAL MANUAL EPSON 41 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT) 4.10 Interrupt and HALT The S1C60N06 has a total of six interrupt functions: two external input interrupts, three internal timer interrupts, and one remote control (REM) interrupt. Each of them can be masked. To enable an interrupt, the interrupt flag must be enabled (set to "1"). Upon occurrence of an interrupt, the flag is disabled (set to "0"). When an interrupt occurs, the address of the next program to execute is saved into the stack (RAM) and the program counter is set to the interrupt vector (page 1, steps 01H to 0FH) depending on the interrupt factor. (These processes require a time of 12 clocks.) All subsequent processing is controlled by the software written in the interrupt vector. Execution of the HALT instruction stops the CPU clock of the S1C60N06 to halt the CPU. An interrupt enables it to restart from the halt state. If the CPU can not restart, because dose not detect an interrupt, it restarts from initial reset state under watchdog timer control. Table 4.10.1 I/O memory map Address Register D3 D2 D1 REMSO IREM IK1 0F0H R/W WDRST R IT2 IT8 0F1H W REMC R EIREM EIK1 0F2H R/W TMRUN EIT2 EIT8 0F3H R/W 1 Initial value at initial reset 2 Not set in the circuit Comment Name Init 1 1 0 0 Forced REM output (on/off) REMSO On Off IK0 - 5 Interrupt factor flag (REM) IREM 4 Yes No IK1 4 0 Interrupt factor flag (K10-K13) Yes No IK0 4 0 Interrupt factor flag (K00-K03) Yes No WDRST Reset Reset Watchdog timer reset - IT32 IT2 4 0 Interrupt factor flag (clock timer 2 Hz) Yes No IT8 4 0 Interrupt factor flag (clock timer 8 Hz) Yes No IT32 4 0 Interrupt factor flag (clock timer 32 Hz) Yes No REMC REM carrier generation on/off 1 On Off EIK0 EIREM 0 Enable Mask Interrupt mask register (REM) EIK1 0 Enable Mask Interrupt mask register (K10-K13) EIK0 0 Enable Mask Interrupt mask register (K00-K03) TMRUN 0 Run Reset,Stop Timer run/reset & stop EIT32 EIT2 0 Enable Mask Interrupt mask register (clock timer 2 Hz) EIT8 0 Enable Mask Interrupt mask register (clock timer 8 Hz) EIT32 0 Enable Mask Interrupt mask register (clock timer 32 Hz) 3 Always "0" being read 5 Undefined 4 Reset (0) immediately after being read D0 4.10.1 Interrupt request An interrupt request is caused by one of the following factors: Table 4.10.1.1 Interrupt factor and interrupt factor flag Interrupt factor Falling edge of 2 Hz timer signal Falling edge of 8 Hz timer signal Falling edge of 32 Hz timer signal REM control Falling edge of input (K10-K13) Falling edge of input (K00-K03) Interrupt factor flag IT2 (0F1H*D2) IT8 (0F1H*D1) IT32 (0F1H*D0) IREM (0F0H*D2) IK1 (0F0H*D1) IK0 (0F0H*D0) An interrupt factor sets the corresponding interrupt factor flag (read-only register) to "1". When its data is read, the register is reset to "0". At initial reset, it is reset to "0". (However, the value of the REM interrupt factor flag (IREM) is undefined at initial reset.) When the interrupt factor flag is set to "1" with both the corresponding interrupt mask register and interrupt flag set at "1", an interrupt request to the CPU is generated. Reading of interrupt factor flags is available at EI, but be careful in the following cases. If the interrupt mask register value corresponding to the interrupt factor flag to be read is set to "1", an interrupt request will be generated by the interrupt factor flag set timing, or an interrupt request will not be generated. Be very careful when interrupt factor flags are in the same address. 42 EPSON S1C60N06 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT) * Timer Interrupt As described in section 4.8 "Clock Timer", the timer signal of 2 Hz, 8 Hz or 32 Hz can request a timer interrupt (when fOSC1 = 32.768 kHz). As the timer continues to operate even with the CPU in the halt state, the CPU can be restarted under timer control. Interrupt factor flag 2 Hz IT2 (Falling edge) 8 Hz IT8 (Falling edge) 32 Hz IT32 (Falling edge) fOSC1 (32.768 kHz) Timer TMRUN Fig. 4.10.1.1 Timer interrupt request circuit * REM Interrupt As described in section 4.9 "Remote Controller", a REM interrupt can be invoked during operation of the REM circuit or synchronously with a REM carrier. Note that the operation of the REM circuit is assured only with a CPU clock being supplied from OSC3. * Input Interrupt An input interrupt can be invoked by the IK1 group (K10-K13) or the IK0 group (K00-K03). As each pin contains an fOSC1/8 (4 kHz) clock noise reject circuit, the input must be held at low level for at least 16/fOSC1 (0.5 msec) to assure an input interrupt. For the K10-K13 group, the interrupt factor flag can be set with the noise reject circuit bypassed by using the mask option. In this case, the input must be held at low level for at least 5 machine clocks (equivalent to 0.16 msec in the 32 kHz mode or 11 sec in the 455 kHz mode) to get an assured input interrupt. Since the noise reject circuit continues operating with the CPU in the halt state, the CPU can be restarted by an input interrupt. Note that, if this is impossible, initial resetting under watchdog timer control is required. K13 K12 K11 K10 Interrupt factor flag IK1 (Falling edge) Noise reject circuit Mask option K03 K02 K01 K00 Noise reject circuit IK0 (Falling edge) fOSC1/8 (4 kHz) Fig. 4.10.1.2 Input interrupt circuit S1C60N06 TECHNICAL MANUAL EPSON 43 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT) <Input interrupt programming related precautions> Port K input Active status Mask register Factor flag set Not set When the content of the mask register is rewritten, while the port K input is in the active status. The input interrupt factor flag is set at . Fig. 4.10.1.3 Input interrupt timing When using an input interrupt, if you rewrite the content of the mask register, when the value of the input terminal which becomes the interrupt input is in the active status (input terminal = low status), the factor flag for input interrupt may be set. For example, a factor flag is set with the timing of shown in Figure 4.10.1.3. However, when clearing the content of the mask register with the input terminal kept in the low status and then setting it, the factor flag of the input interrupt is again set at the timing that has been set. Consequently, when the input terminal is in the active status (low status), do not rewrite the mask register (clearing, then setting the mask register), so that a factor flag will only set at the falling edge in this case. When clearing, then setting the mask register, set the mask register, when the input terminal is not in the active status (high status). 4.10.2 Interrupt mask register One interrupt mask register is available to each interrupt factor flag to mask an interrupt request. Data can be written to or read from the mask register. An interrupt request is enabled with "1" set in the register, and masked with "0" set in the register. At initial reset, the mask register is reset to "0". Table 4.10.2.1 Interrupt mask register Interrupt mask register EIT2 (0F3H*D2) EIT8 (0F3H*D1) EIT32 (0F3H*D0) EIREM (0F2H*D2) EIK1 (0F2H*D1) EIK0 (0F2H*D0) Interrupt factor flag IT2 (0F1H*D2) IT8 (0F1H*D1) IT32 (0F1H*D0) IREM (0F0H*D2) IK1 (0F0H*D1) IK0 (0F0H*D0) 4.10.3 Interrupt vector In response to an interrupt request, the CPU starts interrupt processing. The CPU saves the PC into the stack and makes a jump to the interrupt address, that is the interrupt handling routine. The interrupt address is indirectly specified by an interrupt factor. Interrupt addresses are assigned to page 1, steps 01H to 0FH of the PC. In other words, the low-order 4 bits of the PC are indirectly addressed by interrupt factors, as follows: Table 4.10.3.1 Interrupt vector PC PCS3 PCS2 PCS1 PCS0 Examples: 44 Value 1 0 1 0 1 0 1 0 Interrupt factor Timer interrupt requested Timer interrupt not requested REM interrupt requested REM interrupt not requested K10-K13 interrupt requested K10-K13 interrupt not requested K00-K03 interrupt requested K00-K03 interrupt not requested * Only timer interrupt requested * Both timer interrupt and REM interrupt requested EPSON -- Jump to page 1, step 08H -- Jump to page 1, step 0CH S1C60N06 TECHNICAL MANUAL CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT) IT2 EIT2 Interrupt vector IT8 (MSB) EIT8 IT32 Program counter Data bus EIT32 (LSB) INT (interrupt request) IREM EIREM IF IK1 EIK1 IK0 EIK0 Interrupt factor flag Interrupt mask register Fig. 4.10.3.1 Interrupt request/interrupt vector generation circuit 4.10.4 Programming notes (1) Restart from the HALT mode is performed by an interrupt. The return address after completion of the interrupt processing will be the address following the HALT instruction. (2) When an interrupt occurs, the interrupt flag will be reset by the hardware and it will become DI status. After completion of the interrupt processing, set to the EI status through the software as needed. Moreover, the nesting level may be set to be programmable by setting to the EI state at the beginning of the interrupt processing routine. (3) The interrupt factor flags must always be reset before setting the EI status. When the interrupt mask register has been set to "1", the same interrupt will occur again if the EI status is set unless of resetting the interrupt factor flag. (4) The interrupt factor flag will be reset by reading through the software. Because of this, when multiple interrupt factor flags are to be assigned to the same address, perform the flag check after the contents of the address has been stored in the RAM. Direct checking with the FAN instruction will cause all the interrupt factor flag to be reset. (5) Reading of interrupt factor flag is available at EI, but be careful in the following cases. If the interrupt mask register value corresponding to the interrupt factor flag to be read is set to "1", an interrupt request will be generated by the interrupt factor flag set timing, or an interrupt request will not be generated. Be very careful when interrupt factor flags are in the same address. S1C60N06 TECHNICAL MANUAL EPSON 45 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Lower Current Dissipation) 4.11 Lower Current Dissipation The S1C60N06 contains a control register for each circuit block to realize lower current consumption. The registers are programmed so as to operate each circuit with a minimum current. For reference in programming, the following table summarizes the circuits that can be controlled for lower current consumption and the in associated registers: Table 4.11.1 Order of current consumption Circuit system CPU CPU operating frequency Ceramic (CR) oscillation circuit REM circuit Clock timer Control register Order of current consumption HALT instruction See Capter 6, "Electrical Characteristics" CLKCHG OSCC Several tens A REMC Several A (in OSC3 mode) Several hundreds nA ("OSC3 not used" selected) TMRUN Several hundreds nA At initial setting with the CPU in operation mode, the CPU is ready with OSC3 clock (CLKCHG = "0", in high-speed mode), the ceramic (CR) oscillation circuit is ON (OSCC = 1), the REM circuit is ON (REMC = "1"), and the timer is OFF (TMRUN = "0"). It should be noted that various factors affecting current consumption. For example, a system in which a resistor is connected to the VADJ pin to control the LCD power (VL1) differ from a system in which the VADJ pin is shorted to VL1. Also, characteristics of the LCD panel used will produce a difference in power consumption to the order of several micro-amperes. 46 EPSON S1C60N06 TECHNICAL MANUAL CHAPTER 5: BASIC EXTERNAL WIRING DIAGRAM BASIC EXTERNAL WIRING DIAGRAM RESET S SR TEST - SEG19 - SEG0 COM0 CB CA C1 C SR VDD LCD COM3 CHAPTER 5 LED VADJ R A1 R A2 RRC CL1 CL2 CL3 VL1 VL2 VL3 VDD C GX X'tal OSC1 S1C60N06 RRB R33 (REM) [The potential of the substrate (back of the chip) is VDD.] 3.0V + OSC2 CD RA3 Vss R02 OSC3 Piezo C GC K10-K13 VS1 C S1 K00-K03 OSC4 P00-P03 CR RA4 R00-R01 R03 C DC TR1 Vss X'tal CGX CR CGC CDC CSR RA1 RA2 RA3, RA4 C1 CS1 CL1-CL3 Crystal oscillator Trimmer capacitor Ceramic oscillator Capacitor Capasitor Capacitor Resistor Resistor Resistor Capacitor Capacitor Capacitor 32.768kHz, CI(Max.)=35k 5-25pF 455kHz 100pF 100pF 0.33F Open(VL=1.0V), 2M (VL=1.5V) Short(VL=1.0V), 1M (VL=1.5V) 100 0.1F 0.1F 0.1F Note: The above table is simply an example, and is not guaranteed to work. S1C60N06 TECHNICAL MANUAL EPSON 47 CHAPTER 6: ELECTRICAL CHARACTERISTICS CHAPTER 6 ELECTRICAL CHARACTERISTICS 6.1 Absolute Maximum Rating Item Symbol Supply voltage VSS Input voltage (1) VI Input voltage (2) VIOSC Operating temperature Topr Storage temperature Tstg Soldering temperature / time Tsol Permissible dissipation 1 PD 1 In case of plastic package (QFP6-60pin, QFP13-64pin). (VDD=0V) Unit V V V C C - mW Rated value -5.2 to 0.5 VSS - 0.3 to 0.3 VS1 - 0.3 to 0.3 -20 to 70 -65 to 150 260C, 10sec (lead section) 250 6.2 Recommended Operating Conditions Item Supply voltage Oscillation frequency LCD drive voltage CR oscillation external resistor Symbol VSS VDD=0V fOSC1 fOSC3 Duty: 505% VL1 RCR Condition Min. -3.5 - 50 -1.6 100 (Ta=-20 to 70C) Typ. Max. Unit -3.0 -2.2 V 32.768 - kHz 455 600 kHz -1.03 - V 140 500 k 6.3 DC Characteristics Unless otherwise specified: VDD=0V, VSS=-2.2 to -3.5V, VL3=-3.0V, Ta=-20 to 70C Item Symbol High level input voltage (1) VIH1 Low level input voltage (1) VIL1 High level input voltage (2) VIH2 Low level input voltage (2) VIL2 High level input current IIH VIH=VDD Low level input current IIL1 VIL1=VSS IIL2 VIL2=VSS VIL3=VSS IIL3 VIL4=0.2*VSS IIL4 VIL5=0.2*VSS IIL5 VIL6=VSS IIL6 High level output current (1) IOH1 VOH1=0.1*VSS Low level output current (1) IOL1 VOL1=0.9*VSS High level output current (2) IOH2 VOH2=0.1*VSS Low level output current (2) IOL2 VOL2=0.9*VSS High level output current (3) IOH3 VOH3=0.1*VSS Low level output current (3) IOL3 VOL3=0.9*VSS Common output current VOH4=-0.05V IOH4 IOL4 VOL4=VL3+0.05V Segment output current IOH5 VOH5=-0.05V (during LCD output) VOL5=VL3+0.05V IOL5 1 Only at read cycle using internal program. 48 Condition K00-03, K10-13, P00-03 K00-03, K10-13, P00-03 RESET RESET K00-03, K10-13, No pull-up K00-03, K10-13, Pull-up RESET K00-03, K10-13, Pull-up RESET P00-03 *1 R00-03 R00-03 P00-03 P00-03 R33(REM) R33(REM) COM0-3 Min. 0.2*VSS VSS 0.1*VSS VSS -1 -5 -5 -50 -50 -13 1.0 1.0 1.0 3.0 SEG0-19 3.0 EPSON Typ. Max. Unit 0 V 0.8*VSS V V 0 0.9*VSS V A 1 A -0.35 A -0.35 A A A A -2 A -250 mA A -250 mA mA -1.8 mA A -3.0 A A -3.0 A S1C60N06 TECHNICAL MANUAL CHAPTER 6: ELECTRICAL CHARACTERISTICS 6.4 Analog Circuit Characteristics and Power Current Consumption Unless otherwise specified: VDD=0V, VSS=-2.2 to -3.5V, Ta=25C Item Symbol Condition LCD drive voltage VL1 VADJ=VL1, IL1=5A 1 M load connected between VDD and VL2 VL2 (no panel load) 1 M load connected between VDD and VL3 VL3 (no panel load) Current consumption HALT mode, OSCC=0 VADJ=VL1 IOP OSC1 mode, OSCC=0 no panel load OSC3 mode *1 1 Ceramic oscillation (455 kHz) or CR oscillation (RCR=140 k) Min. -1.11 2*VL1 Typ. -1.03 3*VL1 2 9 130 Max. -0.95 2*VL1 +0.1 3*VL1 +0.3 5 18 250 Unit V V V A A A 6.5 Oscillation Characteristics Oscillation characteristics will vary according to different conditions (elements used, board pattern). Use the following characteristics are as reference values. OSC1 (Crystal Oscillation) Unless otherwise specified: VDD=0V, VSS=-3.0V, Crystal oscillator: Q13MC146, CG=25pF, CD=built-in, Ta=25C Symbol Item Condition Oscillation start time VSS=-2.2 to -3.5V tsta Built-in capacitance (drain) CD Package as assembled Bare chip Frequency/voltage deviation f/V VSS=-2.2 to -3.5V Frequency/IC deviation f/IC Frequency adjustment range f/CG CG=5 to 25pF Harmonic oscillation start voltage Vhho CG=5pF (VSS) Permitted leak resistance Rleak Between OSC1 and other pins Min. - - - - -10 40 - 200 Typ. - 20 19 - - - - - Max. 3 - - 5 10 - -3.5 - Unit sec pF pF ppm ppm ppm V M Min. -2.2 - -2.2 Typ. Max. - - - Unit V mS V Min. - -2.2 - -2.2 Typ. 280 - 3 - Max. - - - - Unit kHz V mS V OSC3 (Ceramic Oscillation) Unless otherwise specified: VDD=0V, VSS=-3.0V, Ceramic oscillator: CSB455E*1, CGC=CDC=100pF, Ta=25C Item Symbol Condition Oscillation start voltage Vsta (VDD) Oscillation start time tsta VSS=-2.2 to -3.5V Oscillation stop voltage Vstp (VDD) 1 CSB455E: made by Murata Mfg.Co. 3 OSC3 (CR Oscillation) Unless otherwise specified: VDD=0V, VSS=-3.0V, RCR=140k, Ta=25C Item Symbol Oscillation frequency fOSC3 Oscillation start voltage Vsta (VDD) Oscillation start time VSS=-2.2 to -3.5V tsta Oscillation stop voltage Vstp (VDD) S1C60N06 TECHNICAL MANUAL Condition EPSON 49 CHAPTER 6: ELECTRICAL CHARACTERISTICS S1C60N06 oscillation characteristics -- fOSC3 vs RCR -- (for reference) Condition: Ta = 25C, VDD = GND, VSS = -3.0 V, Non board and package capacitance Note: Oscillation characteristics are affected by various conditions (board pattern, parts used, etc.). 1000 fOSC3 [kHz] 500 200 TYP. 100 50 30 100 200 500 1000 RCR [k ] 6.6 Input Current Characteristics (For Reference) Condition: Ta = 25C, VDD = 0 V, VSS = -3.0 V RESET P VIH (V) -3 VIH (V) -2 -1 0 -3 0 -10 -2 -1 0 0 -2 I IH -4 I IH (A) -20 (A) K -6 VIH (V) -3 -2 -1 0 0 -4 -8 I IH 50 (A) -12 EPSON S1C60N06 TECHNICAL MANUAL CHAPTER 6: ELECTRICAL CHARACTERISTICS 6.7 Output Current Characteristics (For Reference) Condition: Ta = 25C, VDD = 0 V R0, P R0, P VOH (V) -3 30 IOL (mA) Vss = -3.0 V -2 P0 R0 -1 0 0 -2 20 Vss = -2.2 V Vss = -2.2 V P0 R0 -4 -6 R0 P0 0 Vss Vss+1 Vss+2 Vss = -3.0 V I OH (mA) 10 R0 P0 -8 Vss+3 VOL (V) R33 (REM) VOH (V) -3 -2 Vss = -2.2 V -1 0 0 -10 -30 S1C60N06 TECHNICAL MANUAL I OH (mA) -20 Vss = -3.0 V EPSON 51 CHAPTER 7: PACKAGE CHAPTER 7 PACKAGE 7.1 Plastic Package QFP6-60pin (Unit: mm) 17.60.4 140.2 45 31 140.2 INDEX 16 60 1 15 0.350.1 0.1 2.70.1 0.8 3.1max 17.60.4 30 46 0.150.05 0 10 0.2 0.85 1.8 QFP13-64pin (Unit: mm) 120.4 100.1 48 33 120.4 32 100.1 49 INDEX 64 17 1.40.1 16 0.5 +0.1 0.18 -0.05 +0.05 0.125 -0.025 0 10 0.2 0.5 0.1 1.7max 1 1 The dimensions are subjected to change without notice. 52 EPSON S1C60N06 TECHNICAL MANUAL CHAPTER 7: PACKAGE 7.2 Ceramic Package for Test Samples (Unit: mm) 81.3 PIN NO. 1 2 23.1 34 33 22.8 64 63 31 32 INDEX MARK 2.54 78.7 No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pin name SEG19 COM3 COM2 COM1 COM0 No. 17 18 19 20 21 VL1 22 23 24 25 26 27 28 29 30 31 32 K11 VL2 VL3 N.C. VADJ CA CB VSS OSC4 OSC3 VS1 S1C60N06 TECHNICAL MANUAL Pin name OSC2 OSC1 VDD P03 P02 P01 P00 N.C. N.C. N.C. K00 K01 K02 K03 K10 No. 33 34 35 36 37 Pin name K12 K13 R00 R01 R02 38 39 40 41 42 43 44 45 46 47 48 R03 54 SEG11 N.C. 55 N.C. N.C. 56 TEST N.C. 57 RESET R33(REM) 58 SEG12 SEG0 59 SEG13 SEG1 60 SEG14 SEG2 61 SEG15 SEG3 62 SEG16 SEG4 63 SEG17 SEG5 64 SEG18 N.C. = No Connection EPSON No. 49 50 51 52 53 Pin name SEG6 SEG7 SEG8 SEG9 SEG10 53 CHAPTER 8: PAD LAYOUT CHAPTER 8 PAD LAYOUT 8.1 Diagram of Pad Layout 10 5 56 55 1 15 Y 50 (0, 0) 2.91 mm 20 X Die No. 45 25 30 35 40 2.74 mm 8.2 Pad Coordinates No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 54 Pad name R33(REM) SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 TEST RESET SEG12 SEG13 SEG14 SEG15 X 806 613 483 353 223 93 -37 -167 -297 -427 -557 -687 -817 -1204 -1204 -1204 -1204 -1204 -1204 Y 1285 1285 1285 1285 1285 1285 1285 1285 1285 1285 1285 1285 1285 1215 1086 858 728 598 468 No. 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 Pad name SEG16 SEG17 SEG18 SEG19 COM3 COM2 COM1 COM0 VL1 VL2 VL3 VADJ CA CB VSS OSC4 OSC3 VS1 OSC2 X -1204 -1204 -1204 -1204 -1204 -1204 -1204 -1204 -1204 -1204 -1204 -1184 -997 -867 -130 0 130 260 390 EPSON Y 338 208 78 -52 -236 -366 -496 -626 -756 -886 -1024 -1285 -1285 -1285 -1285 -1285 -1285 -1285 -1285 No. 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 - Pad name OSC1 VDD P03 P02 P01 P00 K00 K01 K02 K03 K10 K11 K12 K13 R00 R01 R02 R03 Unit: m X Y 520 -1285 650 -1285 787 -1285 917 -1285 1047 -1285 1178 -1285 1204 -249 1204 -119 1204 11 1204 141 1204 271 1204 401 1204 531 1204 661 1204 806 1204 937 1204 1067 1204 1198 S1C60N06 TECHNICAL MANUAL CHAPTER 9: PRECAUTIONS ON MOUNTING CHAPTER 9 PRECAUTIONS ON MOUNTING <Oscillation Circuit> Oscillation characteristics change depending on conditions (board pattern, components used, etc.). In particular, when a ceramic oscillator or crystal oscillator is used, use the oscillator manufacturer's recommended values for constants such as capacitance and resistance. Disturbances of the oscillation clock due to noise may cause a malfunction. Consider the following points to prevent this: (1) Components which are connected to the OSC1, OSC2, OSC3 and OSC4 terminals, such as oscillators, resistors and capacitors, should be connected in the shortest line. (2) As shown in the right hand figure, make a VDD pattern as large as possible at circumscription of the OSC1/OSC3 and OSC2/OSC4 terminals and the components connected to these terminals. Furthermore, do not use this VDD pattern for any purpose other than the oscillation system. Examples of pattern and oscillator layout Crystal oscillator Ceramic oscillator OSC2 OSC4 OSC1 OSC3 VDD VDD In order to prevent unstable operation of the oscillation circuit due to current leak between OSC1/ OSC3 and VSS, please keep enough distance between OSC1/OSC3 and VSS or other signals on the board pattern. <Reset Circuit> The power-on reset signal which is input to the RESET terminal changes depending on conditions (power rise time, components used, board pattern, etc.). Decide the time constant of the capacitor and resistor after enough tests have been completed with the application product. When the built-in pull-up resistor of the RESET terminal, take into consideration dispersion of the resistance for setting the constant. In order to prevent any occurrences of unnecessary resetting caused by noise during operating, components such as capacitors and resistors should be connected to the RESET terminal in the shortest line. <Power Supply Circuit> Sudden power supply variation due to noise may cause malfunction. Consider the following points to prevent this: (1) The power supply should be connected to the VDD and VSS terminal with patterns as short and large as possible. (2) When connecting between the VDD and VSS terminals with a bypass capacitor, the terminals should be connected as short as possible. S1C60N06 TECHNICAL MANUAL EPSON 55 CHAPTER 9: PRECAUTIONS ON MOUNTING Bypass capacitor connection example VDD VDD VSS VSS (3) Components which are connected to the VS1, VL1, VL2 and VL3 terminals, such as capacitors and resistors, should be connected in the shortest line. In particular, the VL1, VL2 and VL3 voltages affect the display quality. Do not connect anything to the VL1, VL2 and VL3 terminals when the LCD driver is not used. <Arrangement of Signal Lines> In order to prevent generation of electromagnetic induction noise caused by mutual inductance, do not arrange a large current signal line near the circuits that are sensitive to noise such as the oscillation unit. When a signal line is parallel with a high-speed line in long distance or intersects a high-speed line, noise may generated by mutual interference between the signals and it may cause a malfunction. Do not arrange a high-speed signal line especially near circuits that are sensitive to noise such as the oscillation unit. Prohibited pattern OSC4 OSC3 VDD Large current signal line High-speed signal line <Precautions for Visible Radiation (when bare chip is mounted)> Visible radiation causes semiconductor devices to change the electrical characteristics. It may cause this IC to malfunction. When developing products which use this IC, consider the following precautions to prevent malfunctions caused by visible radiations. (1) Design the product and implement the IC on the board so that it is shielded from visible radiation in actual use. (2) The inspection process of the product needs an environment that shields the IC from visible radiation. (3) As well as the face of the IC, shield the back and side too. 56 EPSON S1C60N06 TECHNICAL MANUAL International Sales Operations AMERICA ASIA EPSON ELECTRONICS AMERICA, INC. EPSON (CHINA) CO., LTD. - HEADQUARTERS - 28F, Beijing Silver Tower 2# North RD DongSanHuan ChaoYang District, Beijing, CHINA Phone: 64106655 Fax: 64107319 1960 E. Grand Avenue EI Segundo, CA 90245, U.S.A. Phone: +1-310-955-5300 Fax: +1-310-955-5400 SHANGHAI BRANCH 4F, Bldg., 27, No. 69, Gui Jing Road Caohejing, Shanghai, CHINA Phone: 21-6485-5552 Fax: 21-6485-0775 - SALES OFFICES West 150 River Oaks Parkway San Jose, CA 95134, U.S.A. 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FRENCH BRANCH OFFICE 1 Avenue de l' Atlantique, LP 915 Les Conquerants Z.A. de Courtaboeuf 2, F-91976 Les Ulis Cedex, FRANCE Phone: +33-(0)1-64862350 Fax: +33-(0)1-64862355 BARCELONA BRANCH OFFICE Barcelona Design Center Edificio Prima Sant Cugat Avda. Alcalde Barrils num. 64-68 E-08190 Sant Cugat del Valles, SPAIN Phone: +34-93-544-2490 Fax: +34-93-544-2491 421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN Phone: +81-(0)42-587-5812 Fax: +81-(0)42-587-5564 ED International Marketing Department Asia 421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN Phone: +81-(0)42-587-5814 Fax: +81-(0)42-587-5110 In pursuit of "Saving" Technology, Epson electronic devices. Our lineup of semiconductors, liquid crystal displays and quartz devices assists in creating the products of our customers' dreams. Epson IS energy savings. S1C60N06 Technical Manual ELECTRONIC DEVICES MARKETING DIVISION EPSON Electronic Devices Website http://www.epson.co.jp/device/ First issue September, 1998 Printed February, 2001 in Japan M A