682
Fibre Channel Transceiver Chip
Technical Data
HDMP-1526 Transceiver
Features
• ANSI X3.230-1994 Fibre
Channel Compatible (FC-0)
• Supports Full Speed
(1062.5 MBd) Fibre Channel
• Conforms to “Fibre Channel
10-Bit Interface”
Specification
• Transmitter and Receiver
Functions Incorporated onto
a Single IC
• 10-Bit Wide Parallel TTL
Compatible I/Os
• Single +5.0 V Power Supply
Applications
• 1062.5 MBd Fibre Channel
Interface
• Mass Storage System I/O
Channel
• Work Station/Server I/O
Channel
• High Speed Proprietary
Interface
Description
The HDMP-1526 transceiver is a
single silicon bipolar integrated
circuit packaged in an EDQuad
package. It provides a low-cost,
low-power physical layer solution
for 1062.5 MBd Fibre Channel or
proprietary link interfaces. It
provides complete FC-0 func-
tionality for copper transmission,
incorporating both the Fibre
Channel FC-0 transmit and
receive functions into a single
device.
This chip is used to build a high-
speed interface (as shown in
Figure 1) while minimizing board
space, power and cost. It is
compatible with both the ANSI
X3.230-1994 document and the
“Fibre Channel 10-bit Interface”
specification.
The transmitter section accepts
10-bit wide parallel TTL data and
multiplexes this data into a high-
speed serial data stream. The
parallel data is expected to be
8B/10B encoded data, or
equivalent. This parallel data is
latched into the input register of
the transmitter section on the
rising edge of the 106.25 MHz
reference clock (used as the
transmit byte clock).
The transmitter section’s PLL
locks to this user supplied 106.25
MHz byte clock. This clock is
multiplied by 10, to generate the
1062.5 MHz serial signal clock
used to generate the high-speed
output. The high-speed outputs
are capable of interfacing directly
to copper cables for electrical
transmission or to a separate
fiber-optic module for optical
transmission.
The receiver section accepts a
serial electrical data stream at
1062.5 MBd and recovers the
original 10-bit wide parallel data.
The receiver PLL locks onto the
incoming serial signal and
recovers the high-speed serial
clock and data. The serial data is
converted back into 10-bit
parallel data, recognizing the
8B/10B comma character to
establish byte alignment.
The recovered parallel data is
presented to the user at TTL
compatible outputs. The receiver
section also recovers two 53.125
MHz receiver byte clocks that are
180 degrees out of phase with
each other. The parallel data is
aligned with the rising edge of
alternating clocks.
The transceiver provides for on-
chip local loop-back functionality,
controlled through an external
input pin. Additionally, the byte
synchronization feature may be
disabled. This may be useful in
proprietary applications that use
alternative methods to align the
parallel data.
5964-6897E (5/96)
683
HDMP-1526
PROTOCOL DEVICE
SERIAL DATA OUT
RECEIVER SECTION
PLL
TRANSMITTER SECTION
BYTSYNC
-LCKREF
ENBYTSYNC
REFCLK
SERIAL DATA IN
PLL
Figure 1. Typical Application Using the HDMP-1526.
± DOUT
TX
PLL/CLOCK
GENERATOR
REFCLK
± DIN
-LCKREF
RXCAP0
RXCAP1
RBC0
RBC1
BYTSYNC ENBYTSYNC
OUTPUT
DRIVER
INTERNAL
Tx CLOCKS
INPUT
LATCH
DATA BYTE
RX[0-9]
TXCAP1
TXCAP0
DATA BYTE
TX[0-9]
INTERNAL
Rx CLOCKS
LOOPEN
INTERNAL
LOOPBACK
OUTPUT
SELECT
FRAME
MUX
RX
PLL/CLOCK
RECOVERY
INPUT
SELECT
FRAME
DEMUX
AND
BYTE SYNC INPUT
SAMPLER
Figure 2. HDMP-1526 Transceiver Block Diagram.
HDMP-1526 Block Diagram
The HDMP-1526 was designed to
transmit and receive 10-bit wide
parallel data over a single high-
speed line, as specified for the FC-0
layer of the Fibre Channel standard.
The parallel data applied to the
transmitter is expected to be
encoded per the Fibre Channel
specification, which uses an 8B/10B
encoding scheme with special
reserve characters for link
management purposes. In order to
accomplish this task, the HDMP-
1526 incorporates the following:
• TTL Parallel I/Os
• High-Speed Phase Lock Loops
• Clock Generation/Recovery
Circuitry
• Parallel-to-Serial Converter
• High-Speed Serial Clock-and-Data
Recovery Circuitry
• Comma Character Recognition
Circuitry
• Byte Alignment Circuitry
• Serial-to-Parallel Converter
INPUT LATCH
The transmitter accepts 10-bit wide
TTL parallel data at inputs TX[0..9].
The user-provided reference clock
signal, REFCLK, is also used as the
transmit byte clock. The TX[0..9]
and REFCLK signals must be
properly aligned, as shown in
Figure 3.
TX PLL/CLOCK GENERATOR
The transmitter Phase Lock Loop
and Clock Generator (TX PLL/
CLOCK GENERATOR) block is
responsible for generating all
internal clocks needed by the
transmitter section to perform its
functions. These clocks are based on
the supplied reference byte clock
(REFCLK). REFCLK is used as both
the frequency reference clock for
the PLL and the transmit byte clock
for the incoming data latches. It is
expected to be 106.25 MHz and
properly aligned to the incoming
684
parallel data (see Figure 3). This
clock is multiplied by 10 to
generate the 1062.5 MHz clock
necessary for the high-speed
serial outputs.
FRAME MUX
The FRAME MUX accepts the 10-
bit wide parallel data from the
INPUT LATCH. Using internally
generated high-speed clocks, this
parallel data is multiplexed into
the 1062.5 MBd serial data
stream. The data bits are
transmitted sequentially, from the
least significant bit (TX[0]) to the
most significant bit (TX[9]).
OUTPUT SELECT
The OUTPUT SELECT block
provides for an optional internal
loopback of the high-speed serial
signal, for testing purposes.
In normal operation, LOOPEN is
set low and the serial data stream
is placed at ±DOUT. When wrap-
mode is activated by setting
LOOPEN high, the ±DOUT pins
are held static and the serial
output signal is internally
wrapped to the INPUT SELECT
box of the receiver section.
INPUT SELECT
The INPUT SELECT block
determines whether the signal at
±DIN or the internal loop-back
serial signal is used. In normal
operation, LOOPEN is set low
and the serial data is accepted at
±DIN. When LOOPEN is set
high, the high-speed serial signal
is internally looped-back from the
transmitter section to the receiver
section. This feature allows for
loop-back testing exclusive of the
transmission medium.
RX PLL/CLOCK RECOVERY
The RX PLL/CLOCK RECOVERY
block is responsible for frequency
and phase locking onto incoming
serial data stream and recovering
the bit and byte clocks.
In order to accomplish this, upon
startup, the user should set
-LCKREF low for a period of at
least 500 µsec. This allows the
PLL to first frequency lock onto
the 106.25 MHz reference clock
provided at the REFCLK input.
The RX PLL/CLOCK RECOVERY
circuitry multiplies this reference
clock by 10 to generate an
internal 1062.5 MHz clock. After
500 µsec, the user should set
-LCKREF high. This will allow the
receiver to frequency and phase
lock the internal 1062.5 MHz
clock onto the incoming serial
data stream. Once locked, the
receiver will recover the two
53.125 MHz receiver byte clocks
(RBC1/RBC0). These byte clocks
are approximately 180° out of
phase with each other and are
alternately used to clock the
10-bit parallel output data.
INPUT SAMPLER
The INPUT SAMPLER is
responsible for converting the
serial input signal into a retimed
serial bit stream. In order to
accomplish this, it uses the high
speed serial clock recovered from
the RX PLL/CLOCK RECOVERY
block. This serial bit stream is
sent to the FRAME DEMUX and
BYTE SYNC block.
FRAME DEMUX AND BYTE
SYNC
The FRAME DEMUX AND BYTE
SYNC block is responsible for
restoring the 10-bit parallel data
from the high speed serial bit
stream. This block is also
responsible for recognizing the
comma character (or a K28.5
character) of positive disparity
(0011111xxx). When recognized,
the FRAME DEMUX AND BYTE
SYNC block works with the RX
PLL/CLOCK RECOVERY block to
properly align the receive byte
clocks to the parallel data. When
a comma character is detected
and realignment of the receiver
byte clocks (RBC1/RBC0) is
necessary, these clocks are
stretched, not slivered, to the
next possible correct alignment
position. These clocks will be
fully aligned by the start of the
second 4-byte ordered set. The
second comma character received
shall be aligned with the rising
edge of RBC1. Comma characters
should not be transmitted in
consecutive succession to allow
the receiver byte clocks to
maintain their proper recovered
frequencies.
OUTPUT DRIVERS
The OUTPUT DRIVERS present
the 10-bit parallel recovered data
byte properly aligned to the
receive byte clocks (RBC1/
RBC0), as shown in Figure 4.
These output data buffers provide
TTL compatible signals.
685
HDMP-1526 (Transmitter Section)
Timing Characteristics
TC = 0°C to +85°C, VCC = 4.5 V to 5.25 V
Symbol Parameter Units Min. Typ. Max.
tsetup Setup Time nsec 2
thold Hold Time nsec 1.5
t_txlat[1] Transmitter Latency nsec 6.25 12.2
bits 6.64 13.0
Note:
1. The transmitter latency, as shown in Figure 4, is defined as the time between the latching in of the parallel data word (as triggered
by the rising edge of the transmit byte clock, REFCLK) and the transmission of the first serial bit of that parallel word (defined by the
rising edge of the first bit transmitted).
Figure 3. Transmitter Section Timing.
,,
,
DATA DATA
TX[0]-TX[9]
t-SETUP t-HOLD
REFCLK
,
DATA
,
,
,
DATA DATA
1.4 V
2.0 V
0.8 V
Figure 4. Transmitter Latency.
,,
DATA BYTE B DATA BYTE C
TX[0]-TX[9]
DATA BYTE A
± DOUT
,,
1.4 V
DATA BYTE B
t_TXLAT
T5 T6 T7 T8 T9 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T0 T1 T2 T3 T4 T5
REFCLK
686
HDMP-1526 (Receiver Section)
Timing Characteristics
TC = 0°C to +85°C, VCC = 4.5 V to 5.25 V
Symbol Parameter Units Min. Typ. Max.
b_sync[1,2] Bit Sync Time bits 2500
f_lock[2] Frequency Lock Time µsec 500
(from Time of Setting -LCKREF = 0)
f_lock_rate[2] Frequency Lock Rate (when -LCKREF = 0) kHz/µsec 200
tvalid_before Time Data Valid Before Rising Edge of RBC nsec 3 5.8
tvalid_after Time Data Valid After Rising Edge of RBC nsec 1.5 3.3
tduty RBC Duty Cycle % 40 60
tA-B[3] Rising Edge Time Difference nsec 8.9 9.4 9.9
t_rxlat[4] Receiver Latency nsec 25.0 33.9
bits 26.6 36
Notes:
1. This is the recovery time for input phase jumps, per the FC-PH specification Ref 4.1, Sec 5.3.
2. Tested using CPLL = 0.01 µF.
3. The RBC clock skew is calculated as tA-B(max) - tA-B(min).
4. The receiver latency, as shown in Figure 5, is defined as the time between receiving the first serial bit of a parallel data word (as
defined as the first edge of the first serial bit) and the clocking out of that parallel word (defined by the rising edge of the receive
byte clock, either RBC1 or RBC0).
,
,,
DATA DATA
RX[0]-RX[9]
t-VALID BEFORE
t-VALID AFTER
RBC1
,
K28.5
,
,,
,,
DATA DATA
1.4 V
2.0 V
0.8 V
BYTSYNC
RBC0
2.0 V
0.8 V
1.4 V
Figure 6. Receiver Latency.
,,
DATA BYTE A DATA BYTE D
RX[0]-RX[9]
DATA BYTE D
± DIN
,,
1.4 V
t_RXLAT
R5 R6 R7 R8 R9 R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R2 R3 R4 R5
RBC1/0
DATA BYTE C
Figure 5. Receiver Section.
687
HDMP-1526 (TRx)
Absolute Maximum Ratings
TA = 25°C, except as specified. Operation in excess of any one of these conditions may result in permanent
damage to this device.
Symbol Parameter Units Min. Max.
VCC Supply Voltage V -0.5 6.0
VIN,TTL TTL Input Voltage V -0.7 VCC + 0.7
VIN,HS_IN HS_IN Input Voltage V 2.0 VCC
IO,TTL TTL Output Source Current mA 13
Tstg Storage Temperature °C -40 +130
TjJunction Operating Temperature °C 0 +130
Maximum Assembly Temperature (for 10 seconds maximum) °C +260
HDMP-1526 (TRx)
Recommended Operating Conditions
Symbol Parameter Units Min. Max.
VCC Supply Voltage V 4.5 5.25
TCCase Temperature °C085
HDMP-1526 (TRx)
Transceiver Reference Clock Requirements
TC = 0°C to +85°C, VCC = 4.5 V to 5.25 V
Symbol Parameter Unit Min. Typ. Max.
f Nominal Frequency (for Fibre Channel Compliance) MHz 106.20 106.25 106.30
Ftol Frequency Tolerance ppm -100 +100
Symm Symmetry (Duty Cycle) % 40 60
HDMP-1526 (Trx)
DC Electrical Specifications
TC = 0°C to +85°C, VCC = 4.5 V to 5.25 V
Symbol Parameter Unit Min. Typ. Max.
VIH,TTL TTL Input High Voltage Level, Guaranteed High Signal V 2 VCC
for All TTL Inputs
VIL,TTL TTL Input Low Voltage Level, Guaranteed Low Signal for V 0 0.8
All TTL Inputs
VOH,TTL TTL Output High Voltage Level, IOH = -400 µA V 2.4 VCC
VOL,TTL TTL Output Low Voltage Level, IOL = 1 mA V 0 0.6
IIH,TTL Input High Current (Magnitude), VIN = VCC µA 0.004 40
IIL-TTL Input Low Current (Magnitude), VIN = 0 Volts µA 295 600
ICC,TRx[1,2] Transceiver VCC Supply Current, TA = 25°C mA 375 475
Notes:
1. Measurement Conditions: Tested sending 1062.5 MBd PRBS 27-1 sequence with both DOUT outputs biased with 270 Ω resistors
and the receiver TTL outputs driving 10 pF loads.
2. Typical specified with VCC = 5.0 volts, maximum specified with VCC = 5.25 volts.
688
HDMP-1526 (TRx)
AC Electrical Specifications
TC = 0°C to +85°C, VCC = 4.5 V to 5.25 V
Symbol Parameter Units Min. Typ. Max.
tr,TTLin Input TTL Rise Time, 0.8 to 2.0 Volts nsec 2
tf,TTLin Input TTL Fall Time, 2.0 to 0.8 Volts nsec 2
tr,TTLout Output TTL Rise Time, 0.8 to 2.0 Volts, 10 pF Load nsec 1.1 2.4
tf,TTLout Output TTL Fall Time, 2.0 to 0.8 Volts, 10 pF Load nsec 1.5 2.4
trs,HS_OUT[1,2] HS_OUT Single-Ended (+DOUT) Rise Time psec 190 400
tfs,HS_OUT[1,2] HS_OUT Single-Ended (+DOUT) Fall Time psec 170 400
trd,HS_OUT[1,2,3] HS_OUT Differential Rise Time psec 180
tfd,HS_OUT[1,2,3] HS_OUT Differential Fall Time psec 230
VIP,HS_IN[3,4] HS_IN Input Peak-to-Peak Differential Voltage mV 200 1200 2200
VOP,HS_OUT[1,3] HS_OUT Output Peak-to-Peak Differential Voltage mV 1200 1740 2200
Notes:
1. Each output is measured with a 270 Ω bias resistor to ground and a 50 Ω AC load.
2. Specified between 20% and 80% points of full voltage swing.
3. Output Peak-to-Peak Differential Voltage specified as DOUT+ minus DOUT-.
4. Measured using a 50 Ω load.
a. Differential HS_OUT Output (Dout+ Minus Dout-).
Figure 7. Transmitter DOUT Eye Diagrams.
b. Single-Ended HS_OUT Output (Dout+).
TIME BASE UNITS
TIME BIT PERIOD
BIT RATE
1.06250 0BITS/s
SCALE
2.000 BIT
POSITION
218.68931 BIT
REFERENCE
LEFT CENTER
TIME BASE WINDOWING...
205.0252 ns100.2 ps/div
f1 150 mU/div
t
X1
X2
FC1063
TIME BASE UNITS
TIME BIT PERIOD
BIT RATE
1.06250 0BITS/s
SCALE
2.000 BIT
POSITION
218.01994 BIT
REFERENCE
LEFT CENTER
TIME BASE WINDOWING...
205.1952 ns188.2 ps/div
f1 250 mU/div
t
FC1063
689
HDMP-1526 (Transmitter Section)
Output Jitter Characteristics
TC = 0°C to +85°C, VCC = 4.5 V to 5.25 V
Symbol Parameter Units Typ.
RJ[1] Random Jitter at DOUT, the High Speed Electrical Data Port, specified as ps 8
1 sigma deviation of the 50% crossing point
DJ[1] Deterministic Jitter at DOUT, the High Speed Electrical Data Port ps 35
Note:
1. Defined by Fibre Channel Specification Rev 4.1, Annex A, Section A.4 and tested using measurement method shown in Figure 8.
HDMP-1526 (TRx)
Thermal and Power Temperature Characteristics,
TC = 0°C to +85°C, VCC = 4.5 V to 5.25 V
Symbol Parameter Units Typ. Max.
PD,TRx[1,2] Transceiver Power Dissipation, Outputs Open, Parallel Data Watt 1.6
has 5 Ones and 5 Zeroes
PD,TRx[1,2,3] Transceiver Power Dissipation, Outputs Connected per Watt 1.8 2.4
Recommended Bias Terminations
Θjc[4] Thermal Resistance, Junction to Case °C/Watt 7
Notes:
1. PD is calculated by multiplying the max VCC by the max ICC and subtracting the power dissipated outside the chip at the high speed
bias resistors.
2. Typical specified with VCC = 5 volts, maximum specified with VCC = 5.25 volts.
3. Specified with high speed outputs biased with 270 Ω resistors and receiver TTL outputs driving 10 pF loads. Pattern is PRBS 27-1.
4. Based on independant package testing by HP.
Figure 8. Transmitter Jitter Measurement Method.
HP70841B
PATTERN
GENERATOR*
HP83480A
OSCILLOSCOPE
HDMP-1526
HP70311A
CLOCK SOURCE
+ DATA
- DATA
+K28.5, -K28.5
TRIGGER
CH1 CH2
+DOUT -DOUT
REFCLK LOOPEN
Tx[0..9]
1.0625 GHz
106.25 MHz ENBYTSYNC
Rx[0..9]
-DIN
+DIN
DIVIDE
BY 2
CIRCUIT
DIVIDE
BY 10
CIRCUIT
(DUAL
OUTPUT)
VARIABLE
DELAY
HP70841B
PATTERN
GENERATOR* HP83480A
OSCILLOSCOPE
HDMP-1526
HP70311A
CLOCK SOURCE
+ DATA
- DATA
0000011111
TRIGGER
CH1 CH2
+DOUT -DOUT
REFCLK LOOPEN
Tx[0..9]
BIAS
TEE
1.4 V 0011111000
(STATIC K28.7)
1.0625 GHz
106.25 MHz
* PATTERN
GENERATOR
PROVIDES A
DIVIDE BY
10 FUNCTION.
a. Block Diagram of RJ Measurement Method. b. Block Diagram of DJ Measurement Method.
690
I/O Type Definitions
I/O Type Definition
I-TTL Input TTL. Floats High When Left Open.
O-TTL Output TTL
HS_OUT High Speed Output. ECL Compatible
HS_IN High Speed Input, Internally Biased, High Input Resistance
C External Circuit Node
S Power Supply or Ground
HDMP-1526 (TRx)
Pin Input Capacitance
Symbol Parameter Units Typ. Max.
CINPUT Pin Input Capacitance pF 1.6 4.0
V
CC
_TTL
10 k
V
BB
1.4 V
10 k
GND_TTL
V
CC
_TX
or
V
CC
_RX
ESD
PROTECTION
GND_TTL
V
CC
_TTL
6 k 36
72800
O_TTL I_TTL
GND ESD
PROTECTION
V
CC
_TX
HS_OUT
3.2 K
0.01 µF
0.01 µF
Zo = 75 Ω
Zo = 75 Ω
V
CC
_TXHS
V
CC
_TXECL
GND
ESD
PROTECTION
-DOUT
+DOUT
270
270
75
75
GND_TXHS
0.01 µF
+DIN
-DIN
ESD
PROTECTION
3.2 K
+
–+
–
HS_IN
75
75
V
CC
_RX
GND
GND_RXHS
V
CC
_RXHS 2 V 2 V
60 µA 60 µA
Figure 10. HS_OUT and HS_IN Simplified Circuit Schematic.
Notes:
1. HS_IN inputs should never be connected to ground as permanent damage to the device may result.
2. 75 Ω serial padding resistors are optional, the serial resistors should be matched to the receiver input bias resistors.
Figure 9. O-TTL and I-TTL Simplified Circuit Schematic.
691
RXCAP0
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
GND_TXHS
HDMP-1526
xxxx YYWW
hp
COUNTRY
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1617 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
BYTSYNC
GND_RXTTL
RX[0]
RX[1]
RX[2]
V
CC
_RXTTL
RX[3]
RX[4]
RX[5]
RX[6]
V
CC
_RXTTL
RX[7]
RX[8]
RX[9]
GND_RXTTL
GND_TXTTL
TX[0]
TX[1]
TX[2]
V
CC
_TXTTL
TX[3]
TX[4]
TX[5]
TX[6]
V
CC
_TXTTL
TX[7]
TX[8]
TX[9]
GND_TXTTL
GND_TXA
TXCAP1
V
CC
_TXHS
+DOUT
-DOUT
V
CC
_TXECL
V
CC
_TX
GND
V
CC
_RX
GND_RXHS
V
CC
_RXHS
+DIN
V
CC
_RXHS
-DIN
GND_RXA
V
CC
_RXA
RXCAP1
TXCAP0
V
CC
_TXA
LOOPEN
V
CC
_TX
GND
REFCLK
V
CC
_RX
ENBYTSYNC
GND
N/C
-LCKREF
V
CC
_RX
V
CC
_RXTTL
RBC1
RBC0
GND_RXTTL
xxxx = WAFER LOT NUMBER
YYWW = DATE CODE (YY = YEAR, WW = WORK WEEK)
COUNTRY = COUNTRY OF MANUFACTURE
Figure 11. HDMP-1526 (TRx) Package Layout and Marking, Top View.
692
TRx I/O Definition
Name Pin Type Signal
GND_TXTTL 1 S TTL Transmitter Ground: Normally 0 volts. Used for the TTL input cells
14 of the transmitter section.
TX[0] 2 I-TTL Data Inputs: One, 10 bit, pre-encoded data byte. TX[0] is the first bit
TX[1] 3 transmitted. TX[0] is the least significant bit.
TX[2] 4
TX[3] 6
TX[4] 7
TX[5] 8
TX[6] 9
TX[7] 11
TX[8] 12
TX[9] 13
VCC_TXTTL 5 S TTL Power Supply: Normally 5 volts. Used for all TTL transmitter input
10 buffer cells.
GND_TXA 15 S Analog Ground: Normally 0 volts. Used to provide a clean ground plane
for the PLL and high-speed analog cells.
TXCAP1 16 C Loop Filter Capacitor: A loop filter capacitor must be connected across
TXCAP0 17 the TXCAP1 and TXCAP0 pins (typical value = 0.01 µF).
VCC_TXA 18 S Analog Power Supply: Normally 5 volts. Used to provide a clean supply
line for the PLL and high-speed analog cells.
LOOPEN 19 I-TTL Loopback Enable Input: When set high, the high-speed serial signal is
internally wrapped from the transmitter’s serial loopback outputs back
to the receiver’s loopback inputs. Also, when in loopback mode, the
±DOUT outputs are held static. When set low, ±DOUT outputs and
±DIN inputs are active.
VCC_TX 20 S Logic Power Supply: Normally 5 volts. Used for internal transmitter
59 PECL logic. It should be isolated from the noisy TTL supply as well as
possible.
GND 21 S Logic Ground: Normally 0 volts. This ground is used for internal PECL
25 logic. It should be isolated from the noisy TTL ground as well as possible.
58
REFCLK 22 I-TTL Reference Clock and Transmit Byte Clock: A 106.25 MHz clock supplied
by the host system. The transmitter section accepts this signal as the
frequency reference clock. It is multiplied by 10 to generate the serial bit
clock and other internal clocks. The transmit side also uses this clock as
the transmit byte clock for the incoming parallel data TX[0]..TX[9]. It
also serves as the reference clock for the receive portion of the
transceiver. When -LCKREF is activated, the receiver PLL frequency
locks to this reference signal.
VCC_RX 23 S Logic Power Supply: Normally 5 volts. Used for internal receiver PECL
28 logic. It should be isolated from the noisy TTL supply as well as possible.
57
ENBYTSYNC 24 I-TTL Enable Byte Sync Input: When high, enables the internal byte sync
function to allow clock synchronization to a comma character (or a
K28.5 character) of positive disparity (0011111010). When the line is
low, the function is disabled and will not reset registers and clocks, or
strobe the BYTSYNC line.
-LCKREF 27 I-TTL Lock to Reference: When low, causes the PLL to acquire frequency lock
on the external reference, supplied at REFCLK.
693
TRx I/O Definition (cont’d.)
Name Pin Type Signal
VCC_RXTTL 29 S TTL Power Supply: Normally 5 volts. Used for all TTL receiver output
37 buffer cells.
42
RBC1 30 O-TTL Receiver Byte Clocks: The receiver section recovers two 53.125 MHz
RBC0 31 receive byte clocks. These two clocks are approximately 180 degrees out
of phase. The receiver parallel data outputs are alternatively clocked on
the rising edge of these clocks. RBC1 aligns and outputs the comma
character (for byte alignment) when detected.
GND_RXTTL 32 S TTL Receiver Ground: Normally 0 volts. Used for the TTL output cells
33 of the receiver section.
46
RX[0] 45 O-TTL Data Outputs: One 10 bit data byte. RX[0] is the first bit received.
RX[1] 44 RX[0] is the least significant bit.
RX[2] 43
RX[3] 41
RX[4] 40
RX[5] 39
RX[6] 38
RX[7] 36
RX[8] 35
RX[9] 34
BYTSYNC 47 O-TTL Byte Sync Output: An active high output. Used to indicate detection of
either a comma character or a K28.5 special character of positive
disparity. It is only active when ENBYTSYNC is enabled.
RXCAP0 48 C Loop Filter Capacitor: A loop filter capacitor for the internal PLL is
RXCAP1 49 connected across the RXCAP0 and RXCAP1 pins.
(typical value = 0.01 µF).
VCC_RXA 50 S Analog Power Supply: Normally 5 volts. Used to provide a clean supply
line for the PLL and high-speed analog cells.
GND_RXA 51 S Analog Ground: Normally 0 volts. Used to provide a clean ground
plane for the receiver PLL and high-speed analog cells.
-DIN 52 HS_IN Serial Data Inputs: High-speed inputs. Serial data is accepted from the
+DIN 54 ±DIN inputs when LOOPEN is low.
VCC_RXHS 53 S High-Speed Supply: Normally 5 volts. Used only for the high-speed
55 receiver cell (HS_IN). Noise on this line should be minimized for best
operation.
GND_RXHS 56 S Ground: Normally 0 volts.
VCC_TXECL 60 S High-Speed ECL Supply: Normally 5 volts. Used only for the last stage
of the high-speed transmitter output cell (HS_OUT) as shown in
Figure 9. Due to high current transitions, this VCC should be well
bypassed to a ground plane.
VCC_TXHS 63 S High-Speed Supply: Normally 5 volts. Used by the transmitter side
for the high-speed circuitry. Noise on this line should be minimized
for best operation.
-DOUT 61 HS_OUT Serial Data Outputs: High-speed outputs. These lines are active when
+DOUT 62 LOOPEN is set low. When LOOPEN is set high, these outputs are held
static.
GND_TXHS 64 S Ground: Normally 0 volts.
694
Transceiver Package
Information
The HDMP-1526 is constructed
of a single integrated circuit
packaged in a 14x14 mm
EDQuad package. This package
was designed to provide
enhanced power dissipation, thus
allowing for smaller package
dimensions. The package
conforms to the industry standard
JEDEC land pattern for 14x14
mm devices. As shown in Figure
12, the die is attached to a
copper heatsink using thermally
conductive epoxy. This allows for
the power dissipated by the IC to
be directly connected to the
ambient environment, thereby
minimizing the Θjc of the device.
Figure 12. Power Supply Bypass.
RXCAP0
V
CC
_RXTTL
V
CC
_RXTTL
GND_TXHS
TOP VIEW
GND_RXTTL
GND_TXTTL
V
CC
_TXTTL
V
CC
_TXTTL
GND_TXTTL
GND_TXA
TXCAP0
V
CC
_TXHS
V
CC
_TXECL
V
CC
_TX
GND
V
CC
_RX
GND_RXHS
V
CC
_RXHS
V
CC
_RXHS
GND_RXA
V
CC
_RXA
RXCAP1
* SUPPLY VOLTAGE INTO V
CC
_RXA AND V
CC
_TXA SHOULD
BE FROM A LOW NOISE SOURCE. ALL BYPASS CAPACITORS
ARE 0.1 µF. THE PLL FILTER CAPACITORS ARE 0.01 µF.
V
CC
_TXA
GND
V
CC
V
CC
V
CC
V
CC
*
V
CC
V
CC
V
CC
GND_RXTTL
TXCAP0
V
CC
_TX
GND
V
CC
_RX
GND_RXTTL
V
CC
_RXTTL
V
CC
_RX
V
CC
C
PLLT
V
CC
* V
CC
V
CC
V
CC
V
CC
C
PLLR
Transceiver Power
Supply Bypass and Loop
Filter Capacitors
Bypass capacitors should be
liberally used and placed as close
as possible to the appropriate
power supply pins of the HDMP-
1526 as shown on the schematic
of Figure 11. All bypass chip
capacitors are 0.1 µF. The
VCC_RXA and VCC_TXA pins are
the analog power supply pins for
the PLL sections. The voltage into
these pins should be clean with
minimum noise. The PLL loop
filter capacitors and their pin
locations are also shown on
Figure 11. Notice that only two
capacitors are required: CPLLT for
the transmitter and CPLLR for the
receiver. Nominal capacitance is
0.01 µF. The voltage across the
capacitors is on the order of 1
volt, so the capacitor can be a
low voltage type and physically
small. The PLL capacitors are
placed physically close to the
appropriate pins on the HDMP-
1526. Keeping the lines short will
prevent them from picking up
stray noise from surrounding
lines or components.
COPPER HEATSINK NICKEL PLATING
CERAMIC
LEAD
DIE
WIRE BOND
Figure 13. Package Cross Section of HDMP-1526.
695
EDQuad Package Information
Item Details
Package Material Plastic (with copper heat slug)
Lead Finish Material 85% Tin, 15% Lead
Lead Finish Thickness 300-800 µm
Lead Coplanarity 0.10 mm max
Mechanical Dimensions
Assembly Handling
Information
Caution: Parts must be kept in
dry pack, or baked out before IR
reflow. Refer to package moisture
label for more details.
Figure 14. Mechanical Dimensions of HDMP-1526.
14.00
± 0.10
17.20
± 0.25
PIN #1 ID
14.00 ± 0.10
17.20 ± 0.25
0.35
± 0.05
0.17 MAX.
0.88 ± 0.15
2.00 ± 0.10
0.25 MAX.
0.80 BASIC
ALL DIMENSIONS ARE IN MILLIMETERS.
0.25
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
HDMP-1526
TOP VIEW
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1617 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
2.35 MAX.
