zk i ae a cw Ld _ Features 0.8-micron BICMOS for high per- formance High-speed access 15 ns (commercial) 25 ns (military) Automatic power-down Fully asynchronous operation Master /Slave select pin allows bus width expansion to 16/18 bits or more e Busy arbitration scheme provided CYPRESS SEMICONDUCTOR ULE D MM 2589bbe2 0006390 2 EACYP TU -2 3-17 PRELIMINARY CY7B144 CY7B145 Functional Description The CY7B144 and CY7B145 are high- speed BICMOS 8K x8 and 8K x9 dual-port static RAMs, Various arbitration schemes are included on the CY7B144/5 to handle situations when multiple processors access the same piece of data. Two ports are pro- vided permitting independent, asynchro- nous access for reads and writes to any lo- cation in memory. The CY7B144/5 can be utilized as a standalone 64-Kbit dual-port staticRAM or multiple devicescan be com- bined in order to function as a 16/18-bit or CYPRESS SEMICONDUCTOR 8K x 8/9 Dual-Port Static RAM with Sem, Int, Busy Each port has independent control pins: chip enable ), read or write enable ,and output enable (OB). Two flags, BUSY and INT, are provided on each port. BUSY signals that the port is trying to ac- cess the same location currently being ac- cessed by the other port. The interrupt flag (INT) permits communication between ports or systems by means of mail box or message center. The semaphores are used to pass a flag, or token, from one port to the other to indicate thata shared resource isinuse. The semaphore logiciscomprised of eight shared latches, Only one side can Semaphores included to permit soft- wider master/slave dual-port static RAM. : ware handshaking between ports An M/S pin is provided for implementing contrat ee ren cone ore) at any tine. e INT flag for port-to-port communica- _16/18-bit or wider memory applications shared resource is in use. An automatic tion without the need for separate master and pj ower-down featureiscontrolledindepen- Available in 68-pin LCC/PLCC/PGA slave devices or additional discrete logic. dently on each port by a chip enable (cE) \ Application areas include interprocessor/ yin or SEM pin TTL compatible multiprocessor designs, communications P pin. . status buffering, and dual-port video/ The CY7B144 and CY7B145 are available graphics memory. in 68-pin LCCs, PLCCs, and PGAs. Logic Block Diagram AW, a, Ue CEA OE, OER Av Aza Ato. Aton (78145) WO, Yaa (78145) Von : YOra Woo. : Oon Busy! BUsyAl!4 Aa. Aa Aa Aon INTERRUPT SEMAPHORE ARBITRATION SEM, SEN, INTL IRTRe! Bi44-1 MS Notes; 1. BUSY is an output in master mode and an input in slave mode. 2, Master: push-pull output and requires no pull-up resistor. 2-128CVE SEMICONDUCTOR UE D Ml 2589662 0006391 4 emcyp YPRESS SSS Boss PRELIMINARY CY7B145 SS SEMICONDUCTOR : T 46 23-12 . Pin Configurations . 68-Pin PGA . 7 : 68-Pin LCC/PLCC Top View : Top View = al a8 = 119] 116) 116] 144] 1412] 110f +03] 106} 104 - 69 Ga wWoo8addd gaoc Ast | An [ Aa. | Ao. [BUSY MIS | NTR | Ain | Aga wo ee pis 222 oC OSL SE Wai} 120] 117f 115) 113] i114] 109] to7{ tos] 103] 102 76 32 66 65 64 iT o An | Aa | Ax | Aww | INTL | OND IBUSYH Aon | Aca | Aan | Asa Woz. 009 As. = YOu 506 Ag < izaf 122 100} tot VOs, 58 Ag. Pa fou | AaL Arm | Aen WOs, 874 Aa wo 125[ 124 sal 99 GND 569 Ait Attu | Ato. Aan | Aen YOg. 855 Aa 127] 126 e6| 97 id 549 iL Veo | Ara. Anta | Ator ce 53 BUSY, GND 529 GND 29] 128 94 95 . Wor 51 MS NG } NGC 78144/5 GND | Aizr Orn 809 BUSY, 431] 190 2] 93 YOzn 499 Nia SEM.) CE, nc | NC Won 489 Aon A 475 Aw oe. Ra, st, a, VOan 465 Aan Lh tL at A YOsq 45 Aan 135] 194 68] 89 YOen P 26 449 Aun WOo. | NCU Op | RAV, 27 28 29 30.31 92 93 34 95 26 97 38 99 40 41 42.43 136 69 7 3 78 7 79 8t a3 86 a7 = & WwEONEeeae ec YOr | VOa. | Oa, | GND | VOn| GND | YOtR| Veo | VOsa | 07_ | NCE! gis eR 226 Se ECS ff 7O) 72 74] 76] ze] sol sa] sal as Notes: B144-3 "Oat | WOst | VOs. | Veo | Oor | VOza | Ora | VOsa | YOsR Ai44-2 3. I/Ogr on the CY7B145, 4. W/Ogr.on the CY7B145, Pin Definitions Left Port Right Port Description V/Oo.71(81) V/Oor-7R(8R) Data bus Input/Output AoL12L Aor-12R AddressLines CE, CER Chip Enable OEL OER Output Enable R/W, R/Wp Read/Write Enable SEM, SEMR SemaphoreEnable. When asserted LOW, allows accessto eightsemaphores, The three least significant bits of the address lines will determine whichsema- hore to write or read. The 1/Opg pin is used when writing to a semaphore. emaphoresare requested by writing a 0 into the respective location. INT, INTR InterruptFlag. INT, issetwhen rightport writes location 1FFEandiscleared when left port teads location 1FFE. INTp is setwhen left portwrites location 1FFF and is cleared when right port reads location LEFF. BUSY, BUSYR Busy Flag MS Master or Slave Select Vec Power GND Ground Selection Guide 7B144~15 TB144~25 TB144~35 7B145-15 7B145~25 7B145~35 Maximum Access Time (ns) : 15 25 35 Maximum Operating Commercial 260 220 210 Current(mA) Military 280 250 MaximumSt andby Commercial 90 75 70 Current for Ispi (mA) Military "80 5 2-129CYPRESS SEMICONDUCTOR | 4bE D MM 2589662 0006392 & EACYP == CY7B144 Ses CYPRESS PRELIMINARY CY7B145 SS & SEMICONDUCTOR 2 =_= Maximum Ratings T-46-23- . (Abovewhich the useful life may be impaired. Foruserguidelines, Static Discharge Voltage ..........+eeeeesereeses >2001V nottested.) (per MIL-STD-883, Method 3015) Storage Temperature ........ vececneees = 65Cto +150C Latch-UpCurrent ........sssereeaceserenereens >200 mA Ambient Temperaturewith : : . PowerApplicd ..scscseeeees busecueees _ =55Cto 125C Operating Range = : _ - bient Supply Voltage to Ground Potential......... 0.5V to +7,0V Range Temperature Veo DC Voltage Applied to Outputs : = > in High ZState ......0.eeeeeees beaneees . -0.5t0+7.0V | Commercial 0C to +70C SV = 10% DC Input Voltage) oo... cee eee rece =35Vto+7,0V | Industrial 40C to +85C 5V + 10% Output Current into Outputs(LOW) .......0eee vevee 20MA Military] ~55Cto 125C SV = 10% Electrical Characteristics Over the Operating Ranged] 7B144-15 | 7B14425 | 7B144-35 7B145-15 | 7B145-25 | 7B14535 Parameter Description Test Conditions Min. | Max. | Min. | Max. | Min, | Max. | Unit Vou Output HIGH Voltage Vcc = Min., Ion = 4.0mA 2.4 2.4 2.4 Vv Vo. Output LOW Voltage Vec = Min., Ion = 4.0mA 0.4 0.4 0.4 Vv Vint Input HIGH Voltage 2.2 2.2 2.2 Vv Vit Input LOW Voltage 0.8 0.8 08 | V Ix Input Leakage Current GND < Vi < Vcc -10 | +10 | 10 | +10 | -10 |] +10 | pA loz Output LeakageCurrent | Outputs Disabled, GND < Vo < Vcc | 10 | +10 | ~10 | +10 | -10 } +10 | pA Ioc OperatingCurrent Vec= Max, Com! 260 220 210 | mA lout = 9 - Outputs Disabled Mil/Ind 280 250 Isp Standby Current CE, and GFR > Van Comt 90 5 70 | mA (Both Ports TTL Levels) | f= fax' Milind 7) 75 Isna Standby Current CE, or CER > Vin Comt 160 140 130 | mA (One Port TIL Level) f= fyaxl Milind 150 160 Isp3 Standby Current Both Ports Com'l 15 15 15 | mA (Both Ports CMOS Levels) oa and CER 2% 0.29, In2 cc ~ . i orvin c2v,f=ol8) | Mivand 30 30 Isp Standby Current One Port_ Com! 140 120 110 | mA (One Port CMOS Level) | CELorCER > Vceco 0.2V, Vin = Vcc 0.2V or - Vin <.0.2V, Active Mil/Ind 150 130 Port Outputs, f = fyax!l Capacitancell Parameters Description Test Conditions Max, Unit Cin InputCapacitance Ta = 25C, = 1 MHz, 10 pF Cout Output Capacitance. Vec = 5.0V 15 pF Notes: 5, Pulse width < 20 ns, * 8. fax = ltrc = Allinputs cycling at f = 1/tac (except output enable). 6. Tais the instant on case temperature, 7, Seethe last page of this specification for Group A subgroup testing in- formation. 9. 2-130 f = 0 means no address or control lines change. This applies only to inputs at CMOS level standby Isp3. Tested initially and after any design or process changes that may affect these parameters. noeYPRESS SEMICONDUCTOR =sailieges CY7B144 SS 2S ercs PRELIMINARY CY7B145 SS SEMICONDUCTOR AC Test Loads and Waveforms T-46-23. 12 BV : BV Al = 6930 Rr = 2502 Rt = 8992 OUTPUT OUTPUT OUTPUT C= 380 pF R2=3470 enor T G=5pF A2.= 3470 4 = = Vier = 1.4V 1 = (a) Normal Load (Load 1) (b) Thvenin Equivalent (Load 1) (c) Three-State Delay (Load 3) B1444 Bi44-5 ; Bt44-6 ALLINPUT PULSES OUTPUT . L C= 380 pF Load (Load 2) BI44-7 B144-8 Switching Characteristics Overthe Operating Rangel!0.11] . 7B14415 7B14425 7B144~35 TB14515 7B14525 7B145-35 Parameters Description Min, [| Max. | Min. | Max. | Min. | Max. Units READ CYCLE tre Read Cycle Time 15 25 35 ns tan Address to Data Validl!21 15 | 25 35 ns toHA Output Hold From AddressChange 3 3 3 ns tace CE LOW to Data Validli2] 15 25 35 ns tbor OE LOW to Data Validli2] 10 15 20 ns trzont3) OE Low to Low Z 3 3 3 ns tuzogl3) OE HIGH to High Z. 10 15 20 ns trzcel!s} CE LOW to Low Z 3 3 3 ns tyzcEl!3] CE HIGH to High Z 10 15 20 ns teu CE LOW to Power-Up 0 0 i) ns tpp CE HIGH to Power-Down 15 25 35 ns WRITE CYCLE twe Write Cycle Time 15 25 35 ns tscr CE LOW to Write End 12 20 30 ns taw Address Set-Up to Write End 12 20 30 ns tHa Address Hold From Write End 2 2 2 us tsa Address Set-Up to Write Start 0 0 0 ns tpwe Write Pulse Width 12 20 25 ns tsp Data Set-Up to Write End 10 15 15 ns typ Data Hold From Write End 0 0 0 ns tuzweltsl R/W LOW to High Z 10 15 20 ns trzwel3] R/W HIGH to LowZ. 3 3 3 ns twpp Write Pulse to Data Delay 30 50 60 ns tppp Write Data Valid to Read Data Valid 25 30 35 ns 2-131 UbE D Ka 2S585bb2 0006393 & EACYP: SRAMs |_ rs CYPRESS SEMICONDUCTOR WBE D EM 254%bbe 0006394 T EaACYP 10. Seethe last page of this specification for Group A subgroup testing in- formation. 11. Test conditions assume signal transition time of 3 ns or less, timing ref- erence levels of 1.5V, input pulse levels of 0 to 3.0V, and outputloading of the specified Io1/Ior and 30 pF load capacitance. : 12, AC test conditions use Voy = 1.6V and Vor = 1.4V. 13, Test conditions used are Load 3. 14. Test conditions used are Load 2. 2-132 = CY7B144 = 4 PRELIMINARY ~ CY7B145 Sess | SEMICONDUCTOR ; Switching Characteristics Over the Operating Rangel!.11] (continued) T-46-23- 12 * 7Bi44-15 | 7B14425 | 7B14435 7B14515 7B14525 7B145-35 Parameters Description Min. | Max. | Min. | Max. | Min. | Max. Units BUSYTIMINGU4] tBLa BUSY LOW from Address Match 15 20 20 iis tpHa BUSY HIGH from AddressMismatch 15 20 20 ns tare BUSY LOW from CE LOW 15 20 20 ns tpHc BUSY HIGH from CE HIGH 15 20 20 ns tps Port Set-Up for Priority 5 5 5 ns twp WE LOW after BUSY LOW 0 0 0 ns tw WE HIGH after BUSY HIGH 13 20 30 ns tppp BUSY HIGH to Data Valid 15 25 35 ns | INTERRUPTTIMINGU4 tins INT Set Time 15 3 25 ns tinr INT Reset Time 15 25 25 ns SEMAPHORETIMING_. tsor SEM Flag Update Pulse (OE or SEM) 10 10 15 ns tswRD SEM Flag Write to Read Time 5 3 3 ns tsps SEM Flag Contention Window 3 5 5 ns Notes: -un SEM MICONDUCTOR ~23-12 Switching Waveforms T-46-23 Read Cycle No, 1[19, 20] Either Port Address Access \ lee . tac ADDRESS . taa h* toa > DATAOUT _ PREVIOUS DATA VALID KXXXX DATA VALID Bi44-11 Read Cycle No, 211% 18:19 : Either Port CE/OE Access SEM or GE SK Ww dE face et tizce a / t tHzoe _P lor +4 took . +# tizce y, : DATA OUT HELE DATA VALID + : P teu +- top lec I Isp Bi44-10 Read Timing with Port-to-Port Delay (M/S = L)l25: 16) be two ADDRESS, MATCH x PA, ____. }# we Kw . ep P HD DATAINA . f VALID . ADDRESS, xX MATCH nt topp 1 DATAgutL - VALID nt twop | Bie4-9 Notes; = 15. BUSY = HIGH for the writing port. . 19. R/W is HIGH for read cycle. 16, CE, = CER = LOW. 17. Address valid alid prior to or coincident with CE transition LOW. 18. CE, = L, SEM = Hwhen accessing RAM. CE = H, SEM = Lwhen accessingsemaphores. 20. Device is continuously selected CE = LOW and OH = LOW. This waveform cannot be used for semaphore reads. 2-133 S SEMICONDUCTOR 4bE dD 2e54%9bb2 0006395 1 Eecyp CY7B144 sense PRELIMINARY CY7B145 SRAMs -CYPRESS SEMICONDUCTOR 4BE D ma 258%bbe OO0b39b 3 MACYP CY7B144 PRELIMINARY CY7B145 Switching Waveforms (continued) Write Cycle No. 1: OE Three-State Data /Os (Either Port)(21: 22,24] two ADDRESS SEMOR je tsp T-46-23-12 =: DATA VALID | OE Uf x ' XY tHz0E . zor ->] SOOO HIGH IMPEDANCE TITITTT DATA OUT >>> REE Bi44-i2 Write Cycle No. 2: R/W Three-State Data I/Os (Either Port)(?1, 25, 24] two ADDRESS SEM OR CE DATA IN DATA OUT tsp tuo DATA VALID tizwe HIGH IMPEDANCE 6144-13 Notes: 21. The internal write time of the memory is defined by the overlap of CE or SEM LOW and R/W LOW. Both signals must be LOW to initiate awrite, and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. 3 22. If OF is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tpwe or (tyzwe + tsp) toallowthe YO 24. 2-134 drivers to turn off and data to be placed on the bus for the required tsp. If OF is HIGH during a R/W controlled write cycle (as in this ex- ample), this requirement does not apply and the write pulse can be as short as the specified tpwr. . Data I/O pins enter high impedance when OE is held LOW during write. R/W must be HIGH during all address transitions.CYPRESS SEMICONDUCTOR 4BE D 549bb2 0006397 5 Eacyp S~ CY7B144 =e PRELIMINARY CY7B145 ees SEMICONDUCTOR Switching Waveforms (continued) T-46 ~23-12 Semaphore Read After Write Timing, Either Sidel28] oo | taa | Kk torn o tote KX WERE KKK warrants NOOO fav > | tace SEM tHa | ce We | / tgp Og DATA-IN VALID DATA-OUTVAUD tsa mle trys -af HO RAW . NH tswan . tpog __- 8 LLMLLLLILL LLL LLL LLL oO / 4. WRITECYCLE ft#---. READ CYCLE Bi44-15 Semaphore Contention(2>: 26, 27] Oe AguAat MATCH KK RAR SEM, tsps > Aon~Acn MATCH KX RW y o SEM, < a / B144-14 Notes: ae 25, WOor = VOot = LOW (request semaphore); CEp = CE, = HIGH 28, CH=HIGH forthe duration ofthe above timing (both write andread 26. Semaphores are reset (available to both ports) at cycle start. cycle). 27, If tsps is violated, the semaphore will definitely be obtained by one side or the other, but there is no guarantee which side will control the semaphore. 2-135 SRAMs aCYPRESS SEMICONDUCTOR HEE D ES 2549bbe 00Ub394 7 egcyP a CY7B144 ae PRELIMINARY CY7B145 Sass = SEMICONDUCTOR Switching Waveforms (continued) ee T-46-23-12 Read with BUSY (M/S=HIGH)I!6} I two ADDRESS, MATCH * RWa +. ewe sO " 7 - sp le tuo DATAINg f VALID * tbs ADDRESS, MATCH t, BLA et toa BUSY, + t BOD topo DATAguTL SK vauo ~ twop 6144-16 Write Timing with Busy Input (M/S=LOW) tewe RW t t B144-17 2-136CYPRESS SEMICONDUCTOR 4EE D MM 258%bb2 000639599 q Eacyp = CY7B144 a PRELIMINARY CY7B145 SF SRE wuctor Switching Waveforms (continued : 8 (Continged) T-46-23-12 Busy Timing Diagram No. 1 (CE Arbitration) 25! CE, Valid First: 4 ADDRESS, p x ADDRESS MATCH xX - SRAMs CE, _ tps -> CER ane | YK taic f- teyc BUSY, B144-20 CER Valid First: ADDRESS, p xX ADDRESS MATCH xX CER tpg > CE, taic i- tsua me =[ 6144-21 Busy Timing Diagram No. 2 (Address Arbitration)(29] Left Address Valid First: tac oF two ADDRESS, ADDRESS MATCH L ADDRESS MISMATCH KX jt tps ADDRESS, xX BUSY, B144-18 Right Address Valid First: tac or two ADDRESSR ADDRESS MATCH ADDRESS MISMATCH xX ADDRESS, xX tBLa < tBHA BUSY, Bt44-19 s Nate: 29. If tps is violated, the busy signal willbe asserted on one side or the oth- er, but there is no guarantee on which side BUSY will be asserted 31. tins or tinr depends on which enable pin (CEy, or R/Wy) is asserted ast, 30. tra depends on which enable pin (CE, or R/W_) is deasserted first, 2-137WbE D EM 258%9bbe 0006400 1 EECYP CY7B144 PRELIMINARY CY7B145 Switching Waveforms (continued) T~4 6~2 3 re Interrupt Timing Diagrams Left Side SetsINTR: ' WG ADDRESS, WRITE 1FFF xxx x CE, tral] N AL _ N INTR er bs h 8144-22 Right Side Clears INTR: poDRes SKKKEREREREEI mK tc OOr"7*7 RW J / / of p4 . Oia NS N N - Lf TTT Intra A B144-23 Right Side Sets INT; 7 . - two : ADDRESS, a WRITE 1FFE Kx x xX tna) <> SZ ta] > CER YR / r RWa \ . N 7 < INT, eek ~ Laer SK 8144-24 Left Side Clears INT, ADDRESSa READ 1FFE . .|)|.|lUt~~S / tall 7 LAYS J m - Bi44-25 2-138WBE D FE 258%bb2 OOOb4O1 3 EECYP CY7B144 PRELIMINARY CY7B145 CYPRESS SEMICONDUCTOR an, ; Bae T-46-23-12 SS SEMICONDUCTOR Architecture The CY7B144/S consists of a an array of 8K words of 8/9 bits each ofdual-port RAM cells, I/O and address lines, and control signals (CE, OF, R/W).These control pins permit independentaccess for reads or writes to any location in memory, To handlesimultaneous writes/reads to the same location, a BUSY pin is provided on each port. Twointerrupt (INT) pins canbe utilized forport-to-portcom- munication. Two semaphore (SEM) control pins are used for alfo- cating shared resources, With the M/S pin, the CY7B144/5 can functionas a Master (BUSY pins are outputs) or asa slave (BUSY pins are inputs), The CY7B144/5 has an automatic power-down featurecontrolled by CE, Each port isprovided with its own output enable control (OE), which allows data to be read from the device. Functional Description Write Operation Data must be set up for a duration of tsp before the rising edgeof R/W in order to guarantee a valid write. A write operation is con- trolfed by cither the OE pin (see Write Cycle No.1 waveform) or the R/W pin (see Write Cycle No. 2waveform), Datacanbewritten to the device tyzoR after the OE is deasserted or tyyzwe after the falling edge of R/W. Required inputs for non-contention opera- tions are summarized in Table 1, Ifa location is being written to by one port and the opposite port attempts to read that location, a port-to-port flowthrough delay must be met before the data is read on the output, Data will be val- id on the port wishing fo read the location tppp after the data is presentedon the other port. Read Operation When reading the device, the user must assert both the OE and CE pins. Data will be available tacg after CE or tpog after OF are as- serted, If the user of the CY7B144/5 wishes fo access a semaphore flag, then the SEM pin must be asserted instead of the CE pin. Interrupts The interrupt flag (INT) permits communications between ports. Whenthe left port writes to location 1FFF, the right portsin- terrupt flag (INTR) is set. This flag is cleared when the right part reads that same location. Setting the left ports interrupt flag (INT; is accomplished when the right port writes to location 1FFE. This flagis cleared when the left port reads location 1FFE, Themessage at IFFF or 1FFE is user-defined. See Table 2 for input require- ments for INT. INT and INT{ are push-pull outputs and do not requirepull-up resistors to operate. Busy - The CY7B144/5 provides on-chip arbitration to alleviate simulta- neousmemory location access (contention). Ifboth ports CEs are asserted or an address match occurs within tps of each other the Busy logic will determine which port has access, If tps is violated, one port will definitely gain permission to the location, but itis not guaranteed which one. BUSY will be asserted tar after an ad- dress match or tpic after CE is taken LOW. BUSY, and BUSYz in master mode are push-pull outputs and do not require pull-up resistorsto operate. Master/Slave AnM pin is provided in order to expand the word width by confi- guring the device as cither a master or aslave. The BUSY output of the master is connected to the BUSY input of the slave. This will allow the device to interface ta a master device with no external components. Wtiting of slave devices must be delayed until after the BUSY input has settled, Otherwise, the slave chip may begin a write cycle during a contention situation. When presented a HIGH input, the M/S pin allows the device to be used as a master and therefore the BUSY line is an output. BUSY can then be used to send the arbitration outcome to a slave. Semaphore Operation The CY7B144/S provides eight semaphore latches which are sepa- rate from the dual-portmemory locations.Semaphores are used to reserveresources that are shared between the two ports. The state. ofthe semaphore indicates that a resource isin use, Forexample, if the left port wants to requesta given resource, itsetsa latch by writ- inga 0 to a semaphore location. The left port then verifies its suc- cess in setting the latch by reading it. After writing to the sema- phore, SEM or OE must be deasserted for tsop before attempting to read the semaphore. The semaphore value will be available tswrp + inog after the rising edge of the semaphore write. Ifthe left port. was successful (reads a 0), it assumes control over the shared resource, otherwise (reads a 1) it assumes the right port has control and continues to poll the semaphore. When the right side hasrelinquished control of the semaphore (by writing a 1), the left sidewill succeed in gaining control ofthesemaphore. Iftheleftside no longer requires the semaphore, a 1 is written to cancel its re- quest. Semaphores are accessed by asserting SEM LOW. The SEM pin functionsas a chip enable for the semaphore latches (CE must re- main HIGH during SEM LOW). Ag-2 represents the semaphore address. OF and RAW are used in the same manner as a normal memory access, When writing or reading a semaphore, the other address pins have no effect. When writing to the semaphore, only I/Op is used. Ifa 0 is written tothe left port ofan unused semaphore, a 1 will appear at the same Semaphoreaddresson the right port. Thatsemaphore cannowonly bemodified by the side showing 0 (the left port in this case). Ifthe left port now relinquishes control by writing a 1 to the semaphore, the semaphore will be set to 1 for both sides. However, if the right port had requested the semaphore (written a0) while the left port had control, the right port would immediately own the semaphore assoonas the left port released it, Table 3showssamplesemaphore operations, When reading a semaphore, all eight data lines output the sema- phore value, The read value is latched in an output register to pre- vent the semaphore from changing state during a write from the other port. If both ports attempt to access the semaphore within tsps ofeach other, the semaphorewill definitely be obtainedbyone side or the other, but there is no guarantee which side will control thesemaphore. Table 1. Non-Contending Read/Write Inputs Outputs CE | R/W| OE ]SEM[ 1/0o-7 Operation H | X x H | HighZ Power-Down H | HI] L | L |Dataout Senapain xX | X | H X |HighZ V/O lines Disabled H |] fr] xX L | DataIn Write to Semaphore Ly;H{L H | DataOut Read L L/ x H {DataIn Write LY xX] x L HlegalCondition 2-139 SRAMs aCYPRESS SEMICONDUCTOR WBE D MM 2546%bb2 OO0b40e S EECYP. =i ae 46-23-12 PRELIMINARY CY7B145 SS SEMICONDUCTOR Table 2, Interrupt Operation Example (assumes BUSY, =BUSYp=HIGH) Left Port Right Port Function Ao-12 IFFE Xx x L x x L Table 3. Semaphore Operation Example Yoo | yoo Function Left Status 1 1 Left port 1 Left port obtains 1 access Left port 1to portis granted access tosemaphore port Oto No Left port is access port semaphore port Ito Noport port writes 0 port Noportaccessing port Oto Left port port ito port accessing Ordering Information Speed Package | Operating Speed Package | Operating (ns) Ordering Code Type Range (ns) Ordering Code Type Range 15 CY7B144~15GC G68 Commercial 15 CY7B145-15GC G68 Commercial CY7B144-15]C J81 CY7B14515IC J81 CY7B144-15LC L81 CY7B145-15LC L81 25 CY7Bi4425GC G68 Commercial 25 CY7B14525GC G68 Commercial CY7B14425]C J81 CY7B14525JC I8t CY7B14425LC L81 CY7B14525LC L81 CY7Bi4425JE 381 Industrial _ CY7B145--2551 J81 Industrial CY7B144--25GMB G68 Military CY7B145-25GMB G68 Military CY7Bi44--25LMB L81 CY7B14525LMB L81 35 CY7B144-35GC G68 Commercial 35 CY7B145--35GC G68 Commercial CY7B144355C J81 CY7B145353C J8i CY7B144-35LC L8i CY7B14535LC L8i CY7B1443531 J8i Industrial CY7Bi453551 J81 Industrial CY7B14435GMB G68 Military CY7B14535GMB G68 Military CY7B144-35LMB L81 CY7B145-35LMB L81 2-140CYPRESS SEMICONDUCTOR = = SS. ;, ULE D MM 254%bbe OOOb4OS 7 EmcyPp St 5 Cirenss PRELIMINARY =S >" SEMICONDUCTOR MILITARY SPECIFICATIONS T-46-23-12 Group A Subgroup Testing fe DC Characteristics Switching Characteristics Parameters Subgroups Parameters | Subgroups Vou 1, 2,3 READ CYCLE VoL 1,2,3 tre 7, 8, 9, 10, 11 Vint 1,2,3 taa 7, 8, 9, 10, 14 Vir Max. 1,2,3 toHA 7, 8, 9, 10, 11 Ix 1,2,3 tAcE 7,8, 9, 10, 11 Ioz 1,2,3 tpoE 7, 8,9, 10, 11 Tos 1,2,3 WRITE. CYCLE Toc 123 two 7,8, 9, 10, 11 Tsp 1,2,3 tscr 7, 8, 9, 10, 14 Isp2 1,2,3 taw 7,8, 9, 10, 11 Isp 1,2,3 tra 7,8, 9, 10, 11 Tspa 1,2,3 tsa 7, 8, 9, 10, 11 tpwr 7, 8, 9, 10, 11 tsp 7, 8,9, 10, 11 tup 7, 8, 9, 10, 11 BUSYANTERRUPT TIMING tela 7,8, 9, 10, 11 taHa 7, 8, 9, 10, 11 tec 7, 8, 9, 10, 11 tgHc 7, 8,9, 10, 11 tps 7, 8, 9, 10, 11 tins 7, 8, 9, 10, 11 tinR 7, 8, 9, 10, 11 BUSY TIMING twa 7, 8, 9, 10, 11 twH 7,8, 9, 10, 11 tppp 7,8, 9, 10, 11 tppp 7, 8, 9,10, 11 twop 7, 8, 9, 10, 11 Document #: 38-00163-B 2~141 SRAMs a