Dual 3A/Single 6A Step-Down DC/DC Power Module ISL8203M Features The ISL8203M is an integrated step-down power module rated for dual 3A output current or 6A current sharing operation. Optimized for generating low output voltages down to 0.8V, the ISL8203M is ideal for any low power low-voltage applications. The supply voltage range is from 2.85V to 6V. The two channels are 180 out-of-phase for input RMS current and EMI reduction. Each channel is capable of 3A output current. They can be combined to form a single 6A output in current sharing mode. While in current sharing mode, the interleaving of the two channels reduces input and output voltage ripple. * Dual 3A and single 6A switching power supply The ISL8203M offers an independent power-good (PG) signal for each channel. When shut down, the ISL8203M discharges the output capacitor. Other features include internal digital soft-start, enable for power sequence, overcurrent protection and over-temperature protection. The ISL8203M integrates a PWM controller, synchronous switching MOSFETs, inductors and passive components to maximize efficiency and minimize external component count. The ISL8203M is available in a thermally-enhanced, compact QFN package. * High efficiency, up to 95% * Input voltage range: 2.85V to 6V * Output voltage range: 0.8V to 5V * Internal digital soft-start: 1.5ms * External synchronization up to 4MHz * Compact size: 9.0mmx6.5mmx1.83mm * Peak current limiting and hiccup mode short circuit protection * Overcurrent protection Applications * C/P, FPGA and DSP power * Plug-in DC/DC modules for routers and switchers * Test and measurement systems * Bar code reader Related Literature * AN1941, "ISL8203MEVAL2Z Dual 3A/single 6A Evaluation Board Set-Up Procedure" INPUT 2.85V to 6V OUTPUT1 1.5V/3A VIN1 CIN VOUT1 1800pF VIN2 100k COUT1 FB1 VDD 113k EN1 EN2 SGND ISL8203M OUTPUT2 1.8V/3A SS MODULE TOP VOUT2 SYNC 1800pF 100k COUT2 PG1 FB2 PG2 80.6k PGND SGND MODULE BOTTOM FIGURE 1. TYPICAL APPLICATION CIRCUIT - DUAL 3A July 23, 2014 FN8661.1 1 FIGURE 2. SMALL FOOTPRINT PACKAGE WITH LOW PROFILE CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2014. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. ISL8203M COMP SS RC NETWORK SOFT START SHUTDOWN VIN1 SHUTDOWN EN1 BANDGAP REFERENCE 0.8V + EAMP 3pF FB1 1F PWM LOGIC CONTROLLER PROTECTION DRIVER + COMP 1H VOUT1 SW1 PGND SLOPE COMP 1.6k + + CSA1 PGOOD COMPARATORS VIN1 1M PG1 SYNC OSCILLATOR 1ms DELAY SGND SHUTDOWN THERMAL SHUTDOWN SS OCP THRESHOLD LOGIC RC NETWORK SOFT START SHUTDOWN VIN2 SHUTDOWN EN2 BANDGAP REFERENCE 0.8V + EAMP + COMP 3pF FB2 SLOPE COMP 1F PWM LOGIC CONTROLLER PROTECTION DRIVER 1H VOUT2 SW2 PGND + 1.6k + CSA2 PGOOD COMPARATORS VIN2 PG2 1ms DELAY SGND FIGURE 3. INTERNAL BLOCK DIAGRAM Submit Document Feedback 2 FN8661.1 July 23, 2014 ISL8203M Pin Configuration ISL8203M (23 LD QFN) TOP VIEW VOUT1 6 SW1 5 PGND 4 VIN1 VDD SS 2 1 3 22 EN1 21 SYNC 20 PG1 19 NC 18 FB1 17 COMP 23 16 7 VOUT2 8 SW2 9 PGND 10 VIN2 11 12 EN2 PG2 NC 15 NC 14 FB2 13 NC Pin Descriptions PIN NUMBER SYMBOL DESCRIPTION 1 SS Soft-start pin. SS is used to adjust the soft-start time. For dual-output mode, tie SS pin to VIN directly and the soft-start time is fixed at 1.5ms. SS pin is tied to CSS only in parallel mode operation, with external compensation. In parallel mode, connect a capacitor CSS from SS to SGND to adjust the soft-start time. CSS should not be larger than 33nF. This capacitor, along with an internal 5A current source sets the soft-start time, (refer to Equation 2). 2 VDD 3, 10 VIN1, VIN2 4, 9 PGND 5, 8 SW1, SW2 6, 7 VOUT1, VOUT2 22, 11 EN1, EN2 Power enable pins. The output is enabled when the respective ENABLE pin is driven to high. The output is shut down and output capacitors discharged when the respective ENABLE pin is driven to low. Typically, tie to VIN pin directly. Do not leave this pin floating. 20, 12 PG1, PG2 Power-good pins. At power-up or EN HI, this output is a 1ms delayed Power-Good signal for the output voltage. 13, 15, 16, 19 NC No Connection pins. These pins have no connections inside. Leave these pins floating. 14 FB2 Voltage setting pin. The output voltage VOUT2 is set by an external resistor divider connected to FB2. Refer to "Programming the Output Voltage" on page 12. 17 COMP 18 FB1 Submit Document Feedback Input voltage for internal control circuit. Tie VDD directly to VIN1. VDD should be at the same potential as the input voltage. Power inputs. Input voltage range: 2.85V to 6V. Tie directly to the input rail. Input ceramic capacitors are needed between these two pins and PGND. Power ground. Power ground pins for both input and output returns. Switching node. Use for monitoring switching frequency. Switching nodes should be floating or used for snubber connections. Power Output. Apply output load between these pins and PGND pins. Output voltage range: 0.8V to 5V. Compensation pin. Typically floating for dual-output mode. For dual output operation, internal compensation networks are implemented for stable operation in the full range of I/O conditions. For parallel mode operation, external compensation is required. Refer to "Output Current Sharing" on page 11. Voltage setting pin. The output voltage VOUT1 is set by an external resistor divider connected to FB1. Refer to "Programming the Output Voltage" on page 12. 3 FN8661.1 July 23, 2014 ISL8203M Pin Descriptions (Continued) PIN NUMBER SYMBOL DESCRIPTION 21 SYNC Synchronization pin. Connect to logic high or input voltage VIN for non-use. Connect to an external function generator for external Synchronization. Negative edge trigger. Do not leave this pin floating. Do not tie this pin low (or to PGND). 23 SGND Control signal ground. Connect to PGND under the module on the top layer. Make sure to have only two connect locations between SGND and PGND to avoid noise coupling. See "PCB Layout Recommendation" on page 14. Ordering Information PART NUMBER (Notes 2, 3) PART MARKING ISL8203MIRZ (Note 1) ISL8203M ISL8203MEVAL2Z Evaluation Board TEMP. RANGE (C) -40 to +85 PACKAGE (Pb-free) 23 Ld QFN PKG. DWG. # L23.6.5x9 NOTES: 1. Add "-T*" suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL8203M. For more information on MSL, please see Technical Brief TB363. Submit Document Feedback 4 FN8661.1 July 23, 2014 ISL8203M Absolute Maximum Ratings (Reference to SGND) VIN1, VIN2, VDD . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V (DC) or 7V (20ms) SW1, SW2 . . . . . . . . . . . -3V/(10ns)/-1.5V (100ns)/-0.3V (DC) to 6.5V (DC) or . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V (20ms)/8.5V(10ns) EN1, EN2, PG1, PG2, SYNC, SS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V FB1, FB2, COMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.7V ESD Ratings Human Body Model (Tested per JESD22-A114) . . . . . . . . . . . . . . . .1.5kV Charged Device Model (Tested per JESD22-C101E). . . . . . . . . . . . . . 1kV Latch Up (Tested per JESD-78A; Class 2, Level A) . . . . . . . . . . . . . . 100mA Thermal Information Thermal Resistance (Typical) JA (C/W) JC (C/W) 23 Ld QFN (Notes 4, 5) . . . . . . . . . . . . . . 15 2 Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-40C to +125C Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-55C to +150C Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . -40C to +85C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493 Recommended Operating Conditions VIN Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.85V to 6V Output Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.8V to 5V Load Current Range per Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . 0A to 3A Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . -40C to +85C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 4. JA is measured in free air with the component mounted on the ISL8203MEVAL2Z evaluation board with "direct attach" features. See Tech Brief TB379. 5. For JC, "case temperature" location is at the center of the exposed metal pad on the package underside. Electrical Specifications Unless otherwise noted, the typical specifications are measured at the following conditions: TA = +25C, VOUT = 1.2V. Boldface limits apply over internal junction temperature range, -40C to +125C. PARAMETER SYMBOL TEST CONDITIONS MIN MAX (Note 6) TYP (Note 6) UNITS 2.5 V INPUT SUPPLY VIN Undervoltage Lock-out Threshold (Note 7) Input Supply Current (Note 7) VUVLO Rising Hysteresis IVIN 35 2.85 130 VIN = 6V, EN1 = EN2 = 0, no load mV 42 A OUTPUT REGULATION Output Continuous Current Range IOUT(DC) Line Regulation VIN = 5V, VOUT1 = 1.2V 0 3 A VIN = 5V, VOUT2 = 1.2V 0 3 A VIN = 5V, VOUT1 = 1.2V, in parallel mode 0 VOUT1/VOUT1 VIN = 2.85V to 6V, VOUT1 = 1.2V, no load VOUT2/VOUT2 VIN = 2.85V to 6V, VOUT2 = 1.2V, no load Load Regulation 6 0.25 0.25 % VIN = 2.85V to 6V, VOUT1 = 1.2V, IOUT1 = 3A 0.25 % VIN = 2.85V to 6V, VOUT2 = 1.2V, IOUT2 = 3A 0.25 % VOUT1/VOUT1 VIN = 5V, 2x22F ceramic output capacitor VOUT2/VOUT2 IOUT1 = 0A to 3A, VOUT1 = 1.2V IOUT2 = 0A to 3A, VOUT2 = 1.2V Output Voltage Accuracy Output Ripple Voltage VOUT FB1, FB2 Regulation Voltage (Note 7) VFB FB1, FB2 Bias Current (Note 7) IFB Soft-start Ramp Time Cycle (Note 7) Soft-start Charging Current (Note 7) Submit Document Feedback 5 1 % 1 % Over line/load/temperature range -1.5 1.5 % Over line/load/temperature/life range -2.0 2.0 % VIN = 5V, 3x22F ceramic output capacitor IOUT1 = 0A, VOUT1 = 1.2V 10 mVP-P IOUT2 = 0A, VOUT2 = 1.2V 10 mVP-P IOUT1 = 3A, VOUT1 = 1.2V 12 mVP-P IOUT2 = 3A, VOUT2 = 1.2V 12 mVP-P 0.8 V VFB = 0.75V 0.1 A SS = VDD ISS A % 1.5 4 5 ms 6 A FN8661.1 July 23, 2014 ISL8203M Electrical Specifications Unless otherwise noted, the typical specifications are measured at the following conditions: TA = +25C, VOUT = 1.2V. Boldface limits apply over internal junction temperature range, -40C to +125C. (Continued) PARAMETER MIN MAX (Note 6) TYP (Note 6) UNITS IOUT1 = 0A to 1.5A 35 mVP-P IOUT2 = 0A to 1.5A 35 mVP-P IOUT1 = 1.5A to 0A 45 mVP-P IOUT2 = 1.5A to 0A 45 mVP-P 17 Clock pulses SYMBOL TEST CONDITIONS VOUT-DP Current slew rate = 1A/s, VIN = 5V, VOUT = 1.2V, 3x22F ceramic output capacitor DYNAMIC CHARACTERISTICS Voltage Change for Positive Load Step Voltage Change for Negative Load Step VOUT-DP Current slew rate = 1A/s, VIN = 5V, VOUT = 1.2V, 3x22F ceramic output capacitor OVERCURRENT PROTECTION Dynamic Current Limit ON-time tOCON Dynamic Current Limit OFF-time tOCOFF 8 SS cycle Output Overcurrent Limit IOUT1 VIN = 5V, VOUT1 = 1.2V 4.8 A IOUT2 VIN = 5V, VOUT2 = 1.2V 4.8 A SW1, SW2 (Note 7) SW_ Maximum Duty Cycle 100 PWM Switching Frequency Synchronization Frequency Range (Note 8) fSw 0.85 fSYNC 2.64 Channel 1 to Channel 2 Phase Shift Rising edge to rising edge timing SW Minimum On Time SYNC = High (PWM mode) Soft Discharge Resistance RDIS EN = LOW 1.1 % 1.32 MHz 4 MHz 140 ns 124 0.32 V 0.1 A 180 80 100 PG1, PG2 (Note 7) Output Low Voltage Sinking 1mA, VFB = 0.7V PG Pin Leakage Current PG = VIN = 6V Internal PGOOD Threshold Percentage of nominal regulation voltage Delay Time (Rising Edge) Time from VOUT reached regulation 0.01 90 % 1 Internal PGOOD Delay Time (Falling Edge) 7 ms 15 s 0.4 V EN1, EN2, SYNC (Note 7) Logic Input Low Logic Input High 1.5 SYNC Logic Input Leakage Current Enable Logic Input Leakage Current V ISYNC Pulled up to 6V 0.1 1 A IEN Pulled up to 6V 0.1 1 A Thermal Shutdown 150 C Thermal Shutdown Hysteresis 25 C NOTES: 6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 7. Parameters with MIN and/or MAX limits are 100% tested for internal IC prior to module assembly, unless otherwise specified. Temperature limits established by characterization and are not production tested. 8. The operational frequency per switching channel is half of the SYNC frequency. Submit Document Feedback 6 FN8661.1 July 23, 2014 ISL8203M Typical Performance Characteristics Efficiency TA = +25C. 100 100 VOUT = 2.5V 95 EFFICIENCY (%) EFFICIENCY (%) 85 VOUT = 1.5V 80 VOUT = 1.2V 75 70 85 VOUT = 1.5V 80 VOUT = 1.2V 75 70 VOUT = 1V VOUT = 1V 65 65 60 60 0 0.5 1.0 1.5 2.0 LOAD CURRENT (A) 2.5 3.0 FIGURE 4. SINGLE CHANNEL, EN1 = HIGH, EN2 = LOW, VIN = 3.3V 0 0.5 1.0 1.5 2.0 LOAD CURRENT (A) 2.5 3.0 FIGURE 5. SINGLE CHANNEL, EN1 = HIGH, EN2 = LOW, VIN = 5V 100 100 95 VOUT = 2.5V VOUT = 2.5V 95 90 VOUT = 3.3V 90 EFFICIENCY (%) EFFICIENCY (%) VOUT = 3.3V 90 90 85 VOUT = 1V 80 VOUT = 1.5V 75 VOUT = 1.2V 70 85 80 VOUT = 1.5V VOUT = 1V 75 VOUT = 1.2V 70 65 60 VOUT = 2.5V 95 65 0 1 2 3 4 5 6 60 0 LOAD CURRENT (A) FIGURE 6. PARALLEL SINGLE OUTPUT, VIN = 3.3V Output Voltage Ripple 2 3 4 LOAD CURRENT (A) 5 6 FIGURE 7. SINGLE CHANNEL, VIN = 5V TA = +25C. 20mV/DIV 20mV/DIV 2s/DIV FIGURE 8. SINGLE CHANNEL, EN1 = HIGH, EN2 = LOW, VIN = 5V, VOUT = 1.5V, IOUT = 3A, COUT = 3x22F CERAMIC CAPACITORS Submit Document Feedback 1 7 2s/DIV FIGURE 9. PARALLEL SINGLE OUTPUT, VIN = 5V, VOUT = 1.5V, IOUT = 6A, COUT = 6x22F CERAMIC CAPACITORS FN8661.1 July 23, 2014 ISL8203M Typical Performance Characteristics (Continued) Load Transient Response TA = +25C. Load current step slew rate: 1A/s 50mV/DIV 50mV/DIV 50s/DIV 50s/DIV FIGURE 10. SINGLE CHANNEL, EN1 = HIGH, EN2 = LOW, VIN = 3.3V, VOUT = 1V, IOUT = 0A to 1.5A STEP, COUT = 3x22F CERAMIC CAPACITORS FIGURE 11. SINGLE CHANNEL, EN1 = HIGH, EN2 = LOW, VIN = 5V, VOUT = 1V, IOUT = 0A TO 1.5A STEP, COUT = 3x22F CERAMIC CAPACITORS 50mV/DIV 50mV/DIV 50s/DIV 50s/DIV FIGURE 12. SINGLE CHANNEL, EN1 = HIGH, EN2 = LOW, VIN = 5V, VOUT = 1.5V, IOUT = 0A to 1.5A STEP, COUT = 3x22F CERAMIC CAPACITORS FIGURE 13. SINGLE CHANNEL, EN1 = HIGH, EN2 = LOW, VIN = 5V, VOUT = 3.3V, IOUT = 0A TO 1.5A STEP, COUT = 3x22F CERAMIC CAPACITORS 50mV/DIV 50mV/DIV 50s/DIV FIGURE 14. PARALLEL SINGLE OUTPUT, VIN = 3.3V, VOUT = 1V, IOUT = 0A TO 1.5A STEP, COUT = 6x22F CERAMIC CAPACITORS Submit Document Feedback 8 50s/DIV FIGURE 15. PARALLEL SINGLE OUTPUT, VIN = 5V, VOUT = 1.2V, IOUT = 0A TO 1.5A STEP, COUT = 6x22F CERAMIC CAPACITORS FN8661.1 July 23, 2014 ISL8203M Typical Performance Characteristics (Continued) Start-Up TA = +25C VOUT 0.5V/DIV VOUT 0.5V/DIV PGOOD 5V/DIV PGOOD 5V/DIV IIN 2A/DIV IIN 1A/DIV 1ms/DIV 1ms/DIV FIGURE 16. SINGLE CHANNEL, EN1 = HIGH, EN2 = LOW, SOFT-START WITH 3A LOAD, VIN = 5V, VOUT1 = 1.2V, IOUT1 = 3A, COUT = 3x22F CERAMIC CAPACITORS, CIN = 100F + 22F CERAMIC CAPACITORS FIGURE 17. PARALLEL SINGLE OUTPUT, SOFT-START WITH 6A LOAD, VIN = 5V, VOUT = 1.2V, IOUT = 6A, CSS = 0.022F, COUT = 6x22F CERAMIC CAPACITORS, CIN = 100F + 22F CERAMIC CAPACITORS Short Circuit Protection TA = +25C, parallel single output mode, VIN = 5V, VOUT = 1.5V, IOUT = 6A, CIN = 100F+22F ceramic capacitors, COUT = 6x22F ceramic capacitors. VOUT 0.5V/DIV VOUT 0.5V/DIV SW1 2V/DIV SW1 2V/DIV IIN 2A/DIV IIN 2A/DIV 20s/DIV 10ms/DIV FIGURE 19. OUTPUT SHORT CIRCUIT PROTECTION, HICCUP MODE FIGURE 18. OUTPUT SHORT CIRCUIT PROTECTION VOUT 0.5V/DIV SW1 2V/DIV IIN 2A/DIV 5ms/DIV FIGURE 20. OUTPUT SHORT CIRCUIT RECOVERY FROM HICCUP Submit Document Feedback 9 FN8661.1 July 23, 2014 ISL8203M Typical Application Circuits INPUT 2.85V to 6V VIN1 CIN INPUT 2.85V to 6V OUTPUT1 1.5V/3A OUTPUT 1.5V/6A VIN1 VOUT1 1800pF VIN2 100k COUT1 CIN VOUT1 1800pF VIN2 COUT VDD VDD 113k 113k EN1 EN2 100k FB1 FB1 EN1 SGND SGND EN2 ISL8203M OUTPUT2 1.8V/3A SS SS VOUT2 SYNC 1800pF 100k PG1 COUT2 FB2 30.1k COMP PG2 80.6k PGND 270pF PGND SGND FIGURE 21. DUAL OUTPUT FOR 1.5V/3A AND 1.8V/3A FIGURE 22. PARALLEL SINGLE OUTPUT FOR 1.5V/6A INPUT 2.8V to 6V OUTPUT 1.2V/12A VIN1 CIN VOUT2 PG1 FB2 PG2 ISL8203M SYNC VOUT1 1800pF VIN2 100k COUT FB1 VDD 113k EN1 EN2 SGND ISL8203M SYNC SS VOUT2 FB2 PG1 30.1k COMP PG2 270pF PGND VOUT1 VIN1 VIN2 FB1 VDD EN1 EN2 SYNC SS SGND ISL8203M VOUT2 FB2 PG1 PG2 COMP PGND FIGURE 23. 4-PHASE PARALLEL SINGLE OUTPUT FOR 1.2V/12A NOTES: 9. Refer To "PCB Layout Recommendation" on page 14 For Shorting SGND To PGND. 10. Refer To "Output Current Sharing" on page 11 For External Compensation Components. Submit Document Feedback 10 FN8661.1 July 23, 2014 ISL8203M Functional Description PWM Control Scheme Each channel of the ISL8203M employs the current-mode pulse-width modulation (PWM) control scheme for fast transient response and pulse-by-pulse current limiting, as shown in the "Internal Block Diagram" on page 2 with waveforms in Figure 24. The current loop consists of the oscillator, the PWM comparator COMP, current sensing circuit, and the slope compensation for the current loop stability. The current sensing circuit consists of the resistance of the P-MOSFET when it is turned on and the current sense amplifier CSA1 (or CSA2 of Channel 2). The gain for the current sensing circuit is typically 0.2V/A. The control reference for the current loops comes from the error amplifier EAMP of the voltage loop. The PWM operation is initialized by the clock from the oscillator. The P-channel MOSFET is turned on at the beginning of a PWM cycle and the current in the MOSFET starts to ramp up. When the sum of the current amplifier CSA1 (or CSA2 of channel 2) and the compensation slope (0.46V/s) reaches the control reference of the current loop, the PWM comparator COMP sends a signal to the PWM logic to turn off the P-MOSFET and to turn on the N-channel MOSFET. The N-MOSFET stays on until the end of the PWM cycle. Figure 24 shows the typical operating waveforms during the PWM operation, where the dotted lines illustrate the sum of the compensation ramp and the current-sense amplifier output VCSA_, VEAMP represents the output of the error amplifier, and IL represents the inductor current. VEAMP VCSA1 indefinitely allowing 180 out-of-phase operation between the two channels. The switching frequency per channel is half of the external signal's frequency applied to the SYNC pin. The maximum external signal frequency is limited by the SW minimum on time (140ns MAX) requirement. The maximum external signal frequency can be calculated as shown in Equation 1. V OUT 1 1 --- f = f SW - MAX ---------------- ----------------V IN 140ns 2 SYNC - MAX (EQ. 1) where: * fSYNC-MAX is the maximum external signal frequency * fSW-MAX is the maximum switching frequency per channel * VOUT is the output voltage * VIN is the input voltage Output Current Sharing The ISL8203M's two channels can be paralleled for dual-phase operation in order to support a 6A output. In the parallel mode, the two channels are 180 out-of-phase, which reduces input and output voltage ripple and EMI. Connect the VOUT1 to VOUT2, FB1 to FB2, EN1 to EN2, PG1 to PG2, and connect a soft-start capacitor CSS from SS to SGND; refer to Figure 22. In parallel mode, external compensation network of a resistor and a capacitor is required with the typical values of 30.1k and 270pF; refer to Figure 22. Similar to the dual-phase operation, multiple modules can be paralleled for higher current capability. Connect all the modules' FB pins, COMP pins, SS pins, EN pins and PG pins; refer to Figure 23. Overcurrent Protection Duty Cycle IL VOUT FIGURE 24. PWM OPERATION WAVEFORMS The output voltage is regulated by controlling the reference voltage to the current loop. The bandgap circuit outputs a 0.8V reference voltage to the voltage control loop. The feedback signal comes from the FB pin. The soft-start circuitry only affects the operation during start-up and will be discussed separately; please refer to "Soft-Start" on page 12. The voltage loop is internally compensated for the dual output mode. For parallel current sharing mode, external compensation is required. Synchronization Control The frequency of operation can be synchronized up to 4MHz by an external signal applied to the SYNC pin. The 1st falling edge on the SYNC triggers the rising edge of the PWM ON pulse of Channel 1. The 2nd falling edge of the SYNC triggers the rising edge of the PWM ON pulse of Channel 2. This process alternates Submit Document Feedback 11 Current sense amplifiers CSA1 and CSA2 are used to monitor the two channels' internal inductor current respectively. The overcurrent protection is realized by monitoring the CSA output with the OCP threshold logic, as shown in Figure 2 on page 1. The current sensing circuit has a gain of 0.2V/A, from the P-MOSFET current to the CSA_ output. When the CSA1 output reaches the threshold, the OCP comparator is tripped to turn off the P-MOSFET immediately. The overcurrent function protects the module from a shorted output by monitoring the current flowing through the upper MOSFETs. Upon detection of an overcurrent condition, the upper MOSFET will be immediately turned off and will not be turned on again until the next switching cycle. Upon detection of the initial overcurrent condition, the Overcurrent Fault Counter is set to 1 and the Overcurrent Condition Flag is set from LOW to HIGH. If, on the subsequent cycle, another overcurrent condition is detected, the OC Fault Counter will be incremented. If there are 17 sequential OC fault detections, the module will shut down under an Overcurrent Fault Condition. An Overcurrent Fault Condition will result in the module attempting to restart in a hiccup mode with the delay between restarts being 8 soft-start periods. At the end of the eighth soft-start wait period, the fault counters are reset and soft-start is attempted again. If the overcurrent condition goes away prior to the OC Fault Counter reaching a count of four, the Overcurrent Condition Flag will set back to LOW. FN8661.1 July 23, 2014 ISL8203M If the negative current of the internal inductor reaches -2.5A, the module enters Negative Overcurrent Protection. At this point, all switching stops and the module enters tri-state mode while the pull-down MOSFET discharges the output until it reaches normal regulation voltage, then the module restarts. Power-Good There are two independent power-good signals for each of the two outputs via the FB pins. PG1 monitors the output Channel 1 and PG2 monitors the output Channel 2. When powering up, the open-collector Power-on Reset output holds low for about 1ms after VOUT reaches within 8% of the preset voltage. The PG pins do not require a pull-up resistor. UVLO (Undervoltage Lock-Out) When the input voltage is below the undervoltage lock-out (UVLO) threshold, the module is disabled. The maximum UVLO threshold is 2.85V. Enable The enable (EN) input allows the user to control the turning on or off of the module for purposes such as power-up sequencing. Each channel of the ISL8203M can be turned on or off independently through the EN pins. Once the module is enabled, there is typically a 600s delay for waking up the bandgap reference, then the soft start-up begins. Soft-Start The ISL8203M employs an internal digital soft-start circuitry which minimizes input inrush current during the start-up. The soft-start circuitry outputs a ramp reference to both the voltage loop and the current loop. The two ramps limit the inductor current rising speed as well as the output voltage rising speed so that the output voltage rises in a controlled fashion. At the beginning of the soft-start internal, when the voltage on the FB pin is less than 0.5V, the PWM oscillator frequency is forced to half of the normal frequency. During the soft-start, the module cannot sink current, behaving as in diode emulated mode for the soft-start time. If SS pin is tied to VIN, the soft-start time is an internally fixed 1.5ms. For parallel current sharing mode operation, connect a capacitor CSS from SS to SGND. CSS should not be larger than 33nF. This capacitor along with the internal current source of 5A sets the soft-start time tSS, which can be calculated as shown in Equation 2. (EQ. 2) t SS ms = 0.16 C SS nF Discharge Mode When a transition to shutdown mode occurs, or the output undervoltage fault latch is set, the module's output discharges to PGND through an internal 100 switch. Power MOSFETs The internal power MOSFETs are optimize for best efficiency. The ON-resistance for the P-MOSFET is typically 50m and the ON-resistance for the N-MOSFET is typically 50m. Submit Document Feedback 12 100% Duty Cycle Operation The ISL8203M offers 100% duty cycle operation. When the input voltage drops to a level that the ISL8203M can no longer maintain the regulation at the output, the module completely turns on the P-MOSFET. The maximum drop-out voltage under the 100% duty-cycle operation is the product of the load current and the ON-resistance of the P-MOSFET. Thermal Shutdown The ISL8203M offers built-in over-temperature protection. When the junction temperature reaches +150C, the module is completely shut down. As the temperature drops to +125C, the ISL8203M resumes operation by stepping through a soft-start. Applications Information Programming the Output Voltage The output voltage of the module is programmed by an external resistor divider between VOUT, FB, and SGND pins, as shown in Figure 21. The output voltage can be calculated as shown in Equation 3. R FBTOP VOUT = 0.8V 1 + ----------------------- R FBBOT (EQ. 3) Where: * RFBTOP is the top feedback resistor * RFBBOT is the bottom feedback resistor The top resistor is typically a 100k value, and a 1800pF capacitor is recommended to be connected in parallel. The value of the bottom resistor for different output voltages is shown in Table 1. TABLE 1. VALUE OF BOTTOM RESISTOR FOR DIFFERENT OUTPUT VOLTAGES (VOUT vs RFBBOT) RFBTOP (k) VOUT (V) RFBBOT (k) 100 0.8 open 100 1.0 402 100 1.2 200 100 1.5 113 100 1.8 80.6 100 2.5 47.5 100 3.3 32.4 Please note that the output voltage accuracy is also dependent on the resistor accuracy of RFBTOP and RFBBOT. The user needs to select high accuracy resistors (i.e., 0.5%) in order to achieve the overall output accuracy. Input Capacitor Selection Low Equivalent Series Resistance (ESR) ceramic capacitance is recommended to reduce input voltage ripple and decouple between the VIN and PGND of each channel. This capacitance reduces voltage ringing created by the switching current across FN8661.1 July 23, 2014 ISL8203M parasitic circuit elements. The ceramic capacitors should be placed as closely as possible to the module pins. A minimum of 22F ceramic capacitance for each channel is recommended. A bulk input capacitance may also be needed if the input source does not have enough output capacitance. A typical value of bulk input capacitor is 100F. In such conditions, this bulk input capacitance can supply the current during output load transient conditions. Output Capacitor Selection Ceramic capacitors are typically used as the output capacitors for the ISL8203M. A minimum output capacitance of 2x22F per phase is recommended. Bulk output capacitors that have adequately low Equivalent Series Resistance (ESR), such as low ESR polymer capacitors or a low ESR tantalum capacitor, may also be used in combination with the ceramic capacitors, depending on the output voltage ripple and transient requirements. thermal consideration for the module. The ISL8203M's thermally enhanced package offers typical junction to ambient thermal resistance JA of approximately 15C/W at natural convection (13C/W with 200LFM airflow) with a typical 4-layer PCB board. The derating curves (Figures 27 through 31) are derived from the maximum power dissipation allowed, while maintaining the junction temperature below a maximum junction temperature of +120C; the derating curves take into consideration the increased power dissipation at elevated ambient temperatures. The maximum +120C junction temperature is recommended for the module to load the current consistently and it provides the 5C margin of safety from the rated junction temperature of +125C. All the derating curves are obtained based on tests on the ISL8203MEVAL2Z evaluation board (Refer to AN1941, "ISL8203MEVAL2Z Dual 3A/Single 6A Evaluation Board Set-Up Procedure"). If necessary, the customer can adjust the margin of safety according to the real application. In the actual application, other heat sources and design margins should be considered. Thermal Consideration and Current Derating Experimental power loss data (Figures 25 and 26), along with JA from thermal modeling analysis, can be used as a guide for 3.0 3.0 2.5 2.5 POWER LOSS (S) POWER LOSS (S) Power Loss Curves 2.0 1.5 VOUT = 3.3V 1.0 VOUT = 1V 0.5 0 0 1 2 3 4 5 6 FIGURE 25. POWER LOSS AT VIN = 5V, PARALLEL SINGLE OUTPUT, TA = +25C 13 VOUT = 2.5V 1.5 1.0 VOUT = 1V 0.5 LOAD CURRENT (A) Submit Document Feedback 2.0 0 0 1 2 3 4 5 6 LOAD CURRENT (A) FIGURE 26. POWER LOSS AT VIN = 3.3V, PARALLEL SINGLE OUTPUT, TA = +25C FN8661.1 July 23, 2014 ISL8203M Derating Curves 7 7 200LFM 6 LOAD CURRENT (A) LOAD CURRENT (A) 6 5 4 0LFM 3 2 1 0 200LFM 5 4 0LFM 3 2 1 20 30 40 50 60 70 80 90 100 110 0 120 20 30 40 AMBIENT TEMPERATURE (C) 7 70 80 90 100 110 120 7 6 6 200LFM 200LFM LOAD CURRENT (A) LOAD CURRENT (A) 60 FIGURE 28. DERATING CURVES AT VIN = 5V, VOUT = 3.3V FIGURE 27. DERATING CURVES AT VIN = 5V, VOUT = 1V 5 4 0LFM 3 2 1 0 50 AMBIENT TEMPERATURE (C) 5 4 0LFM 3 2 1 20 30 40 50 60 70 80 90 100 110 120 AMBIENT TEMPERATURE (C) FIGURE 29. DERATING CURVES AT VIN = 3.3V, VOUT = 1V PCB Layout Recommendation To achieve stable operation, low losses, and good thermal performance, some layout considerations are necessary (Figure 31). * Use large copper areas for power path (VIN1, VIN2, SGND, PGND, VOUT1, VOUT2) to minimize conduction loss and thermal stress. Also, it is recommended to use multiple vias to connect the power planes in different layers. Use at least 5 vias on the SGND pad 23 connected to SGND plane(s) for the best thermal relief. * Use a separate SGND ground copper area for components connected to signal ground pins. Connect SGND pad 23 to PGND pin 4 at a single location and SGND pad 23 to PGND pin 9 at a single location. * The switching node of the module, the SW pins and the traces connected to the pins are very noisy. Keep these pads under the module. For noise sensitive applications, it is recommended to keep the SW pads only on the top and inner Submit Document Feedback 14 0 20 30 40 50 60 70 80 90 100 110 120 AMBIENT TEMPERATURE (C) FIGURE 30. DERATING CURVES AT VIN = 3.3V, VOUT = 2.5V layers of the PCB. Do not expose the SW pads to the outside on the bottom layer of the PCB. * Avoid routing noise-sensitive signal traces such as FB1, FB2, and COMP near the noisy SW pins. * The feedback network should be placed as close as possible to the FB pins, and far away from the SW pins. * Place high frequency ceramic capacitors between VIN, VOUT, and PGND, as close to the module as possible in order to minimize high frequency noise. Place several vias close to the ceramic capacitors. The ground terminal of the input capacitors and output capacitors should be placed as close as possible. Package Description The ISL8203M is integrated into a quad flat-pack no-lead package (QFN). This package has such advantages as good thermal and electrical conductivity, low weight, and small size. The QFN package is applicable for surface mounting technology and is becoming more common in the industry. The ISL8203M is a copper lead-frame based package with exposed copper thermal pads, which have good electrical and thermal conductivity. The copper lead frame and multi-component assembly are over-molded with polymer mold compound to protect these devices. FN8661.1 July 23, 2014 ISL8203M Thermal Vias A grid of 1.0mm to 1.2mm pitched thermal vias, which drops down and connects to buried copper planes, should be placed under the thermal land. The vias should be about 0.3mm to 0.33mm in diameter, with the barrel plated to about 2.0 ounce copper. Although adding more vias (by decreasing pitch) improves thermal performance, it also diminishes results as more vias are added. Use only as many vias as are needed for the thermal land size and as your board design rules allow. Stencil Pattern Design Reflowed solder joints on the perimeter I/O lands should have about a 50m to 75m (2mil to 3mil) standoff height. The solder paste stencil design is the first step in developing optimized, reliable solder joins. The stencil aperture size to land size ratio should typically be 1:1. Aperture width may be reduced slightly to help prevent solder bridging between adjacent I/O lands. FIGURE 31. RECOMMENDED LAYOUT The package outline, typical PCB layout pattern, and typical stencil pattern design are shown in the L23.6.5x9 package outline drawing on page 17. TB493 shows typical reflow profile parameters. These guidelines are general design rules. Users can modify parameters according to specific applications. PCB Layout Pattern Design The bottom of ISL8203M is a lead-frame footprint, which is attached to the PCB by surface mounting. The PCB layout pattern is shown in the L23.6.5x9 "Package Outline Drawing" on page 17. The PCB layout pattern is essentially 1:1 with the QFN exposed pad and the I/O termination dimensions, except that the PCB lands are slightly longer than the QFN terminations by about 0.2mm (0.4mm max). This extension allows for solder filleting around the package periphery and ensures a more complete and inspectable solder joint. The thermal lands on the PCB layout should match 1:1 with the package exposed die pads. Submit Document Feedback 15 To reduce solder paste volume on the larger thermal lands, an array of smaller apertures instead of one large aperture is recommended. The stencil printing area should cover 50% to 80% of the PCB layout pattern. Consider the symmetry of the whole stencil pattern when designing the pads. A laser-cut, stainless-steel stencil with electropolished trapezoidal walls is recommended. Electropolishing smooths the aperture walls, resulting in reduced surface friction and better paste release, which reduces voids. Using a trapezoidal section aperture (TSA) also promotes paste release and forms a brick-like paste deposit, which assists in firm component placement. Reflow Parameters Due to the low mount height of the QFN, "No Clean" Type 3 solder paste, per ANSI/J-STD-005, is recommended. Nitrogen purge is also recommended during reflow. A system board reflow profile depends on the thermal mass of the entire populated board, so it is not practical to define a specific soldering profile just for the QFN. The profile given in TB493 is provided as a guideline to customize for varying manufacturing practices and applications. FN8661.1 July 23, 2014 ISL8203M Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. DATE REVISION CHANGE July 23, 2014 FN8661.1 Added Evaluation Board to "Ordering Information" on page 4. June 23, 2014 FN8661.0 Initial Release About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com Submit Document Feedback 16 FN8661.1 July 23, 2014 ISL8203M Package Outline Drawing L23.6.5x9 23 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 0, 4/14 13x 0.55 6.500 PIN 1 INDEX AREA 2x 0.60 0.100 M C A B 3.60 6 0.90 1.20 B 13 PIN #1 IDENTIFICATION CHAMFER 0.300x45 22 12 1 23 36x 0.50 4x 0.550 3.30 2x 1.40 2x 0.42 9.00 2x 0.50 46x 0.22 0.100 M C A B 00.50 M C 2x 0.90 2x 1.49 2x 1.60 2x 1.42 6 2x 1.00 7 0.60 TOP VIEW A 6 22x 0.30 2x 2.70 2x 2.70 2x 0.50 BOTTOM VIEW 12x 0.22 4x 1.10 SEE DETAIL "X" 2x 0.72 PACKAGE BOUNDARY 1.40 13x 0.750 0.100 C C 1.90 MAX 2x 1.40 2x 1.22 3.30 4x 0.60 2x 0.072 2x 0.90 46X 0.05 C 0.05 SIDE VIEW 2x 1.254 2x 1.60 SEATING PLANE 3.60 2x 1.50 4x 3.20 2x 1.50 2x 2.70 2x 1.00 2x 1.22 4 2x 0.72 C 2x 0.690 0.203 REF 2x 0.590 2x 0.390 0 - 0.05 DETAIL "X" TYPICAL RECOMMENDED LAND PATTERN NOTES: 1. Dimensions are in millimeters. 2. Dimensioning and tolerancing conform to ASMEY 14.5m-1994. 3. Unless otherwise specified, tolerance: Decimal 0.05. 4. Tiebar shown (if present) is a non-functional feature. 5. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 6. Lead pitches not centered in "y" direction. Submit Document Feedback 17 FN8661.1 July 23, 2014 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Intersil: ISL8203MIRZ ISL8203MEVAL2Z