32Kx8 Static RAM
CY62256
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
November 26, 1997
56
Features
• 4.5V–5.5V Oper ati on
• Lo w acti ve power (70 ns, LL ver sion)
—275 mW (max.)
• Lo w standby power (70 ns, LL version)
—28 µW (max.)
• 55, 70 ns access time
• Eas y memory expansion w it h CE and OE f eatures
• TTL-compati ble inputs and outputs
• Automatic power-down when deselected
• CMOS for optimum speed/power
Functional Description
The CY62256 is a high-pe rformance CM O S static RAM orga-
nized as 32,768 words by 8 bits. Easy memor y expansion is
provided by an active LOW chip enable (CE) and active LOW
output en abl e (O E) and three-state driv ers. This de vice has an
automati c power-down fe ature , reducing the power consump-
tion by 99.9% when deselected. The CY62256 is in the stan-
dard 450-mil-wide (300-mil body width) SOIC, TSOP, and
600-mil PDIP packages .
An active LOW write enable signal (WE) controls the writ-
ing/reading op eration of the memory. When CE and WE inputs
are both LOW, data on the eight data input/output pins (I/O0
throug h I/O7) is written int o the memory location addres sed by
the address present on the address pins (A0 through A14).
Reading the device is accomplished by selecting the device
and enabling the outputs, CE and OE active LOW, while WE
remains inactive or HIGH. Under these conditions, the con-
tents of the location addressed by the i nfor mation on address
pins are pr esent on the eight dat a input/output pins.
The input /output pins r emain in a hi gh-impedance s tate unle ss
the chip is selected, outputs are enabled, and write enable
(WE) is HIGH.
LogicBlock Diagram Pin Configurations
A9
A8
A7
A6
A5
A4
A3
A2
COLUMN
DECODER
ROW DECODER
SENSE AMPS
INPUTBUFFER
POWER
DOWN
WE
OE
I/O0
CE
I/O1
I/O2
I/O3
1
2
3
4
5
6
7
8
9
10
11
14 15
16
20
19
18
17
21
24
23
22
Top Vie w
SOIC/DIP
12
13
25
28
27
26
GND
A6
A7
A8
A9
A10
A11
A12
A13
WE
VCC
A4
A3
A2
A1
I/O7
I/O6
I/O5
I/O4
A14
A5
I/O0
I/O1
I/O2
CE
OE
A0
I/O3
512x512
ARRA
Y
I/O7
I/O6
I/O5
I/O4
A10
A13
A11
A12
A1
A14
C62256–1
C62256–2
A0
22
23
24
25
26
27
28
1
2
510
11
15
14
13
12
16
19
18
17
3
4
20
21
7
68
9
OE
A1
A2
A3
A4
WE
VCC
A5
A6
A7
A8
A9
A0
CE
I/O7
I/O6
I/O5
GND
I/O2
I/O1
I/O4
I/O0
A14
A10
A11 A13
A12
C62256–3
I/O3
22
23
24
25
26
27
28
1
2
510
11
15
14
13
12
16
19
18
17
3
4
20
21
7
68
9
OE
A1
A2
A3
A4
WE
VCC
A5
A6
A7
A8
A9
A0
CE
I/O7
I/O6
I/O5
GND
I/O2
I/O1
I/O4
I/O0
A14
A10
A11 A13
A12
C62256–4
I/O3
TSOP I
Top Vie w
(not to scale)
TSOP I
Top Vie w
(not to scale)
Reverse Pinout
CY62256
2
Maximum Ratings
(Above whi ch the useful l ife may be impaired. For user guide-
li nes, not tested.)
Storage Tem perature .....................................−65°C to +15 0°C
Ambient Temperature with
Power Applied...................................................0°C to +7 0 °C
Supply Voltage to Ground Pot ential
(Pin 28 to Pin 14).................................................−0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State[1] ....................................... −0.5V to VCC + 0.5V
DC Input Voltage[1].................................... −0.5V to VCC + 0.5V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage ............. ..... ..... ..... .............. >2001V
(per MIL- STD-883, Method 3015)
Latch-Up Current... .. .................. .. .. ............ ........ ..... >200 m A
Operating Range
Range Ambient Temperature VCC
Commercial 0°C to +70°C 5V ± 10%
Industrial –40°C to +85 °C 5V ± 10%
Electrical Characteristics Over the Oper ating Range
Parameter Description Test Conditi ons
CY62256−55 CY62256−70
UnitMin. Typ[2] Max. Min. Typ[2] Max.
VOH Output HIGH Vol tage VCC = Min., IOH = −1.0 mA 2.4 2.4 V
VOL Output LOW Voltage VCC = Min., IOL = 2.1 mA 0.4 0.4 V
VIH Input HIGH Voltage 2.2 VCC
+0.5V 2.2 VCC
+0.5V V
VIL Input LOW Voltage −0.5 0.8 −0.5 0.8 V
IIX Input Load Current GND < V I < VCC −0.5 +0.5 −0.5 +0.5 µA
IOZ Output Leakage
Current GND < VO < VCC, Output Dis-
abled −0.5 +0.5 −0.5 +0.5 µA
ICC VCC Operating Supply
Current VCC = M ax.,
IOUT = 0 mA,
f = fMAX = 1/tRC
28 55 28 55 mA
L25 50 25 50 mA
LL 25 50 25 50 mA
ISB1 Auto m a tic C E
Power-Down Current—
TTL Inputs
Max. VCC, CE > VIH,
VIN > VIH or
VIN < VIL, f = fMAX
0.5 20.5 2mA
L0.4 0.6 0.4 0.6 mA
LL 0.3 0.5 0.3 0.5 mA
ISB2 Auto m a tic C E
Power-Down Current—
CMOS Inputs
Max. VCC,
CE > VCC − 0.3V
VIN > VCC − 0.3V
or VIN < 0.3V, f = 0
1 5 1 5 mA
L 2 50 250 µA
LL 0.1 50.1 5µA
Indust’l Temp Range LL 0.1 10 0.1 10 µA
Shaded area contains preliminary information.
Capacitance[3]
Parameter Description Test Conditions Max. Unit
CIN Input Capac it ance TA = 25°C, f = 1 MHz,
VCC = 5.0V 6pF
COUT Outpu t Capacitance 8pF
Note:
1. VIL (min.) = −2.0V for pulse durations of less than 20 ns.
2. Typical specifications are the mean values measured over a large sample size across normal production process v ariations and are taken at nominal conditions
(TA = 25°C, VCC). Parameters are guaranteed by design and characterization, and not 100% tested.
3. Tested initially and after any design or process changes that may affect these parameters.
CY62256
3
AC Te st Loads and Waveforms
3.0V
5V
OUTPUT
R1 1800Ω
R2
990Ω
100pF
INCLUDING
JIG AND
SCOPE
GND
90%
10% 90%
10%
<5ns <5ns
5V
OUTPUT
R1 1800Ω
R2
990Ω
5pF
INCLUDING
JIG AND
SCOPE
(a) (b)
OUTPUT 1.77V
Equivalent to: THÉ VENIN EQUIVALENT
ALL INPUT PULSES
C62256–5C62256–6
639Ω
Data Reten ti o n Char acter i stic s
Parameter Description Conditions[4] Min. Typ.[2] Max. Unit
VDR VCC f or D ata Re tention VCC = 3.0V,
CE > VCC − 0.3V,
VIN > VCC − 0. 3V or
VIN < 0.3V
2.0 V
ICCDR Data Retent ion Current L 2 50 µA
LL 0.1 5µA
LL Indust’l0.1 10 µA
tCDR[3] Chip Deselec t to Data
Retention Time 0ns
tR[3] Operation Recovery Time tRC ns
Data Retention Wav eform
Note:
4. No input may exceed VCC+0.5V.
C62256–7
3.0V3.0V
tCDR
VDR >2V
DATA RETENTION MODE
tR
CE
VCC
CY62256
4
Switching Characteristics Over t he Operating Range[5]
Parameter Description
CY62256−55 CY62256−70
UnitMin. Max. Min. Max.
READ CYCLE
tRC Read Cycle Time 55 70 ns
tAA Addr e ss to Data Valid 55 70 ns
tOHA Dat a Hold from Address Change 5 5 ns
tACE CE LOW to Data Valid 55 70 ns
tDOE OE LOW to Data Valid 25 35 ns
tLZOE OE LOW to Low Z[6] 5 5 ns
tHZOE OE HIGH to High Z[6, 7] 20 25 ns
tLZCE CE LOW to Low Z[6] 5 5 ns
tHZCE CE HIGH to High Z[6, 7 ] 20 25 ns
tPU CE LOW to Power-Up 0 0 ns
tPD CE HIGH to P ower-Down 55 70 ns
WRITE CYCLE[8, 9 ]
tWC Write Cycle Time 55 70 ns
tSCE CE LOW to Write End 45 60 ns
tAW Addr ess Set -Up to W rite End 45 60 ns
tHA Add ress Hold from Write End 0 0 ns
tSA Addr ess Set -Up to W rite Start 0 0 ns
tPWE WE Pulse Width 40 50 ns
tSD Data Set-Up to Write End 25 30 ns
tHD Data Hold from Write End 0 0 ns
tHZWE WE LOW to High Z[6, 7] 20 25 ns
tLZWE WE HIGH to Low Z[6] 5 5 ns
Shaded area contains preliminary information.
Swi t ch ing Waveforms
Notes:
5. Test conditions assume signal transition time of 5 ns or less, timing reference lev els of 1.5V, input pulse level s of 0 to 3.0V, and output loading of the specified
IOL/IOH and 100- pF lo ad capaci tance .
6. At any given temperature and voltage condition, tHZCE is les s than tLZCE, tHZOE is less t han t LZOE, and tHZWE is less t han t LZWE fo r any gi v en de vi ce.
7. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part ( b) of A C Test Loads . Transition i s mea sured ±500 mV from s teady- state v ol tage .
8. The internal write time of the memory is defined by the overlap of C E LO W and WE LOW. Bot h signal s must be LO W to ini tiate a write and ei ther signal can t erminate
a write by go in g HIGH. The data in put set-up an d hol d t iming s hould be ref eren ced to th e risi ng edge of th e signal that termina tes t he write.
9. The minimum write cycle time for write cycle #3 (WE controll ed, OE LOW) is th e su m of tHZWE and tSD
10. Device is continuously selected. OE, CE = VIL.
11. WE is HI GH f or read c ycle .
ADDRESS
DATA OUT PREVIOUS DATA VALID DATA VALID
tRC
tAA
tOHA
C62256–8
Read Cycle No. 1
[10,11]
CY62256
5
Notes:
12. Address valid prior to or coincident with CE transition LO W .
13. Data I/O is high impedance if O E = VIH.
14. If CE goes HIGH simult aneously with WE HIG H, the out put r emains i n a high-impe dance s tate .
Swi t ch ing Waveforms (continued)
50%
50%
DATA VALID
tRC
tACE
tDOE
tLZOE
tLZCE
tPU
DATA OUT HIGH IMPEDANCE IMPEDANCE
ICC
ISB
tHZOE
tHZCE
tPD
OE
CE
HIGH
VCC
SUPPLY
CURRENT
C62256–9
Read Cycle No. 2 [11,12]
tHD
tSD
tPWE
tSA
tHA
tAW
tWC
DATA I/O
ADDRESS
CE
WE
OE
tHZOE C62256–10
DATAIN VALID
NOTE
Write Cycl e No. 1 (WE Controlled) [8,13,14]
15
tWC
tAW
tSA tHA
tHD
tSD
tSCE
WE
DATA I/O
ADDRESS
CE
C62256–11
DATAIN VALID
Write Cycl e No . 2 (CE Contr olled) [8,13,14]
CY62256
7
Typ i cal DC an d AC Ch ar acter i stic s
1.2
1.4
1.0
0.6
0.4
0.2
4.0 4.5 5.0 5.5 6.0
1.6
1.4
1.2
1.0
0.8
−55 25 125
−55 25 125
1.2
1.0
0.8
NORMALIZED t AA
120
100
80
60
40
20
0.0 1.0 2.0 3.0 4.0
OUTPUT SOURCE CURRENT (mA)
SUP PLY VOLTAG E (V)
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
AMBIENT TEMPERATURE (°C)
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
AMBIENT TEMPERATURE (°C)
OUT PUT VOLT AGE (V)
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
0.0
0.8
1.4
1.1
1.0
0.9
4.0 4.5 5.0 5.5 6.0
NORMALIZED t
SUP PLY VOLTAG E (V)
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
120
140
100
60
40
20
0.0 1.0 2.0 3.0 4.0
OUTPUT SINK CURRENT (mA)
0
80
OUTPU T VOLTAGE (V )
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
0.6
0.4
0.2
0.0
NORMALIZED I
CC
NORMALIZED I , I
CC SB
ICC
ICC
VCC =5.0V VCC =5.0V
TA=25°C
VCC =5.0V
TA=25°C
ISB
TA=25°C
0.6
0.8
0
AA
1.3
1.2
VIN =5.0V
TA=25°C
1.4
VCC =5.0V
VIN =5.0V
−55 25 105
2.5
2.0
1.5
CURRENT
vs. AMBIENT TEMPERATURE
A MBIENT TEM PERATUR E (°C)
1.0
0.5
0.0
-0.5
ISB
3.0
STANDBY
VCC =5.0V
VIN =5.0V
ISB2 µA
CY62256
8
Typ i cal DC an d AC Ch ar acter i stic s (continued)
3.0
2.5
2.0
1.5
1.0
0.5
0.0 1.0 2.0 3.0 4.0
NORMALIZED I PO
SUP PLY VOLTAG E (V)
TYPICAL POWER-ON CURRENT
vs. SUPPLY VOLTAGE 30.0
25.0
20.0
15.0
10.0
5.0
0 200 400 600 800
DELTA t (ns)
AA
CAPACITANCE (pF)
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING 1.25
1.00
0.75
10 20 30 40
NORMALIZED ICC
CYCLE FREQUENCY (MHz)
NORMALIZED ICC vs.CYCLETIME
0.0 5.0 0.0 1000 0.50
VCC =4.5V
TA=25°C
VCC =5.0V
TA=25°C
VIN =0.5V
Truth Table
CE WE OE Inputs/Outputs Mode Power
H X X High Z Deselect/Power-Down Standby (ISB)
L H L Data Out Read Active (ICC)
L L X D a ta In Write Active (ICC)
L H H High Z Deselect, Out put Disabled Active (ICC)
CY62256
9
Shaded area contains preliminary information.
Document #: 38−00455−C
Orde ring Information
Speed
(ns) Ord eri ng Code Package
Name Pa ck age Ty p e Operating
Range
55 CY62256−55SNC S22 28-Lead 450-Mil (300-Mil Body Width) SOIC Commercial
CY62256L−55SNC S22 28-Lead 450-Mil (300-Mil Body Width ) SOIC
CY62256LL−55SNC S22 28-Lead 450-Mil (300-Mil Body Width) SOIC
CY62256−55ZRC ZR28 28-Lead Reverse Thi n Small Outline Package
CY62256L−55ZRC ZR28 28-Lead Rever se Thi n Small Outline Package
CY62256LL−55ZRC ZR28 28-Lead Rever se Thi n Small Outline Packag e
CY62256−55ZC Z28 28-Lead Thin Small Outl ine Package
CY62256L−55ZC Z28 28-Lead Thin Small Ou tl ine Package
CY62256LL−55ZC Z28 28-Lead Thin Small Ou tl ine Package
CY62256−55PC P15 28-Lead (600-Mil) Molded DIP
70 CY62256−70SNC S22 28-Lead 450-Mil (300-Mil Body Width) SOIC Commercial
CY62256L−70SNC S22 28-Lead 450-Mil (300-Mil Body Width ) SOIC
CY62256LL−70SNC S22 28-Lead 450-Mil (300-Mil Body Width) SOIC
CY62256–70SNI S22 28-Lead 450- M il (300-Mil Body Width ) SOIC Industrial
CY62256L–70SNI S22 28-Lead 450-Mil (300-Mil Body Width ) SOIC
CY62256LL−70SNI S22 28-Lead 450-Mil (300-Mil Body Width) SOIC
CY62256−70ZC Z28 28-Lead Thin Small Outl ine Package Commercial
CY62256L−70ZC Z28 28-Lead Thin Small Ou tl ine Package
CY62256LL−70ZC Z28 28-Lead Thin Small Ou tl ine Package
CY62256–70ZI Z28 28-Lead Thin Small Outl ine Package Industrial
CY62256L−70ZI Z28 28-Lead Thin Small Ou tl ine Package
CY62256LL−70ZI Z28 28-Lead Thin Small Ou tl ine Package
CY62256−70PC P15 28-Lead (600-Mil) Molded DIP Commercial
CY62256L−70PC P15 28-Lead (600-Mi l) Molded DIP
CY62256LL−70PC P15 28-Lead (600-Mi l) Molded DIP
CY62256−70ZRC ZR28 28-Lead Reverse Thin Small Outline Package
CY62256L−70ZRC ZR28 28-Lead Reve rse Thi n Small Outl ine Package
CY62256LL−70ZRC ZR28 28-Lead Reverse Th in Small Outl ine Package
CY62256
10
Pack ag e D iagr ams
28-Lead (600-Mil) MoldedDIP P15
28-Lead 450-Mil (300-Mil Body Width) SOIC S22
CY62256
11
Pack ag e D iagr ams (continued)
28-Lead Thin Small Outline Package Z28
CY62256
© Cypress Semiconductor Corporation, 1997. The information contained herein is subject to change without notice. Cypress Semic onductor Corporation assumes no responsibility for the use
of any circui try other than circuitry embodied in a Cypress Semicon ductor product. Nor does it conv ey or imply any lice nse under patent or other rights. Cypress Semicondu ctor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life -support systems application impli es that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Pack ag e D iagr ams (continued)
28-LeadReverse Thin Small OutlinePackage ZR28
