TECH. CORP. SPECIFICATIONS CUSTOMER SAMPLE CODE : : (Ver.) MASS PRODUCTION CODE PG12864LRF-NRA-H-Q (Ver.0) (Ver.) : DRAWING NO. (Ver.) PG-99003 Customer Approved Date: Approved QC Confirmed Designer Approval For Specifications Only. * This specification is subject to change without notice. Please contact Powertip or it's representative before designing your product based on this specification. Approval For Specifications and Sample. POWERTIP TECH. CORP. Headquarters: th No.8, 6 Road, Taichung Industrial Park, TEL: 886-4-2355-8168 E-mail: sales@powertip.com.tw FAX: 886-4-2355-8166 Http://www.powertip.com.tw Taichung, Taiwan 407 8 NO.PT-A-005-6 TECH. CORP. RECORDS OF REVISION Date Rev. 2006/02/09 0 Description Note Page PG12864LRF-NRA-H-Qis the ROHS compliant part number based on Powertip's standard PG12864LRF-NRA-H Total36 Page PG12864LRF-NRA-H-Q Rev.0(DK) Page2 TECH. CORP. Contents 1. SPECIFICATIONS 1.1 1.2 1.3 1.4 1.5 1.6 Features Mechanical Specifications Absolute Maximum Ratings DC Electrical Characteristics Optical Characteristics Backlight Characteristics 2. MODULE STRUCTURE 2.1 2.2 2.3 2.4 Counter Drawing Interface Pin Description Timing Characteristics Display Command 3. QUALITY ASSURANCE SYSTEM 3.1 Quality Assurance Flow Chart 3.2 Inspection Specification 4. RELIABILITY TEST 4.1 Reliability Test Condition 5. PRECAUTION RELATING PRODUCT HANDLING 5.1 5.2 5.3 5.4 Safety Handling Storage Terms of Warranty 6. THIS PRODUCT CONFORMS THE ROHS OF PTC. NoteFor detailed information please refer to IC data sheetLH155BA5 PG12864LRF-NRA-H-Q Rev.0(DK) Page3 TECH. CORP. 1. SPECIFICATIONS 1.1 Features Item Standard Value Display Type 128 * 64 dots LCD Type FSTN, White, Transflective, Positive, Extended Temp. Driver Condition LCD Module1/64 Duty , 1/9 Bias Viewing Direction 6 O'clock Backlight YG LED B/L Weight Interface Other 1.2 Mechanical Specifications Item Standard Value Unit Outline Dimension 55.2(L) * 39.8(w) * 6.5(H)(Max) mm Viewing Area 45.2(L) * 27.0(w) mm Active Area 40.92(L) *24.28(w) mm Dot Size 0.28(L) *0.34(w) mm Dot Pitch 0.32(L) * 0.38(w) mm NoteFor detailed information please refer to LCM drawing 1.3 Absolute Maximum Ratings Item Symbol Condition Min. Max. Unit Power Supply Voltage VDD -0.3 6.0 V LCD Driver Supply Voltage VDD-VEE -0.3 15.0 V Input Voltage VIN -0.3 VDD+0.3 V Operating Temperature TOP Excluded B/L -20 70 Storage Temperature TST Excluded B/L -30 80 Storage Humidity HD Ta40 - 90 %RH PG12864LRF-NRA-H-Q Rev.0(DK) Page4 TECH. CORP. 1.4 DC Electrical Characteristics VDD = 3.3 V 0.3VVSS = 0VTa = 25 Item Symbol Condition Min. Typ. Max. Unit Logic Supply Voltage VDD 3.0 3.3 3.6 V "H" Input Voltage VIH 0.8 VDD - VDD V "L" Input Voltage VIL 0 - 0.2VDD V Supply Current IDD VDD = 5.0 V - 0.6 1.0 mA -20C - - - 25C 9.2 9.5 9.8 70C - - - LCM Driver Voltage Note: VOP V THE VOP TEST POINT IS VDD - VO 1.5 Optical Characteristics LCD Panel1/64 Duty1/9 BiasVLCD =9.6VTa = 25 Item Symbol Conditions Min. Typ. Max. Reference View Angle C>2.0, = 0 0 - 30 Notes 1 & 2 Contrast Ratio C = 5, = 0 2 5 - Note 3 Response Time(rise) tr = 5, = 0 - 110ms 165ms Note 4 Response Time(fall) tf = 5, = 0 - 190ms 285ms Note 4 PG12864LRF-NRA-H-Q Rev.0(DK) Page5 TECH. CORP. Note 1: Definition of angles and z (=0) Light (when reflected) Cmax. Sensor Y'(=180) Note 2: Definition of viewing angles 1 and 2 LCD panel X(=90) X' Z' Light (when transmitted ) 2.0 1 Y(=0) 2 viewing angle ( fixed) (=90) Note : Optimum viewing angle with the naked eye and viewing angle at Cmax. Above are not always the same Note 3: Definition of contrast C Note 4: Definition of response time Brightness (reflection) of unselected dot (B2) C = Brightness (reflection) of selected dot (B1) VLCD Brightness (reflection) of selected dot 0 (%) -VLCD Brightness B2 Non-selected state (reflection) of Contrast unselected dot Brightness Non-selected state Selected state 90% B1 10% (reflection) Time tf tr 0 Note: Measured with a transmissive LCD operating voltage (v) PG12864LRF-NRA-H-Q Rev.0(DK) panel which is displayed 1 cm2 VLCD : Operating voltage fFRM : Frame frequency tr tf : Response time (fall) : Response time (rise) Page6 TECH. CORP. 1.6 Backlight Characteristics LCD Module with LED Backlight Maximum Ratings Item Symbol Conditions Min. Max. Unit Forward Current IF Ta =25 - 100 mA Reverse Voltage VR Ta =25 - 4 V Power Dissipation PO Ta =25 - 0.26 W Electrical / Optical Characteristics Ta =25 Item Symbol Conditions Min. Typ. Max. Unit Forward Voltage VF IF= 40 mA - 2.1 2.6 V Reverse Current IR VR= 4 V - - 0.2 mA Wavelength p IF= 40 mA 569 - 576 nm Luminous Intensity (without LCD) IV 5 6 - cd/m2 IF=40 mA Color PG12864LRF-NRA-H-Q Rev.0(DK) Yellow-green Page7 TECH. CORP. 2. MODULE STRUCTURE 2.1 Counter Drawing PG12864LRF-NRA-H-Q Rev.0(DK) Page8 TECH. CORP. 2.2 Interface Pin Description Pin No. Symbol 1 VSS Signal ground (GND) 2 RES Controller reset (module reset) 3 CS Chip enable 4 RS Used to identify data sent by MPU at D0 to D7. 5 Function Used to switch between parallel and serial interface. P/S Chip select Data identification Data P/S "H" CSB RS "L" CSB RS Read/Write Serial clock S0-D7 RDB,WRB SDA Write only SCL P/S= "H": Fixes SDA and SCL at "H or "L". P/S= "L" : Fixes D7 to D0 at HI-Z : RDB and WRB at "H" or "L". 6 WR Data write (write data to the module at "L") 7 RD Data read (read data from the module at "L") 8~15 DB0~DB7 16 VDD 17 SCL 18 SDA 19 A LED Backlight (+) 20 K LED Backlight (-) Data bus Power supply (+3.3V) Used as data transfer clock pin when serial interface is selected. The SDA data is shifted at rising edge of the SCL. Internal serial/parallel conversion to 8-bit data is performed by the rising edge at 8th clock of the SCL. Be sure to set this pin at "L" after completion of transfer or at not accessing. Used as serial data input pin when serial interface is selected. Contrast Adjust LCD MODULE 19 20 2.1V PG12864LRF-NRA-H-Q Rev.0(DK) Page9 TECH. CORP. 2.3 Timing Characteristics 2.3.1 system Bus Read/Write Timing (80 Family MPU) tAH8 tAS8 CSB tAH8 tAS8 CSBRS tRDW8 RS tRDW8 RDB RDB tRDH8 tRDH8 D0 to d7 D0 to d7 tRDD8 tCYC8 tRDD8 tCYC8 Read timing Write timing tAH8 tAS8 CSB RS tWRW8 WRB tDS8 tDH8 D0 to d7 tCYC8 PG12864LRF-NRA-H-Q Rev.0(DK) Page10 TECH. CORP. MPU timing characteristics (VDD=3.3 V 10%,Ta=-30 to +85) Item Symbol Measuring condition MIN MAX Unit Address hold time Address setup time System cycle time Road pulse width (READ) Write pulse width (WRITE) Data setup time Data hold time Applicable pin tAH8 tAS8 60 40 ns ns CSB RS tCYC8 tRDW8 tWRW8 450 270 100 ns ns ns RDB WRB tDS8 tDH8 100 40 ns ns D0 to D7 220 ns ns D0 to D7 30 ns All of above pins Read data output delay time Read data hold time tRDD8 tRDH8 Input signal rise and fall time tr,tf CL=15pF 10 (VDD=3.3 V 10%,,Ta=-30 to +85) Item Symbol Measuring condition MIN MAX Unit Address hold time Address setup time System cycle time Road pulse width (READ) Write pulse width (WRITE) Data setup time Data hold time tAH8 tAS8 80 80 ns ns CSB RS tCYC8 tRDW8 tWRW8 900 500 200 ns ns ns RDB WRB tDS8 tDH8 200 80 ns ns D0 to D7 320 ns ns D0 to D7 30 ns All of above pins Read data output delay time Read data hold time tRDD8 tRDH8 Input signal rise and fall time tr,tf PG12864LRF-NRA-H-Q Rev.0(DK) Applicable pin CL=15pF 10 Page11 TECH. CORP. (VDD=3.3 V 10%,,Ta=-30 to +85) Item Symbol Measuring condition MIN MAX Unit Address hold time Address setup time System cycle time Road pulse width (READ) Write pulse width (WRITE) Data setup time Data hold time tAH8 tAS8 160 160 ns ns CSB RS tCYC8 tRDW8 tWRW8 1800 1000 400 ns ns ns RDB WRB tDS8 tDH8 400 160 ns ns D0 to D7 640 ns ns D0 to D7 30 ns All of above pins Read data output delay time Read data hold time tRDD8 tRDH8 Input signal rise and fall time tr,tf CL=15pF 10 Note: All the timings must be specified relative to 20% and 80% of VDD voltage 2-3.2 Serial Interface Timing tDSS tCSH CSB RS tASS tAHS tSLW SCL tSHW tDSS tDHS SDA tCYCS PG12864LRF-NRA-H-Q Rev.0(DK) Applicable pin Page12 TECH. CORP. (VDD=3.3 V 10%,,Ta=-30 to +85) Item Symbol Measuring condition MIN MAX Unit Serial clock period tCYCS 1000 ns SCL "H" pulse width tSHW 400 ns SCL "L" pulse width tSLW 400 ns Address setup time tASS 80 ns Address hold time tAHS 80 ns Data set up time tDSS 400 Data hold time tDHS 400 ns DSB to SCL time tCSS 80 ns CSB hold time tCSH 80 ns Input signal rise and fall time Item tr,tf tCYCS 2000 ns SCL "H" pulse width tSHW 800 ns SCL "L" pulse width tSLW 800 ns Address setup time tASS 160 ns Address hold time tAHS 160 ns Data set up time tDSS 800 Data hold time tDHS 800 ns DSB to SCL time tCSS 160 ns CSB hold time tCSH 160 ns CSB tr,tf 30 Page13 Applicable pin SCL RS SDA ns Note: All the timings must be specified relative to 20% and 80% of VDD voltage. Rev.0(DK) RS 30 ns All of above pins (VDD=1.8~2.4V,Ta=-30 to +85) Serial clock period PG12864LRF-NRA-H-Q SCL SDA Symbol Measuring condition MIN MAX Unit Input signal rise and fall time Applicable pin CSB All of above pins TECH. CORP. 2.3 Command Function The LH155BA has a lot of commands as shown in a list of command and each command is example in detail as follows. Data codes and command codes are defined as follows and execution of commands must be made in the state of chip select (CSB="L")(For example X address) RS e D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 AX3 AX2 AX1 AX0 Data Codes Command Codes RS = "0" : RAM Data Access (7-1,7-2) RS = "1" : Register Access (7-3~7-16) The undefined command codes are inhibited. 2-4.1 Data Write to Display RAM RE RS 0 0 D7 D6 D5 D4 D3 D2 D1 D0 Display RAM write data The Display RAM data of 8-bit are written in the designated X and Y address. 2-4.2 Data Read to Display RAM RE RS 0 0 D7 D6 D5 D4 D3 D2 D1 D0 Display RAM read data The 8-bit contents of Display RAM designated in X and Y address and read out immediately after data are set in X and Y address, dummy read is necessary once. 2-4.3 X Address Register Set RE RS D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 0 0 0 AX3 AX2 AX1 AX0 (At the time of reset AX3~AX0 = 0H, read address : 0H) Addresses of Display RAM's X direction are set. The values of AX3 to AX0 are usable up to 00H-0F, but 10H-FFH are inhibited. When the register setting SEG output normal/reverse is REF = "0", the data of AX3~AX0 are addressed to Display RAM as they are. When REF = "1", the data of 0FH-(AX3~AX0)H are addressed to Display RAM. PG12864LRF-NRA-H-Q Rev.0(DK) Page14 TECH. CORP. 2-4.4 Y Address Register Set RE RS D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 0 1 0 AY3 AY2 AY1 AY0 D2 D1 D0 AY6 AY5 AY4 (At the time of reset AX3~AX0 = 0H, read address : 2H) RE RS D7 D6 0 1 0 0 mark shows "Don't care" D5 D4 1 1 D3 (At the time of reset:AY6~AY4=0H, read address:3H Addresses of Display RAM's Y direction are set. In data setting, lower place and upper place are divided with 4 bit and 3 bit respectively. When data set, lower place must be set first and upper place must be set second. The values of AY6 to AY0 are usable up to 00H-42H, but 43H-FFH are inhibited. The addresses of 40H to 42H are for the Segment Display RAM. 2-4.5 Display Starting Line Register Set RE RS D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 0 0 LY3 LY2 LY1 LY0 D1 D0 (At the time of reset AX3~AX0 = 0H, read address: 4H) RE RS D7 D6 D5 D4 D3 D2 0 1 0 1 0 1 LA5 LA4 mark shows "Don't care" (At the time of reset :LA4,LA5 = 0H, read address: 5H) The display line address is required to designate, and the designated address become the display line of COM0. The display of LCD panel is indicated in he increment direction of the designated display starting address to the line address. LA5 LA4 LA3 LA2 LA1 LA0 LINE ADDRESS 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1 1 1 1 63 PG12864LRF-NRA-H-Q Rev.0(DK) Page15 TECH. CORP. 2-4.6 n Line Alternated Register Set RE RS D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 1 0 N3 N2 N1 N0 D2 D1 D0 (At the time of reset: N3~N0 = 0H, read address: 6H) RE RS D7 D6 D5 D4 D3 0 1 0 1 1 1 N5 N4 mark shows "Don't care"(At the time of reset: N5~N4 = 0H, read address: 7H) The reverse line number of LCD alternated drive is required to set in the register. The line number possible to set is 2-64 lines. The values set up by the n-line alternated register become enable when the n line alternated drive command of ON. (NLIN="1") When the n line alternated drive command is OFF (NLIN="0"), alternated drive waveform which reverses by frame cycle is generated. LA5 LA4 LA3 LA2 LA1 LA0 LINE ADDRESS 0 0 0 0 0 0 0 0 0 0 0 1 2 1 1 1 1 1 1 64 2-4.7 Alternated Timing At the Time of n Line Alternated OFF (in case of 1/64 DUTY Display) Line Frist Line Second Line Third Line 64-th Line LP FLM M PG12864LRF-NRA-H-Q Rev.0(DK) Page16 Frist Line Second TECH. CORP. 2-4.8 Display Control(1) Register Set RE RS D7 D6 D5 D4 D3 D2 D1 D0 0 1 1 0 0 0 SHIFT SEGMENT ALLON ON/OFF (At the time of reset: (SHIFT, SEGON, ALLON, ON/OFF)=0H, read address: 8H) Various control of display is set up. (I) ON/OFF Command (For the Graphic Display only) To control ON/OFF of the Graphic Display ON/OFF = "0": display OFF ON/OFF ="1" : display ON (II) ALLON Command (For the Graphic Display only) Regardless of the data of the Graphic Display RAM, the Graphic Display are on. This command has priority over display normal/reverse commands. SEGON="0":display OFF The terminals are specified VSS level. SEGON="1":display ON (III) SEGMENT Command (For the Segment Display only) To control ON/OFF of the Segment Display SEGON="0":display OFF The terminals are specified VSS level. SEGON="1":display ON (IV) SHIFT Command (For the Graphic Display only) The shift direction of the Graphic Display scanning data in the common driver output is selected. SHIFT="0":COM0->COM63 shift-scan SHIFT="1":COM63->COM0 shift-scan RE RS D7 D6 D5 D4 D3 D2 D1 D0 1 1 1 0 0 0 ER IR mark shows "Don't care"(At the time of reset: (ER,IR)=0H,read address:8H) (i) IR Command (For the Segment Display only) IR command is not available now. When using the Segment Display, please set "0" (ii) ER Command (For the Segment Display only) ER command is not available now. When using the Segment Display, please set "1 And when using the Segment Display, please input VA, VB, VC and VD level externaly. External Power Supply VA VB LH155BA5 VC VD PG12864LRF-NRA-H-Q Rev.0(DK) Page17 TECH. CORP. 2-4.9 Display Control(2) Register Set RE RS D7 D6 D5 D4 D3 D2 D1 D0 0 1 1 0 0 1 REV NLIN SWAP REF (At the time of reset: (REV, NLIN, SWAP, REF)=0H, read address: 9H) Various control of display is set up. (I) REF Command When MPU accesses to the Graphic Display RAM, the relationship between X address and write data is normalized or reversed. Therefore, the order of segment driver output can be reversed by register setting, lessening the limitation of IC location in assembling into the LCD panel. REF ACCESS FROM MPU INTERNAL ACCESS DDRRESPONDING X ADDRESS D7~D0 X ADDRESS D7-D0 SEG OUTPUT 0 NH D0(LSB) D7(MSB) NH (LSB) (MSB) SEG(8*NH) Output 1 NH D0(LSB) D7(MSB) 0FH-NH (MSB) (LSB) SEG(8*NH+7) Output SEG(8*(0F-NH)+7) Output SEG(8*(0F-NH)) Output When using this command. Output of Segment Display Circuits are set as below. However the order of D0->D7 are not changed. REF ACCESS FROM MPU X ADDRESS 0 00H 0 01H 1 0FH 1 H0E D7~D0 D0(LSB) D7(MSB) D0(LSB) D3(MSB) D0(LSB) D7(MSB) D0(LSB) D3(MSB) INTERNAL ACCESS X ADDRESS 00H 01H 00H 01H DDRRESPONDING D7-D0 SEG OUTPUT D0(LSB) D7->D0 D7(MSB) SEGS0->SEGS7 D0(LSB) D0~D3 D3(MSB) SEGS8->SEGS11 D0(LSB) D0->D7 D7(MSB) SEGS0->SEGS7 D0(LSB) D0->D3 D3(MSB) SEGS8->SEGS11 When REF="1",please set X address of Segment Display Circuits like below. 00H->0FH 01H->0EH PG12864LRF-NRA-H-Q Rev.0(DK) Page18 TECH. CORP. (II) SWAP Command (For the Graphic Display only) When data to the Graphic Display RAM are written, the write data are swapped. SWAP="1": Normal mode. In data-writing, the data of D7~D0 can be written to the Display RAM. Graphic SWAP="1": SWAP mode ON. In data-writing, the swapped data of D7~D0 can be written to the Graphic Display RAM. SWAP="0" SWAP="1" EXTERNAL DATA D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 INTERNAL DATA d7 d6 d5 d4 d3 d2 d1 d0 d0 d1 d2 d3 d4 d5 d6 d7 (III) NLIN Command (For the Graphic Display only) The ON/OFF control of n-line alternated drive is performed. NLIN="0" : n line alternated drive OFF. By using frame cycle, the alternated signals (M) are reversed. NLIN="1" : n line alternated drive ON. According to data set up in n line alternated register, the alternation is made. (IV) REV Command (For the Graphic Display only) Corresponding to the data of the Graphic Display RAM, the lighting or not-lighting of the display is set up. REV="0": When RAM data at "H", LCD at ON voltage (normal) REV="1": When RAM data at "L", LCD at ON voltage (reverse) 2-4.10 Increment Control Register Set RE RS D7 D6 D5 D4 D3 D2 D1 D0 0 1 1 0 1 0 AIM AY1 AX1 mark shows "Don't care"(At the time of reset: (AIM, AY1, AX1)= 0H, read address :AH) The increment mode is set up when accessing to the Graphic Display RAM. (The Graphic Display RAM only) By AIM, AY1 and AX1 registers, the setting-up of increment operation /non-operation for the X-address counter and the Y-address counter every write access of every read access to the Graphic Display RAM is possible. In setting to this control register, the increment operation of address can be made without setting successive addresses for writing data or for reading data to the Graphic Display RAM from MPU. After setting this register be sure to set the X and Y Address Register. Because it is not assuring the data of X and Y Address Register after setting increment Control Register. PG12864LRF-NRA-H-Q Rev.0(DK) Page19 TECH. CORP. The increment control of X and Y address by AIM, AY1 and AX1 registers is as follows. ALM SELECTION OF INCREMENT TIMING REFERENCE 0 When writing to Graphic Display RAM or reading from Graphic Display RAM <1> 1 Only when writing to Graphic Display RAM (read modify) <2> <1> This is effective when subsequently writing and reading the successive address area. <2> This is effective in the case that after reading and writing the successive address area every address, the read data are modified to write. AY1 AX1 SELECTION OF INCREMENT ADDRESS REFERENCE 0 0 Increment is not made <1> 0 1 X address automatic increment <2> 1 0 Y address automatic increment <3> 1 1 X and Y address cooperative, automatic increment <4> <1> Regardless of AIM, no increment for X and Y address. <2> According to the setting-up of AIM, increment or decrement for only X address. In accordance with the REF conditions of SEG normal/reverse output setting register, X address become as follows. At REF="0" (normal output), increment by loop of 00H 0FH At REF="1" (reverse output), decrement by loop of <3> According to the setting-up of AIM, increment for only Y address. Regardless of REF, increment by loop of 0FH 00H 00H for Y address. PG12864LRF-NRA-H-Q Rev.0(DK) Page20 3FH TECH. CORP. <4> According to the setting-up of AIM, cooperative variation for X and Y address. When the access of X address is made up to 0FH, Y address increment occurs. At REF="0" (normal output) 00H 0FH 3FH 00H (X address) vary in the above loops. (Y address) AtREF="1" (reverse output 0FH 00H 00H (X address) vary in the above loops. (Y address) 2-4.11 Power Control Register Set (1) RE RS D7 D6 D5 D4 0 1 1 0 1 1 D3 BIAS D2 D1 D0 HALT PON ACL (At the time of reset: BIAS,HLT,PON,ACL)=0H, read address: BH) (1) ACL Command The internal circuit can be initialized. This command is enabled only at Master operation mode. ACL="0":Normal operation ACL="1":Initialization ON If the power control register is read out immediately after executing ACL command (ACL=1), the D0 bit becomes "0". In executing ACL command, the internal reset signals are internally generated by using display master clock (oscillation by OSC1 and OSC0, or clock input at CK pin). Therefore, after executing ACL command, allow WAIT period having at least two cycle portion of the original oscillation clock before the next processing is made. (2) PON Command The internal power supply for the Graphic Display circuit is set ON/OFF. PON="0: Power supply for the Graphic Display circuit OFF PON="1: Power supply for the Graphic Display circuit ON At PON="1": the booster and voltage converter for the Graphic Display circuit function. In accordance with the setting conditions of PMODE pin, the operative circuit part changes. See the Function Description in detail. (3) HALT Command PG12864LRF-NRA-H-Q Rev.0(DK) Page21 TECH. CORP. The conditions of power-saving are set ON/OFF by this command. HALT="0": Normal operation When setting in the power-saving state, the consumed HALT="1": Power-saving operation current can be reduced to a value near to the standby current. The internal conditions at power-saving are as follows. (a) The oscillating circuit and power supply circuit are stopped. (b) The LCD drive is stopped, and output of the segment drive and common driver are VSS lovel. (c) The clock input from CK pin is inhibited. (d) The contents of the Display RAM data are maintained. (e) The operational mode maintains the state of command execution before executing power-saving command. (4) BIAS Command The internal bias value for the Graphic display can be set by this command. BIAS="0": 1/9 bias BIAS="1": 1/7 bias (Bias value for the Segment Display is 1/3 Fixed) 2-4.12 Power Control Register Set (2) RE RS D7 D6 D5 D4 D3 0 1 1 1 0 1 MSS D2 ...... D1 LSB D0 (At the time of reset: DVOL)=0H, read address: DH The LCD drive voltage V0 output from the built-in power circuit can be controlled and the display controlled and the display tone on the LCD can be also controlled. The LCD drive V0 takes one out of 16 voltage values by setting 4 bit data register. MSB ... LSB V0/SV0 0 1 0 1 0 1 0 1 Smaller Larger If the electronic control is not used, specify(1,1,1,1) in the 4-bit data register. After the LH155BA is reset, the 4-bit data register is automatically set to (1,1,1,1) 2-4.13 Power Control register Set (3) RE RS D7 D6 D5 D4 D3 D2 D1 D0 0 1 1 1 1 0 SEGPON EXA ICON mark show "Don't care" (At the time of reset: (SEGPON, EXA, ICON)=0H, read address: EH) (1) ICON Command ICON Display ON/OFF ICON ="0": ICON is OFF PG12864LRF-NRA-H-Q Rev.0(DK) Page22 TECH. CORP. ICON = "1": ICON is ON, See the Function Description in detal. (2) EXA Command Clock for ICON Display External/Internal EXA="0": Internal Clock EXA="1": External Clock from EXA terminal (3) SEGPON Command A power supply for the Segment Display is set ON/OFF SEGPON="0": Power supply circuit OFF SEGPON="1": Power supply circuit ON At SEGPON ="1", the sub-voltage converter for Segment Display function. RE RS D7 D6 D5 D4 D3 D2 1 1 1 1 1 0 DU1 DU0 (At the time of reset: (DU1,DU0,BS1,BS0)=0H, read address: EH) (1) BS Command Select booat voltage level below. BS BS1 BS0 BOOST VOLTAGE LEVEL 0 0 4TIMES 0 1 3 TIMES 1 0 2 TIMES 1 1 PROHIBITION (2) Duty Command Select Duty ratic below.. DUTY D3 D2 DUTY RATIO 0 0 1/64 0 1 1/48 1 0 1/32 1 1 1/16 This module is 1/64 duty. PG12864LRF-NRA-H-Q Rev.0(DK) Page23 D1 D0 BS1 BS0 TECH. CORP. 2-4.14 RE Register Set RE RS D7 D6 D5 D4 D3 D2 D1 0/1 1 1 1 1 0 mark show "Don't care" (At the time of reset: (RE)=0H, read address: FH) D0 RE RE Command RE="0": the below register cannot be accessed. RE="1": the extended function set, electric volume for the Segment Display, Duty ratio select and boost voltage level select can be accessed. 2-4.15 Address Set for Internal Register Read RE RS D7 D6 D5 D4 D3 0 1 1 1 0 0 RA3 (At the time of reset: (RA3, RA2, RA1, RA0)=CH) D2 D1 D0 RA2 RA1 RA0 Then data set up in the internal registers ate read out, set the address for Read allotted to each register by this command before executing the Read command of the internal registers. For example, when the data of the command register in the display control (1) are read out, set the values of (RA3, RA2, RA1, RA0)=8H. Refer to the Function description of each command or at list of commands on the address for Read allotted to each command register. 2-4.16 Internal Register Read RE RS D7 D6 0 1 mark shows "Don't care" D5 D4 D3 D2 D1 D0 Internal register read data Command for reading out the data of the internal registers. When this command is executed, the address for read in the internal registers to be read must be read must be preset. PG12864LRF-NRA-H-Q Rev.0(DK) Page24 TECH. CORP. 2.5 Function Description 2.5.1 MPU Interface 2.5.1-1 Interface Type Selection The LH155BA performs data transfer via the 8-bit data bus or the serial data input (the SDA or SCL pin). The parallel or serial interface is selected by setting the poiarity of the P/S pin to "H' or "L". When selecting serial interface, data-reading cannot be performed. but only data writing can. 2.5.1-2 2.5.1-3 P/S I/F type CSB RS RDB WRB M86 SDA SCL Data H Parallel CSB RS RDB WRB M86 - - D0 to D7 L Serial CSB RS - - - SDA SCL - Parallel input The LH155BA allows parallel data transfer by connecting the data bus to an 8-bit MPU if the parallel interface is selected with the P/S pin. For this 8-bit MPU, the 80-family or 68-family MPU type interface can be selected with the M86 pin. M86 MPU type CSB RS RDB WRB Data L 80-fimily MPU CSB RS RDB WRB D0 to D7 Data identification The LH155BA identifies the data types over the 8-bit data bus by combinations of RS,RDB and WRB signals. 80-family RS WRB RDB FUNCTION 1 0 1 Read internal register 1 1 0 Write internal register 0 0 1 Read display data 0 1 0 Write display data PG12864LRF-NRA-H-Q Rev.0(DK) Page25 TECH. CORP. 2.5.1-4 Serial interface The serial interface for the LH155BA is enabled to accept the SDA and SCL inputs when the chip is selected. If the chip is not selected, the internal shift register and counter are reset to the initial state. The data input is taken in the order of D7...D1, and D0 starting with the serial data input SDA when the serial clock (SCL) rises. At the leading edge of the 8th serial clock , the serial data is converted into 8-bit parallel data and then processed according to its type. The serial data input (SDA) is identified with input at the RS pin. The serial clock input (SCL) must be set to "L' if it is not accessed. After 8-bit data transfer is finished, it must be also set to "L". For the SDA and SCL signals, sufficient care must be taken for external noise. In order to prevent continuous error recognition of transferred data occurring from external noise, the chip selected must be released (CSB="H") whenever 8-bit data transfer is finished. CSB RS SDA valid D7 D6 D5 D4 D3 D2 D1 D0 1 2 3 4 5 6 7 8 SCL 2.5.2 Access to Display RAM and Internal Register The LH155BA makes access to Display RAM, and internal register by data bus D0~D7, chip select CSB is at "H", it is in non-selective state and cannot make access to Display RAM and internal registers, in making access to them , set CSB to "L". The access to either Display RAM or internal registers can be shifted by RS input. RS="L": Display RAM data RS="H": Internal command register The data of 8-bit data bus D0~D7 are written by write operation after address setting through MPU. The timing of Write is at the rising of WRB for 80 family MPU and at the falling of E for 68 family MPU respectively. PG12864LRF-NRA-H-Q Rev.0(DK) Page26 TECH. CORP. Write is is internally processed by placing intermediately the bus holder in the internal data bus .In case of writing data from MPU, the data are temporally held in the bus holder before they are written by the time of the next cycle. Since the Read sequence of Display RAM data is limited, note that when Address Set is made, the designated address data are not output to Read Comman immediately after the Address Set, but are output when the second data Read, resulting in requiring dummy Read one time. Dummy Read is always required one time after Address Set Data Read Operation W RB n D0~D7 Address Set n address RDB D a ta W r ite O p e r a tio n D 0~D 7 n *** n Dummy Read n+1 Data Read n address n+1 n+2 Data Read Data Read n+1 address n+2 address n+2 n+3 n+4 W RB I n te r n a l B us H o ld e r n n+1 n+2 n+3 n+4 W RB 2.5.3 Read of internal Register The LH155BA reads not only Display RAM, but also the internal registers. Addresses for Read (0.2~E[hex])are allotted to each internal register. In reading the internal registers, the addresses of internal registers allotted to read are written in the register Read and then are read. WRB M D0~D7 n N For Register Internal For Register Address set Register Address set Data Read RDB PG12864LRF-NRA-H-Q Rev.0(DK) Page27 n Internal Register Data Read TECH. CORP. 2.5.4 Display Mode The LH155BA have 3 Display modes. One is for Graphic Display mode and one is for Segment display mode and the other is for icon Display. 3 mode are independent of each other, so each mode can function alone. That can drive a minimum circuit each display mode. A suitable mode for lower current consumption is selectable. 2.5.4-1 Graphic Display Mode This mode enable 64x128 Bits - in SRAM and 64 command x 128 segment output terminal. Graphic Display's Memory map is below. When Stand-by mode and Sleep mode, power supply circuit is stopped and output terminal is specified VSS level. The Memory for Graphic Display is accessed by 8 bits at one time. X address is from 00H to 0FH and Y address is from 00H to 3FH. (See table A) 2.5.5 2.5.6 Display Starting Line Register This register is for determining display start line (usually the most upper line) Corresponding to COM0 in case of display the Display data RAM. The register is also used in picture-scrolling. The 6-bit display starting address is set in this register by display starting-line setting command. The register are preset every timing of FLM signal variation in the display line counter. The line counter counts up being synchronized with LP input and generates line addressed which read out sequentially 128-bit data from Display RAM to LCD driver circuit. Addressing of Display RAM Display RAM consists of 128 x 64 bit memory, and makes access in 8 bit unit to an address specified by X address and Y address from MPU. The address, X and Y are possible to be set up so that can increment automatically with the address control register. The increment is made every time Display RAM is read or written from MPU. Thought the X direction side is selected by X address while the Y direction side by Y address, 10H-FFH in the X address are inhibited and do not have the X address set in these addresses. In the Y direction side, the 128-bit display data are internally read the display data latch circuit at the rising of LP every one line cycle, and are output from the display data latch circuit at the falling of LP. 43H-FFH in the Y address are inhibited and do mot have the Y address set in these addresses. When FLM signals being output in one frame cycle are at "H", the value in the display starting line register are preset in the line counter and the line counter counts up at the falling of LP signals. The display line address counter is synchronized with each timing signal of the LCD system to operate and is independent of address counters, X and Y. PG12864LRF-NRA-H-Q Rev.0(DK) Page28 TECH. CORP. 2.5.7 Display RAM Data and LCD One bit of Display RAM data corresponds to one dot of LCD. Normal display and reverse display by REV register are set up as follows. Normal display (REV=0) : RAM data="0" not lighted RAM data="1" lighted Reverse display (REV=1) : RAM data="0" lighted RAM data="1" not lighted =1 X=0FH X=0EH ... X=00H =0 X=00F X=01H ... X=0FH D D D D D D D D D D D D D D D D D D D D D D D D 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 D D D D D D D D D D D D D D D D D D D D D D D D SWAP =1 Display start line Segment Display Output Order/Reverse Set Up The order of display outputs, SEG0~SEG127 can be reversed by reversing access to Display RAM from MPU by using REF register, lessen the limitation in placing IC when assembling a LCD panel module. REP 2.5.8 LINE =0 address 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 00H 00H COM0 01H 01H COM1 02H 02H COM2 03H 03H COM3 04H 04H COM4 05H 05H COM5 06H 06H COM6 07H 07H COM7 08H 08H COM8 3AH 3AH COM58 3BH 3BH COM59 3CH 3CH COM60 3DH 3DH COM61 3EH 3EH COM62 3FH COM63 3FH PG12864LRF-NRA-H-Q ... Rev.0(DK) Page29 Common Output SEG120 SEG121 SEG122 SEG123 SEG124 SEG125 SEG126 SEG127 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SGE7 SEG8 SEG9 SEG10 SEG11 SGE12 SEG13 SEG14 SEG15 Segment Output TECH. CORP. ... 2.5.9 Display Timing Generator The display timing generator generates a timing clock necessary for internal operation and timing pulses (LP, FLM, and M) by inputting the original oscillating clock CK or by the oscillating circuit of OSC1 and OSC0. By setting up Master/Stave mode(M/S), the state of timing pulse pins and the timing generator changes. 2.5.10 Signal Generation to Display Line Counter, and Display Data Latching Circuit Both the clock to the line counter and latching signals to display data latching circuit from the display clock (LP) are generated. Synchronized with the display clock, the line addresses of Display RAM are generated and 128-bit display data are latched to display-data latching circuit to output to the LCD driver circuit (SEG output). 2.5.11 Generation of the Alternated Signal (M) and the Synchronous Signal (FLM) LCD alternated signal (M) and synchronous signal (FLM) are generated by the display clock (LP). The FLM generates alternated drive waveform to the LCD driver circuit. Normally the FLM generates alternated driver drive waveform every frame unit. (M-signal level is reversed every one frame). But by setting up data (n-1) in an n-line reverse register and n-line alternated command (NLIN) at "H", n-line reverse waveform is generated. When the LH155BA is used in multi-chip, the signals of LP, FLM, and M must be sent from Master side in the Slave operation. 2.5.12 Display Data Latching Circuit Display Data Latching Circuit temporary latches display data that is output display data to LCD driver circuit from Display RAM every one common period. Normal display /reverse display, display ON/OFF, and display all on command are operated by controlling data in the latch. And no data within Display RAM changes. PG12864LRF-NRA-H-Q Rev.0(DK) Page30 TECH. CORP. 3. QUALITY ASSURANCE SYSTEM 3.1 Quality Assurance Flow Chart Item Customer Sales Info Marketing & Design R&D Manufactur ing Q.A Product control Purchase Inventory control Survey Request Project Inquiry evaluation Project Validation NG OK Quote Contract Design check Sample test Sample Approval NG Verification NG OK Sample approval OK Pilot Pilot Run & Mass Product NG Verification OK Specification preparation Mass production OK Ship Out PG12864LRF-NRA-H-Q run & Reliability test Inspection NG Shipment Ship out Rev.0(DK) Page31 TECH. CORP. Item Customer Sales Info Claim R&D Q.A Manufactu ring Product control Purchase Failure analysis Sales Service Analysis report Corrective action Tracking 1. ISO 9001 Maintenance Activities Q.A 3. Equipment calibration Activity 5. Standardization Management PG12864LRF-NRA-H-Q Rev.0(DK) 2. Process improvement proposal 4. Education And Training Activities Page32 Inventory control TECH. CORP. 3.2 Inspection Specification Inspection StandardMIL-STD-105E Table Normal Inspection Single Sampling Level EquipmentGaugeMIL-STDPowertip TesterSample IQC Defect LevelMajor Defect AQL 0.4; Minor Defect AQL 1.5 FQC Defect Level100% Inspection OUT Going Defect LevelSampling Specification NO 1 2 3 4 5 Item Specification The part number is inconsistent with work order of Part Number production The quantity is inconsistent with work order of Quantity production The display lacks of some patterns. Electronic Missing line. characteristics of The size of missing dot, A is1/2 Dot size LCM A=( L + W )/2 There is no function. Output data is error Material is different with work order of production LCD is assembled in inverse direction Bezel is assembled in inverse direction Shadow is within LCD viewing area + 0.5 mm Appearance of The diameter of dirty particle, A is0.4 mm LCD Dirty particle length is 3.0mm, and 0.01mmwidth A=( L + W )/2 0.05mm Display is without protective film Dirty particle Conductive rubber is over bezel 1mm (Including Polarizer exceeds over viewing area of LCD scratchbubble ) Area of bubble in polarizer, A1.0mm, the number of bubble is 1 piece. 0.4mmArea of bubble in polarizer, A1.0mm, the number of bubble is 4 pieces. Burned area or wrong part number is on PCB The symbol, character, and mark of PCB are unidentifiable. The stripped solder mask , A is1.0mm 0.3mmstripped solder mask or visible circuit, A Appearance of 1.0mm, and the number is 4 pieces PCB There is particle between the circuits in solder mask A=( L + W )/2 The circuit is peeled off or cracked There is any circuits risen or exposed. 0.2mmArea of solder ball, A is 0.4mm The number of solder ball is 3 pieces The magnitude of solder ball, A is 0.4mm. PG12864LRF-NRA-H-Q Rev.0(DK) Page33 Judge Level N.G. Major N.G. Major N.G. N.G. N.G. N.G. N.G. N.G. N.G. N.G. N.G. N.G. Major Major Major Major Major Major Major Major Major Minor N.G. Minor N.G. N.G. N.G. Minor Minor Minor N.G. Minor N.G. Minor N.G. Major N.G Minor N.G. Minor N.G. Minor N.G N.G N.G Minor Minor Minor N.G Minor N.G Minor TECH. CORP. NO 6 7 8 10 Item Specification The shape of modeling is deformed by touching. Insufficient epoxy: Circuit or pad of IC is visible Appearance of molding Excessive epoxy: Diameter of modeling is 20mm A=( L + W )/2 or height is 2.5mm The diameter of pinhole in modeling, A is 0.2mm. The folding angle of frame must be 45+10 The area of stripped electroplate in top-view of Appearance of frame frame, A is 1.0mm. A=( L + W )/2 Rust or crack is (Top view only) The scratched width of frame is 0.06mm. (Top view only) The color of backlight is nonconforming Electrical Backlight can't work normally. characteristic of The LED lamp can't work normally backlight The unsoldering area of pin for backlight, A is 1/2 solder joint area. A=( L + W )/2 The height of solder pin for backlight is 2.0mm The mark or polarity of component is unidentifiable. The height between bottom of component and surface of the PCB is floating 0.7mm D1/4W W D Assembly parts A=( L + W )/2 PG12864LRF-NRA-H-Q D' Pad End solder joint width, D' is 50% width of component termination or width of pad Side overhang, D is 25% width of component termination. Component is cracked, deformed, and burned, etc. The polarity of component is placed in inverse direction. Maximum fillet height of solder extends onto the component body or minimum fillet height is 0.5mm. Rev.0(DK) Page34 Judge Level N.G. N.G. Major Minor N.G. Minor N.G. N.G. Minor Minor N.G. Minor N.G. Minor N.G. Minor N.G. N.G. N.G. Major Major Major N.G. Minor N.G. N.G. Minor Minor N.G. Minor N.G. Minor N.G. Minor N.G. Minor N.G. Minor N.G. Minor N.G. Minor TECH. CORP. 4. RELIABILITY TEST 4.1 Reliability Test Condition NO Item 1 High Temperature Storage 2 Low Temperature Storage 3 High Temperature /Humidity Storage Test Condition Storage at 80 2 96~100 hrs Surrounding temperature, then storage at normal condition 4hrs Storage at -30 2 96~100 hrs Surrounding temperature, then storage at normal condition 4hrs 1.Storage 96~100 hrs 602, 90~95%RH surrounding temperature, then storage at normal condition 4hrs. (Excluding the polarizer). or 2.Storage 96~100 hrs 402, 90~95%RH surrounding temperature, then storage at normal condition 4 hrs. -20 25 70 25 4 Temperature Cycling (30mins) (5mins) (30mins) (5mins) 10 Cycle 5 Vibration 10~55Hz ( 1 minute ) 1.5mm X,Y and Z direction (each 2hrs) 6 7 ESD Test Drop Test PG12864LRF-NRA-H-Q Rev.0(DK) Air Discharge: Apply 6 KV with 5 times discharge for each polarity +/- Contact Discharge: Apply 250V with 5 times discharge for each polarity +/- Testing location: Around the face of LCD Testing location: 1.Apply to bezel. 2.Apply to Vdd, Vss. Packing Weight (Kg) Drop Height (cm) 0 ~ 45.4 122 45.4 ~ 90.8 76 90.8 ~ 454 61 Over 454 46 Page35 TECH. CORP. 5. PRECAUTION RELATING PRODUCT HANDLING 5.1 SAFETY 5.1.1 5.1.2 If the LCD panel breaks , be careful not to get the liquid crystal to touch your skin. If the liquid crystal touches your skin or clothes , please wash it off immediately by using soap and water. 5.2 HANDLING 5.2.1 5.2.2 5.2.8 Avoid any strong mechanical shock which can break the glass. Avoid static electricity which can damage the CMOS LSI--When working with the module , be sure to ground your body and any electrical equipment you may be using. Do not remove the panel or frame from the module. The polarizing plate of the display is very fragile. So , please handle it very carefully ,do not touch , push or rub the exposed polarizing with anything harder than an HB pencil lead (glass , tweezers , etc.) Do not wipe the polarizing plate with a dry cloth , as it may easily scratch the surface of plate. Do not touch the display area with bare hands , this will stain the display area. Do not use ketonics solvent & aromatic solvent. Use with a soft cloth soaked with a cleaning naphtha solvent. To control temperature and time of soldering is 32010and 3-5 sec. 5.2.9 To avoid liquid (include organic solvent) stained on LCM . 5.2.3 5.2.4 5.2.5 5.2.6 5.2.7 5.3 STORAGE 5.3.1 Store the panel or module in a dark place where the temperature is 25 5 5.3.2 5.3.3 and the humidity is below 65% RH. Do not place the module near organics solvents or corrosive gases. Do not crush , shake , or jolt the module. 5.4 TERMS OF WARRANTY 5.4.1 5.4.2 Applicable warrant period The period is within thirteen months since the date of shipping out under normal using and storage conditions. Unaccepted responsibility This product has been manufactured to your company's specification as a part for use in your company's general electronic products. It is guaranteed to perform according to delivery specifications. For any other use apart from general electronic equipment , we cannot take responsibility if the product is used in nuclear power control equipment , aerospace equipment , fire and security systems or any other applications in which there is a direct risk to human life and where extremely high levels of reliability are required. PG12864LRF-NRA-H-Q Rev.0(DK) Page36