TECH. CORP.
SPECIFICATIONS
CUSTOMER
:
SAMPLE CODE (Ver.)
:
PG12864LRF-NRA-H-Q (Ver.0)
MASS PRODUCTION CODE (Ver.)
DRAWING NO.
(
Ver.
)
: PG-99003
Customer Approved
Date:
Approved QC Confirmed Designer
■ Approval For Specifications Only.
* This specification is subject to change without notice.
Please contact Powertip or it’s representative before designing your product based on this specification.
□ Approval For Specifications and Sample.
POWERTIP TECH. CORP.
Headquarters: No.8, 6th Road, Taichung Industrial Park,
Ta ichung, Taiwan
台中市 407 工業區六路 8號
TEL: 886-4-2355-8168
FAX: 886-4-2355-8166
E-mail: sales@powertip.com.tw
Http://www.powertip.com.tw
NO.PT-A-005-6
TECH. CORP.
PG12864LRF-NRA-H-Q Rev.0(DK) Page2
RECORDS OF REVISION
Date Rev. Description Note Page
2006/02/09 0
PG12864LRF-NRA-H-Qis the ROHS compliant part number
based on Powertip's standard PG12864LRF-NRA-H
Total：36 Page
TECH. CORP.
PG12864LRF-NRA-H-Q Rev.0(DK) Page3
Contents
1. SPECIFICATIONS
1.1 Features
1.2 Mechanical Specifications
1.3 Absolute Maximum Ratings
1.4 DC Electrical Characteristics
1.5 Optical Characteristics
1.6 Backlight Characteristics
2. MODULE STRUCTURE
2.1 Counter Drawing
2.2 Interface Pin Description
2.3 Timing Characteristics
2.4 Display Command
3. QUALITY ASSURANCE SYSTEM
3.1 Quality Assurance Flow Chart
3.2 Inspection Specification
4. RELIABILITY TEST
4.1 Reliability Test Condition
5. PRECAUTION RELATING PRODUCT HANDLING
5.1 Safety
5.2 Handling
5.3 Storage
5.4 Terms of Warranty
6. THIS PRODUCT CONFORMS THE ROHS OF PTC.
Note：For detailed information please refer to IC data sheet：LH155BA5
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PG12864LRF-NRA-H-Q Rev.0(DK) Page4
1. SPECIFICATIONS
1.1 Features
Item Standard Value
Display Type 128 * 64 dots
LCD Type FSTN, White, Transflective, Positive, Extended Temp.
Driver Condition LCD Module：1/64 Duty , 1/9 Bias
Viewing Direction 6 O’clock
Backlight YG LED B/L
Weight －
Interface －
Other －
1.2 Mechanical Specifications
Item Standard Value Unit
Outline Dimension 55.2(L) * 39.8(w) * 6.5(H)(Max) mm
Viewing Area 45.2(L) * 27.0(w) mm
Active Area 40.92(L) *24.28(w) mm
Dot Size 0.28(L) *0.34(w) mm
Dot Pitch 0.32(L) * 0.38(w) mm
Note：For detailed information please refer to LCM drawing
1.3 Absolute Maximum Ratings
Item Symbol Condition Min. Max. Unit
Power Supply Voltage VDD － -0.3 6.0
V
LCD Driver Supply Voltage VDD-VEE － -0.3 15.0 V
Input Voltage VIN － -0.3 VDD+0.3 V
Operating Temperature TOP Excluded B/L -20 70
℃
Storage Temperature TST Excluded B/L -30 80
℃
Storage Humidity HD Ta＜40 ℃ - 90
%RH
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PG12864LRF-NRA-H-Q Rev.0(DK) Page5
1.4 DC Electrical Characteristics
VDD = 3.3 V ± 0.3V，VSS = 0V，Ta = 25℃
Item Symbol Condition Min. Typ. Max. Unit
Logic Supply Voltage VDD － 3.0 3.3 3.6
V
“H” Input Voltage VIH － 0.8 VDD - VDD V
“L” Input Voltage VIL － 0 - 0.2VDD V
Supply Current IDD VDD = 5.0 V - 0.6 1.0 mA
-20°C - - -
25°C 9.2 9.5 9.8
LCM Driver Voltage VOP
70°C - - -
V
Note: THE VOP TEST POINT IS VDD - VO
1.5 Optical Characteristics
LCD Panel：1/64 Duty，1/9 Bias，VLCD =9.6V，Ta = 25℃
Item Symbol Conditions Min. Typ. Max. Reference
View Angle θ C>2.0, ∅ = 0° 0° - 30° Notes 1 & 2
Contrast Ratio C θ = 5°, ∅ = 0° 2 5 - Note 3
Response Time(rise) tr θ = 5°, ∅ = 0° - 110ms 165ms Note 4
Response Time(fall) tf θ = 5°, ∅ = 0° - 190ms 285ms Note 4
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PG12864LRF-NRA-H-Q Rev.0(DK) Page6
Light (when reflected) z (θ=0°)
Note 1: Definition of angles θ and ∅ Note 2: Definition of viewing angles θ1 and θ2
θ1 θ2
viewing angle θ (∅ fixed)
Note : Optimum viewing angle with the
naked eye and viewing angle θ at
Cmax. Above are not always the same
Note 3: Definition of contrast C Note 4: Definition of response time
Brightness (reflection) of unselected dot (B2)
C = ⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯
Brightness (reflection) of selected dot (B1)
Contrast
Non-selected state
VLCD
-VLCD
0
t
f
90%
t
r
10%
Selected state Non-selected state
Time
0
Note: Measured with a transmissive LCD
operating voltage (v) panel which is displayed 1 cm2
VLCD : Operating voltage fFRM : Frame frequency
t
r : Response time (rise) tf : Response time (fall)
(%)
Brightness
(reflection)
Brightness (reflection) o
f
selected dot
Brightness
(reflection) of
unselected dot
Cmax.
2.0
Sensor
LCD panel
X(∅=90°)
Light (when transmitted )
X’
Z’
Y(∅=0°)
(θ=90°)
∅
Y’(∅=180°)
θ
B2
B1
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PG12864LRF-NRA-H-Q Rev.0(DK) Page7
1.6 Backlight Characteristics
LCD Module with LED Backlight
Maximum Ratings
Item Symbol Conditions Min. Max. Unit
Forward Current IF Ta =25℃ - 100 mA
Reverse Voltage VR Ta =25℃ - 4 V
Power Dissipation PO Ta =25℃ - 0.26 W
Electrical / Optical Characteristics
Ta =25℃
Item Symbol Conditions Min. Typ. Max. Unit
Forward Voltage VF IF= 40 mA - 2.1 2.6 V
Reverse Current IR VR= 4 V - - 0.2 mA
Wavelength λp IF= 40 mA 569 - 576 nm
Luminous Intensity
(without LCD) IV IF=40 mA
5 6 -
cd/m2
Color Yellow-green
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2. MODULE STRUCTURE
2.1 Counter Drawing
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PG12864LRF-NRA-H-Q Rev.0(DK) Page9
2.2 Interface Pin Description
Pin No. Symbol Function
1 VSS Signal ground (GND)
2 RES Controller reset (module reset)
3 CS Chip enable
4 RS Used to identify data sent by MPU at D0 to D7.
Used to switch between parallel and serial interface.
P/S Chip select Data identification Data Read/Write Serial clock
“H” CSB RS S0-D7 RDB,WRB -
“L” CSB RS SDA Write only SCL
5
P/S
P/S= ”H”: Fixes SDA and SCL at “H or “L”.
P/S= “L” : Fixes D7 to D0 at HI-Z : RDB and WRB at “H” or “L”.
6 WR Data write (write data to the module at “L”)
7 RD Data read (read data from the module at “L”)
8~15 DB0~DB7 Data bus
16 VDD Power supply (+3.3V)
17 SCL
Used as data transfer clock pin when serial interface is selected.
The SDA data is shifted at rising edge of the SCL.
Internal serial/parallel conversion to 8-bit data is performed by
the rising edge at 8th clock of the SCL.
Be sure to set this pin at “L” after completion of transfer or at
not accessing.
18 SDA Used as serial data input pin when serial interface is selected.
19 A LED Backlight (+)
20 K LED Backlight (-)
Contrast Adjust
LCD MODULE
2.1V
19 20
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PG12864LRF-NRA-H-Q Rev.0(DK) Page10
2.3 Timing Characteristics
2.3.1 system Bus Read/Write Timing (80 Family MPU)
․Read timing
․Write timing
CSB
RS
RDB
D0 to d7
tAS8 tAH8
tRDW8
tRDH8
tRDD8
tCYC8
CSB
RS
RDB
D0 to d7
tAS8 tAH8
tRDW8
tRDH8
tRDD8
tCYC8
CSB
RS
WRB
D0 to d7
tAS8 tAH8
tWRW8
tDH8
tCYC8
tDS8
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PG12864LRF-NRA-H-Q Rev.0(DK) Page11
MPU timing characteristics
(VDD=3.3 V ± 10%,Ta=-30 to +85℃)
Item Symbol Measuring condition MIN MAX Unit Applicable pin
Address hold time
Address setup time
tAH8
tAS8
60
40
ns
ns
CSB
RS
System cycle time
Road pulse width (READ)
Write pulse width (WRITE)
tCYC8
tRDW8
tWRW8
450
270
100
ns
ns
ns
RDB
WRB
Data setup time
Data hold time
tDS8
tDH8
100
40
ns
ns
D0 to D7
Read data output delay time
Read data hold time
tRDD8
tRDH8
CL=15pF
10
220 ns
ns
D0 to D7
Input signal rise and fall time tr,tf 30 ns All of above pins
(VDD=3.3 V ± 10%,,Ta=-30 to +85℃)
Item Symbol Measuring condition MIN MAX Unit Applicable pin
Address hold time
Address setup time
tAH8
tAS8
80
80
ns
ns
CSB
RS
System cycle time
Road pulse width (READ)
Write pulse width (WRITE)
tCYC8
tRDW8
tWRW8
900
500
200
ns
ns
ns
RDB
WRB
Data setup time
Data hold time
tDS8
tDH8
200
80
ns
ns
D0 to D7
Read data output delay time
Read data hold time
tRDD8
tRDH8
CL=15pF
10
320 ns
ns
D0 to D7
Input signal rise and fall time tr,tf 30 ns All of above pins
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PG12864LRF-NRA-H-Q Rev.0(DK) Page12
(VDD=3.3 V ± 10%,,Ta=-30 to +85℃)
Item Symbol Measuring condition MIN MAX Unit Applicable pin
Address hold time
Address setup time
tAH8
tAS8
160
160
ns
ns
CSB
RS
System cycle time
Road pulse width (READ)
Write pulse width (WRITE)
tCYC8
tRDW8
tWRW8
1800
1000
400
ns
ns
ns
RDB
WRB
Data setup time
Data hold time
tDS8
tDH8
400
160
ns
ns
D0 to D7
Read data output delay time
Read data hold time
tRDD8
tRDH8
CL=15pF
10
640 ns
ns
D0 to D7
Input signal rise and fall time tr,tf 30 ns All of above pins
Note: All the timings must be specified relative to 20% and 80% of VDD voltage
2-3.2 Serial Interface Timing
CSB
SCL
RS
SDA
tDSS tCSH
tASS tAHS
tSLW
tSHW
tDHStDSS
tCYCS
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PG12864LRF-NRA-H-Q Rev.0(DK) Page13
(VDD=3.3 V ± 10%,,Ta=-30 to +85℃)
Item Symbol Measuring condition MIN MAX Unit Applicable pin
Serial clock period tCYCS 1000 ns
SCL “H” pulse width tSHW 400 ns
SCL “L” pulse width tSLW 400 ns
SCL
Address setup time tASS 80 ns
Address hold time tAHS 80 ns
RS
Data set up time tDSS 400
Data hold time tDHS 400 ns
SDA
DSB to SCL time tCSS 80 ns
CSB hold time tCSH 80 ns
CSB
Input signal rise and fall time tr,tf
30 ns All of above pins
(VDD=1.8~2.4V,Ta=-30 to +85℃)
Item Symbol Measuring condition MIN MAX Unit Applicable pin
Serial clock period tCYCS 2000 ns
SCL “H” pulse width tSHW 800 ns
SCL “L” pulse width tSLW 800 ns
SCL
Address setup time tASS 160 ns
Address hold time tAHS 160 ns
RS
Data set up time tDSS 800
Data hold time tDHS 800 ns
SDA
DSB to SCL time tCSS 160 ns
CSB hold time tCSH 160 ns
CSB
Input signal rise and fall time tr,tf
30 ns All of above pins
Note: All the timings must be specified relative to 20% and 80% of VDD voltage.
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PG12864LRF-NRA-H-Q Rev.0(DK) Page14
2.3 Command Function
The LH155BA has a lot of commands as shown in a list of command and each command is example in detail as follows.
Data codes and command codes are defined as follows and execution of commands must be made in the state of chip select
(CSB=”L”)(For example X address)
RS D7 D6 D5 D4 D3 D2 D1 D0
e※ 0 0 0 0 AX3 AX2 AX1 AX0
※RS = ”0” : RAM Data Access (7-1,7-2)
RS = “1” : Register Access (7-3~7-16)
The undefined command codes are inhibited.
2-4.1 Data Write to Display RAM
RE RS D7 D6 D5 D4 D3 D2 D1 D0
0 0 Display RAM write data
The Display RAM data of 8-bit are written in the designated X and Y address.
2-4.2 Data Read to Display RAM
RE RS D7 D6 D5 D4 D3 D2 D1 D0
0 0 Display RAM read data
The 8-bit contents of Display RAM designated in X and Y address and read out
immediately after data are set in X and Y address, dummy read is necessary once.
2-4.3 X Address Register Set
RE RS D7 D6 D5 D4 D3 D2 D1 D0
0 1 0 0 0 0 AX3 AX2 AX1 AX0
(At the time of reset AX3~AX0 = 0H, read address : 0H)
Addresses of Display RAM’s X direction are set. The values of AX3 to AX0 are usable up to
00H-0F, but 10H-FFH are inhibited. When the register setting SEG output normal/reverse is
REF = “0”, the data of AX3~AX0 are addressed to Display RAM as they are.
When REF = “1”, the data of 0FH-(AX3~AX0)H are addressed to Display RAM.
Command Codes Data Codes
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PG12864LRF-NRA-H-Q Rev.0(DK) Page15
2-4.4 Y Address Register Set
RE RS D7 D6 D5 D4 D3 D2 D1 D0
0 1 0 0 1 0 AY3 AY2 AY1 AY0
(At the time of reset AX3~AX0 = 0H, read address : 2H)
RE RS D7 D6 D5 D4 D3 D2 D1 D0
0 1 0 0 1 1
※ AY6 AY5 AY4
※ mark shows “Don’t care”
(At the time of reset:AY6~AY4=0H, read address:3H
Addresses of Display RAM’s Y direction are set. In data setting, lower place and upper place are
divided with 4 bit and 3 bit respectively.
When data set, lower place must be set first and upper place must be set second.
The values of AY6 to AY0 are usable up to 00H-42H, but 43H-FFH are inhibited.
The addresses of 40H to 42H are for the Segment Display RAM.
2-4.5 Display Starting Line Register Set
RE RS D7 D6 D5 D4 D3 D2 D1 D0
0 1 0 1 0 0 LY3 LY2 LY1 LY0
(At the time of reset AX3~AX0 = 0H, read address: 4H)
RE RS D7 D6 D5 D4 D3 D2 D1 D0
0 1 0 1 0 1
※ ※ LA5 LA4
※ mark shows “Don’t care” (At the time of reset :LA4,LA5 = 0H, read address: 5H)
The display line address is required to designate, and the designated address become the
display line of COM0.
The display of LCD panel is indicated in he increment direction of the designated display starting
address to the line address.
LA5 LA4 LA3 LA2 LA1 LA0 LINE ADDRESS
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
1
1
0
1
63
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PG12864LRF-NRA-H-Q Rev.0(DK) Page16
2-4.6 n Line Alternated Register Set
RE RS D7 D6 D5 D4 D3 D2 D1 D0
0 1 0 1 1 0 N3 N2 N1 N0
(At the time of reset: N3~N0 = 0H, read address: 6H)
RE RS D7 D6 D5 D4 D3 D2 D1 D0
0 1 0 1 1 1
※ ※ N5 N4
※ mark shows “Don’t care”(At the time of reset: N5~N4 = 0H, read address: 7H)
The reverse line number of LCD alternated drive is required to set in the register. The line number
possible to set is 2-64 lines.
The values set up by the n-line alternated register become enable when the n line alternated drive
command of ON. (NLIN=”1”)
When the n line alternated drive command is OFF (NLIN=”0”), alternated drive waveform which
reverses by frame cycle is generated.
LA5 LA4 LA3 LA2 LA1 LA0 LINE ADDRESS
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
1
1
-
2
64
2-4.7 Alternated Timing
LP
FLM
M
Frist
Line
Line
Second
Line Line
Third
Line
64−th Frist
Line
Second
At the Time of n Line Alternated OFF (in case of 1/64 DUTY Display)
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PG12864LRF-NRA-H-Q Rev.0(DK) Page17
2-4.8 Display Control(1) Register Set
RE RS D7 D6 D5 D4 D3 D2 D1 D0
0 1 1 0 0 0
SHIFT SEGMENT ALLON ON/OFF
(At the time of reset: (SHIFT, SEGON, ALLON, ON/OFF)=0H, read address: 8H)
Various control of display is set up.
(I) ON/OFF Command (For the Graphic Display only)
To control ON/OFF of the Graphic Display
ON/OFF = “0”: display OFF
ON/OFF =”1” : display ON
(II) ALLON Command (For the Graphic Display only)
Regardless of the data of the Graphic Display RAM, the Graphic Display are on.
This command has priority over display normal/reverse commands.
SEGON=”0”:display OFF
The terminals are specified VSS level.
SEGON=”1”:display ON
(III) SEGMENT Command (For the Segment Display only)
To control ON/OFF of the Segment Display
SEGON=”0”:display OFF
The terminals are specified VSS level.
SEGON=”1”:display ON
(IV) SHIFT Command (For the Graphic Display only)
The shift direction of the Graphic Display scanning data in the common driver output is selected.
SHIFT=”0”:COM0->COM63 shift-scan
SHIFT=”1”:COM63->COM0 shift-scan
RE RS D7 D6 D5 D4 D3 D2 D1 D0
1 1 1 0 0 0
※ ※ ER IR
※ mark shows “Don’t care”(At the time of reset: (ER,IR)=0H,read address:8H)
(i) IR Command (For the Segment Display only)
IR command is not available now. When using the Segment Display, please set “0”
(ii) ER Command (For the Segment Display only)
ER command is not available now. When using the Segment Display, please set “1
And when using the Segment Display, please input VA, VB, VC and VD level externaly.
External
Power
Supply
VA
VB
VC
VD
LH155BA5
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PG12864LRF-NRA-H-Q Rev.0(DK) Page18
2-4.9 Display Control(2) Register Set
RE RS D7 D6 D5 D4 D3 D2 D1 D0
0 1 1 0 0 1 REV NLIN SWAP REF
(At the time of reset: (REV, NLIN, SWAP, REF)=0H, read address: 9H)
Various control of display is set up.
(I) REF Command
When MPU accesses to the Graphic Display RAM, the relationship between X address and write
data is normalized or reversed.
Therefore, the order of segment driver output can be reversed by register setting, lessening the
limitation of IC location in assembling into the LCD panel.
ACCESS FROM MPU INTERNAL ACCESS
REF
X ADDRESS D7~D0 X ADDRESS D7-D0
DDRRESPONDING
SEG OUTPUT
0 NH D0(LSB)
D7(MSB) NH (LSB)
(MSB)
SEG(8*NH) Output
SEG(8*NH+7) Output
1 NH D0(LSB)
D7(MSB) 0FH-NH (MSB)
(LSB)
SEG(8*(0F-NH)+7) Output
SEG(8*(0F-NH)) Output
When using this command. Output of Segment Display Circuits are set as below.
However the order of D0->D7 are not changed.
ACCESS FROM MPU INTERNAL ACCESS
REF
X ADDRESS D7~D0 X ADDRESS D7-D0
DDRRESPONDING
SEG OUTPUT
0 00H D0(LSB)
D7(MSB) 00H D0(LSB)
D7(MSB)
D7->D0
SEGS0->SEGS7
0 01H D0(LSB)
D3(MSB) 01H D0(LSB)
D3(MSB)
D0~D3
SEGS8->SEGS11
1 0FH D0(LSB)
D7(MSB) 00H D0(LSB)
D7(MSB)
D0->D7
SEGS0->SEGS7
1 H0E D0(LSB)
D3(MSB) 01H D0(LSB)
D3(MSB)
D0->D3
SEGS8->SEGS11
When REF=”1”,please set X address of Segment Display Circuits like below.
00H->0FH
01H->0EH
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PG12864LRF-NRA-H-Q Rev.0(DK) Page19
(II) SWAP Command (For the Graphic Display only)
When data to the Graphic Display RAM are written, the write data are swapped.
SWAP=”1”: Normal mode. In data-writing, the data of D7~D0 can be written to the Graphic
Display RAM.
SWAP=”1”: SWAP mode ON. In data-writing, the swapped data of D7~D0 can be written to the
Graphic Display RAM.
SWAP=”0” SWAP=”1”
EXTERNAL DATA D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
INTERNAL DATA d7 d6 d5 d4 d3 d2 d1 d0 d0 d1 d2 d3 d4 d5 d6 d7
(III) NLIN Command (For the Graphic Display only)
The ON/OFF control of n-line alternated drive is performed.
NLIN=”0” : n line alternated drive OFF. By using frame cycle, the alternated signals (M)
are reversed.
NLIN=”1” : n line alternated drive ON. According to data set up in n line alternated register, the
alternation is made.
(IV) REV Command (For the Graphic Display only)
Corresponding to the data of the Graphic Display RAM, the lighting or not-lighting of the
display is set up.
REV=”0”: When RAM data at “H”, LCD at ON voltage (normal)
REV=”1”: When RAM data at “L”, LCD at ON voltage (reverse)
2-4.10 Increment Control Register Set
RE RS D7 D6 D5 D4 D3 D2 D1 D0
0 1 1 0 1 0 ※ AIM AY1 AX1
※ mark shows “Don’t care”(At the time of reset: (AIM, AY1, AX1)= 0H, read address :AH)
The increment mode is set up when accessing to the Graphic Display RAM. (The Graphic
Display RAM only)
By AIM, AY1 and AX1 registers, the setting-up of increment operation /non-operation for the
X-address counter and the Y-address counter every write access of every read access to the
Graphic Display RAM is possible.
In setting to this control register, the increment operation of address can be made without setting
successive addresses for writing data or for reading data to the Graphic Display RAM from MPU.
After setting this register be sure to set the X and Y Address Register.
Because it is not assuring the data of X and Y Address Register after setting increment Control
Register.
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PG12864LRF-NRA-H-Q Rev.0(DK) Page20
The increment control of X and Y address by AIM, AY1 and AX1 registers is as follows.
ALM SELECTION OF INCREMENT TIMING REFERENCE
0 When writing to Graphic Display RAM or reading from Graphic Display RAM <1>
1 Only when writing to Graphic Display RAM (read modify) <2>
<1> This is effective when subsequently writing and reading the successive address area.
<2> This is effective in the case that after reading and writing the successive address area every
address, the read data are modified to write.
AY1 AX1 SELECTION OF INCREMENT ADDRESS REFERENCE
0 0 Increment is not made <1>
0 1 X address automatic increment <2>
1 0 Y address automatic increment <3>
1 1 X and Y address cooperative, automatic increment <4>
<1> Regardless of AIM, no increment for X and Y address.
<2> According to the setting-up of AIM, increment or decrement for only X address.
In accordance with the REF conditions of SEG normal/reverse output setting register, X
address become as follows.
‧At REF=”0” (normal output), increment by loop of
‧At REF=”1” (reverse output), decrement by loop of
<3> According to the setting-up of AIM, increment for only Y address.
Regardless of REF, increment by loop of
for Y address.
00H 0FH
0FH 00H
00H 3FH
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PG12864LRF-NRA-H-Q Rev.0(DK) Page21
<4> According to the setting-up of AIM, cooperative variation for X and Y address.
When the access of X address is made up to 0FH, Y address increment occurs.
‧At REF=”0” (normal output)
‧AtREF=”1” (reverse output
2-4.11 Power Control Register Set (1)
RE RS D7 D6 D5 D4 D3 D2 D1 D0
0 1 1 0 1 1
BIAS HALT PON ACL
(At the time of reset: BIAS,HLT,PON,ACL)=0H, read address: BH)
(1) ACL Command
The internal circuit can be initialized. This command is enabled only at Master operation mode.
ACL=”0”:Normal operation
ACL=”1”:Initialization ON
If the power control register is read out immediately after executing ACL command (ACL=1), the
D0 bit becomes “0”.
In executing ACL command, the internal reset signals are internally generated by using display
master clock (oscillation by OSC1 and OSC0, or clock input at CK pin).
Therefore, after executing ACL command, allow WAIT period having at least two cycle portion of
the original oscillation clock before the next processing is made.
(2) PON Command
The internal power supply for the Graphic Display circuit is set ON/OFF.
PON=”0: Power supply for the Graphic Display circuit OFF
PON=”1: Power supply for the Graphic Display circuit ON
At PON=”1”: the booster and voltage converter for the Graphic Display circuit function.
In accordance with the setting conditions of PMODE pin, the operative circuit part changes. See
the Function Description in detail.
(3) HALT Command
00H 0FH 00H 3FH
(X address) (Y address)
vary in the above loops.
0FH 00H 00H
(X address) (Y address)
vary in the above loops.
TECH. CORP.
PG12864LRF-NRA-H-Q Rev.0(DK) Page22
The conditions of power-saving are set ON/OFF by this command.
HALT=”0”: Normal operation
When setting in the power-saving state, the consumed
HALT=”1”: Power-saving operation current can be reduced to a value near to the standby current.
The internal conditions at power-saving are as follows.
(a) The oscillating circuit and power supply circuit are stopped.
(b) The LCD drive is stopped, and output of the segment drive and common driver are VSS lovel.
(c) The clock input from CK pin is inhibited.
(d) The contents of the Display RAM data are maintained.
(e) The operational mode maintains the state of command execution before executing
power-saving command.
(4) BIAS Command
The internal bias value for the Graphic display can be set by this command.
BIAS=”0”: 1/9 bias
BIAS=”1”: 1/7 bias
(Bias value for the Segment Display is 1/3 Fixed)
2-4.12 Power Control Register Set (2)
RE RS D7 D6 D5 D4 D3 D2 D1 D0
0 1 1 1 0 1 MSS
…… LSB
(At the time of reset: DVOL)=0H, read address: DH
The LCD drive voltage V0 output from the built-in power circuit can be controlled and the display
controlled and the display tone on the LCD can be also controlled.
The LCD drive V0 takes one out of 16 voltage values by setting 4 bit data register.
MSB … LSB V0/SV0
0 0 0 0
1 1 1 1
Smaller
Larger
If the electronic control is not used, specify(1,1,1,1) in the 4-bit data register.
After the LH155BA is reset, the 4-bit data register is automatically set to (1,1,1,1)
2-4.13 Power Control register Set (3)
RE RS D7 D6 D5 D4 D3 D2 D1 D0
0 1 1 1 1 0 SEGPON ※ EXA ICON
※mark show “Don’t care” (At the time of reset: (SEGPON, EXA, ICON)=0H, read address: EH)
(1) ICON Command
ICON Display ON/OFF
ICON =”0”: ICON is OFF
TECH. CORP.
PG12864LRF-NRA-H-Q Rev.0(DK) Page23
ICON = “1”: ICON is ON, See the Function Description in detal.
(2) EXA Command
Clock for ICON Display External/Internal
EXA=”0”: Internal Clock
EXA=”1”: External Clock from EXA terminal
(3) SEGPON Command
A power supply for the Segment Display is set ON/OFF
SEGPON=”0”: Power supply circuit OFF
SEGPON=”1”: Power supply circuit ON
At SEGPON =”1”, the sub-voltage converter for Segment Display function.
RE RS D7 D6 D5 D4 D3 D2 D1 D0
1 1 1 1 1 0 DU1 DU0 BS1 BS0
(At the time of reset: (DU1,DU0,BS1,BS0)=0H, read address: EH)
(1) BS Command
Select booat voltage level below.
BS
BS1 BS0
BOOST
VOLTAGE LEVEL
0 0 4TIMES
0 1 3 TIMES
1 0 2 TIMES
1 1 PROHIBITION
(2) Duty Command
Select Duty ratic below..
DUTY
D3 D2
DUTY RATIO
0 0 1/64
0 1 1/48
1 0 1/32
1 1 1/16
This module is 1/64 duty.
TECH. CORP.
PG12864LRF-NRA-H-Q Rev.0(DK) Page24
2-4.14 RE Register Set
RE RS D7 D6 D5 D4 D3 D2 D1 D0
0/1 1 1 1 1 0 ※ ※ ※ RE
※mark show “Don’t care” (At the time of reset: (RE)=0H, read address: FH)
RE Command
RE=”0”: the below register cannot be accessed.
RE=”1”: the extended function set, electric volume for the Segment
Display, Duty ratio select and boost voltage level select can be accessed.
2-4.15 Address Set for Internal Register Read
RE RS D7 D6 D5 D4 D3 D2 D1 D0
0 1 1 1 0 0 RA3 RA2 RA1 RA0
(At the time of reset: (RA3, RA2, RA1, RA0)=CH)
Then data set up in the internal registers ate read out, set the address for Read allotted to each register by this
command before executing the Read command of the internal registers.
For example, when the data of the command register in the display control (1) are read out, set the values of
(RA3, RA2, RA1, RA0)=8H.
Refer to the Function description of each command or at list of commands on the address for Read allotted
to each command register.
2-4.16 Internal Register Read
RE RS D7 D6 D5 D4 D3 D2 D1 D0
0 1
※ ※ ※ ※ Internal register read data
※ mark shows “Don’t care”
Command for reading out the data of the internal registers.
When this command is executed, the address for read in the internal registers to be read must be
read must be preset.
TECH. CORP.
PG12864LRF-NRA-H-Q Rev.0(DK) Page25
2.5 Function Description
2.5.1 MPU Interface
2.5.1-1 Interface Type Selection
The LH155BA performs data transfer via the 8-bit data bus or the serial data input (the SDA or
SCL pin). The parallel or serial interface is selected by setting the poiarity of the P/S pin to “H’ or
“L”. When selecting serial interface, data-reading cannot be performed.
but only data writing can.
P/S I/F type CSB RS RDB WRB M86 SDA SCL Data
H Parallel CSB RS RDB WRB M86 - - D0 to D7
L Serial CSB RS - - - SDA SCL -
2.5.1-2 Parallel input
The LH155BA allows parallel data transfer by connecting the data bus to an 8-bit
MPU if the parallel interface is selected with the P/S pin.
For this 8-bit MPU, the 80-family or 68-family MPU type interface can be selected with the M86
pin.
M86 MPU type CSB RS RDB WRB Data
L 80-fimily MPU CSB RS RDB WRB D0 to D7
2.5.1-3 Data identification
The LH155BA identifies the data types over the 8-bit data bus by combinations of RS,RDB and
WRB signals.
80-family
RS WRB RDB
FUNCTION
1 0 1 Read internal register
1 1 0 Write internal register
0 0 1 Read display data
0 1 0 Write display data
TECH. CORP.
PG12864LRF-NRA-H-Q Rev.0(DK) Page26
2.5.1-4 Serial interface
The serial interface for the LH155BA is enabled to accept the SDA and SCL inputs when the chip
is selected. If the chip is not selected, the internal shift register and counter are reset to the initial
state.
The data input is taken in the order of D7…D1, and D0 starting with the serial data input SDA
when the serial clock (SCL) rises. At the leading edge of the 8th serial clock , the serial data is
converted into 8-bit parallel data and then processed according to its type.
The serial data input (SDA) is identified with input at the RS pin.
The serial clock input (SCL) must be set to “L’ if it is not accessed. After 8-bit data transfer is
finished, it must be also set to “L”.
For the SDA and SCL signals, sufficient care must be taken for external noise. In order to prevent
continuous error recognition of transferred data occurring from external noise, the chip selected
must be released (CSB=”H”) whenever 8-bit data transfer is finished.
2.5.2 Access to Display RAM and Internal Register
The LH155BA makes access to Display RAM, and internal register by data bus D0~D7, chip select
CSB is at “H”, it is in non-selective state and cannot make access to Display RAM and internal
registers, in making access to them , set CSB to “L”.
The access to either Display RAM or internal registers can be shifted by RS input.
RS=”L”: Display RAM data
RS=”H”: Internal command register
The data of 8-bit data bus D0~D7 are written by write operation after address setting through MPU.
The timing of Write is at the rising of WRB for 80 family MPU and at the falling of E for 68 family
MPU respectively.
valid
D7 D6 D5 D4 D3 D2 D1 D0
12345678
CSB
RS
SDA
SCL
TECH. CORP.
PG12864LRF-NRA-H-Q Rev.0(DK) Page27
Write is is internally processed by placing intermediately the bus holder in the internal data bus .In
case of writing data from MPU, the data are temporally held in the bus holder before they are written
by the time of the next cycle. Since the Read sequence of Display RAM data is limited, note that
when Address Set is made, the designated address data are not output to Read Comman
immediately after the Address Set, but are output when the second data Read, resulting in requiring
dummy Read one time. Dummy Read is always required one time after Address Set
2.5.3 Read of internal Register
The LH155BA reads not only Display RAM, but also the internal registers.
Addresses for Read (0.2~E[hex])are allotted to each internal register. In reading the internal registers,
the addresses of internal registers allotted to read are written in the register Read and then are read.
n n+1 n+2 n+3 n+4
n n+1 n+2 n+3 n+4
D ata W rite
Operation
D0~D7
WRB
Bus
Holder
WRB
Internal
n*** nn+1n+2
Data Read Operation
D0~D7
WRB
RDB
Address Set
n address Read
Dummy Data Read
n address
Data Read
n+1 address
Data Read
n+2 address
MnNn
D0~D7
WRB
RDB
For Register
Address set Register
Internal For Register
Address set
Data Read Data Read
Register
Internal
TECH. CORP.
PG12864LRF-NRA-H-Q Rev.0(DK) Page28
2.5.4 Display Mode
The LH155BA have 3 Display modes.
One is for Graphic Display mode and one is for Segment display mode and the other is for icon
Display. 3 mode are independent of each other, so each mode can function alone. That can drive a
minimum circuit each display mode. A suitable mode for lower current consumption is selectable.
2.5.4-1 Graphic Display Mode
This mode enable 64x128 Bits - in SRAM and 64 command x 128 segment output terminal.
Graphic Display’s Memory map is below.
When Stand-by mode and Sleep mode, power supply circuit is stopped and output terminal is
specified VSS level.
The Memory for Graphic Display is accessed by 8 bits at one time.
X address is from 00H to 0FH and Y address is from 00H to 3FH. (See table A)
2.5.5 Display Starting Line Register
This register is for determining display start line (usually the most upper line)
Corresponding to COM0 in case of display the Display data RAM.
The register is also used in picture-scrolling.
The 6-bit display starting address is set in this register by display starting-line setting command.
The register are preset every timing of FLM signal variation in the display line counter. The line
counter counts up being synchronized with LP input and generates line addressed which read out
sequentially 128-bit data from Display RAM to LCD driver circuit.
2.5.6 Addressing of Display RAM
Display RAM consists of 128 x 64 bit memory, and makes access in 8 bit unit to an address specified
by X address and Y address from MPU.
The address, X and Y are possible to be set up so that can increment automatically with the address
control register. The increment is made every time Display RAM is read or written from MPU.
Thought the X direction side is selected by X address while the Y direction side by Y address,
10H-FFH in the X address are inhibited and do not have the X address set in these addresses.
In the Y direction side, the 128-bit display data are internally read the display data latch circuit at the
rising of LP every one line cycle, and are output from the display data latch circuit at the falling of
LP.
43H-FFH in the Y address are inhibited and do mot have the Y address set in these addresses.
When FLM signals being output in one frame cycle are at “H”, the value in the display starting
line register are preset in the line counter and the line counter counts up at the falling of LP signals.
The display line address counter is synchronized with each timing signal of the LCD system to
operate and is independent of address counters, X and Y.
TECH. CORP.
PG12864LRF-NRA-H-Q Rev.0(DK) Page29
2.5.7 Display RAM Data and LCD
One bit of Display RAM data corresponds to one dot of LCD. Normal display and reverse display by
REV register are set up as follows.
‧Normal display (REV=0) : RAM data=”0” not lighted
RAM data=”1” lighted
‧Reverse display (REV=1) : RAM data=”0” lighted
RAM data=”1” not lighted
2.5.8 Segment Display Output Order/Reverse Set Up
The order of display outputs, SEG0~SEG127 can be reversed by reversing access to Display RAM
from MPU by using REF register, lessen the limitation in placing IC when assembling a LCD panel module.
=1 X=0FH X=0EH … X=00H
REP
=0 X=00F X=01H … X=0FH
=1
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
LINE
SWAP
=0
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
address
Display start line
Common
Output
00H 00H COM0
01H 01H COM1
02H 02H COM2
03H 03H COM3
04H 04H COM4
05H 05H COM5
06H 06H COM6
07H 07H COM7
08H 08H COM8
3AH 3AH COM58
3BH 3BH COM59
3CH 3CH COM60
3DH 3DH COM61
3EH 3EH COM62
3FH … 3FH COM63
TECH. CORP.
PG12864LRF-NRA-H-Q Rev.0(DK) Page30
Segment Output
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SGE7
SEG8
SEG9
SEG10
SEG11
SGE12
SEG13
SEG14
SEG15
…
SEG120
SEG121
SEG122
SEG123
SEG124
SEG125
SEG126
SEG127
2.5.9 Display Timing Generator
The display timing generator generates a timing clock necessary for internal operation and timing pulses
(LP, FLM, and M) by inputting the original oscillating clock CK or by the oscillating circuit of OSC1 and
OSC0.
By setting up Master/Stave mode(M/S), the state of timing pulse pins and the timing generator changes.
2.5.10 Signal Generation to Display Line Counter, and Display Data Latching Circuit
Both the clock to the line counter and latching signals to display data latching circuit from the display
clock (LP) are generated.
Synchronized with the display clock, the line addresses of Display RAM are generated and 128-bit
display data are latched to display-data latching circuit to output to the LCD driver circuit (SEG
output).
2.5.11 Generation of the Alternated Signal (M) and the Synchronous Signal (FLM)
LCD alternated signal (M) and synchronous signal (FLM) are generated by the display clock (LP).
The FLM generates alternated drive waveform to the LCD driver circuit. Normally the FLM generates
alternated driver drive waveform every frame unit.
(M-signal level is reversed every one frame).
But by setting up data (n-1) in an n-line reverse register and n-line alternated command (NLIN) at “H”,
n-line reverse waveform is generated.
When the LH155BA is used in multi-chip, the signals of LP, FLM, and M must be sent from Master
side in the Slave operation.
2.5.12 Display Data Latching Circuit
Display Data Latching Circuit temporary latches display data that is output display data to LCD driver
circuit from Display RAM every one common period. Normal display /reverse display, display
ON/OFF, and display all on command are operated by controlling data in the latch. And no data within
Display RAM changes.
TECH. CORP.
PG12864LRF-NRA-H-Q Rev.0(DK) Page31
3. QUALITY ASSURANCE SYSTEM
3.1 Quality Assurance Flow Chart
Item Customer Sales R&D Q.A
Manufactur
ing
Product
control Purchase Inventory
control
Marketing
&
Design
Sample
Approval
Pilot
Run
&
Mass
Product
Ship
Out
OK
Request
Info Survey
Inquiry Project evaluation
Project Validatio
n
Quote OK
N
G
Contract
Design chec
k
Sample test
Verification
Sam
p
le a
pp
roval
N
G
N
G
Pilot run & Reliabilit
y
test
Verification
S
p
ecification
p
re
p
aration
OK
Mass
p
roduction
Ins
p
ection
N
G
OK
Shi
p
ment
N
G
Shi
p
ou
t
OK
TECH. CORP.
PG12864LRF-NRA-H-Q Rev.0(DK) Page32
Item Customer Sales R&D Q.A
Manufactu
ring
Product
control Purchase Inventory
control
Sales
Service
Q.A
Activity
1. ISO 9001 Maintenance Activities 2. Process improvement proposal
3. Equipment calibration 4. Education And Training Activities
5. Standardization Management
Info Clai
m
Failure anal
y
sis
Corrective action
Trackin
g
Anal
y
sis re
p
ort
TECH. CORP.
PG12864LRF-NRA-H-Q Rev.0(DK) Page33
3.2 Inspection Specification
Inspection Standard：MIL-STD-105E Table Normal Inspection Single Sampling Level Ⅱ。
Equipment：Gauge、MIL-STD、Powertip Tester、Sample。
IQC Defect Level：Major Defect AQL 0.4; Minor Defect AQL 1.5。
FQC Defect Level：100% Inspection。
OUT Going Defect Level：Sampling。
Specification：
NO Item Specification Judge Level
1 Part Number
The part number is inconsistent with work order o
f
production N.G. Major
2 Quantity
The quantity is inconsistent with work order of
production N.G. Major
The display lacks of some patterns. N.G. Major
Missing line. N.G. Major
The size of missing dot, A is＞1/2 Dot size N.G. Major
There is no function. N.G. Major
3
Electronic
characteristics of
LCM
A=( L + W )÷2 Output data is error N.G. Major
Material is different with work order of production N.G. Major
LCD is assembled in inverse direction N.G. Major
Bezel is assembled in inverse direction N.G. Major
Shadow is within LCD viewing area + 0.5 mm N.G. Major
The diameter of dirty particle, A is＞0.4 mm N.G. Minor
Dirty particle length is ＞3.0mm, and 0.01mm＜width
≦0.05mm N.G. Minor
Display is without protective film N.G. Minor
Conductive rubber is over bezel 1mm N.G. Minor
Polarizer exceeds over viewing area of LCD N.G. Minor
Area of bubble in polarizer, A＞1.0mm, the number of
bubble is ＞1 piece. N.G. Minor
4
Appearance of
LCD
A=( L + W )÷2
Dirty particle
(Including
scratch、bubble )
0.4mm＜Area of bubble in polarizer, A＜1.0mm, the
number of bubble is ＞4 pieces. N.G. Minor
Burned area or wrong part number is on PCB N.G. Major
The symbol, character, and mark of PCB are
unidentifiable. N.G Minor
The stripped solder mask , A is＞1.0mm N.G. Minor
0.3mm＜stripped solder mask or visible circuit, A ＜
1.0mm, and the number is ≧4 pieces N.G. Minor
There is particle between the circuits in solder mask N.G Minor
The circuit is peeled off or cracked N.G Minor
There is any circuits risen or exposed. N.G Minor
0.2mm＜Area of solder ball, A is ≦0.4mm
The number of solder ball is ≧3 pieces N.G Minor
5
Appearance of
PCB
A=( L + W )÷2
The magnitude of solder ball, A is ＞0.4mm. N.G Minor
TECH. CORP.
PG12864LRF-NRA-H-Q Rev.0(DK) Page34
NO Item Specification Judge Level
The shape of modeling is deformed by touching. N.G. Major
Insufficient epoxy: Circuit or pad of IC is visible N.G. Minor
Excessive epoxy: Diameter of modeling is ＞20mm
or height is ＞2.5mm N.G. Minor
6
Appearance of
molding
A=( L + W )÷2
The diameter of pinhole in modeling, A is ＞0.2mm. N.G. Minor
The folding angle of frame must be ＞45∘+10∘ N.G. Minor
The area of stripped electroplate in top-view of
frame, A is ＞1.0mm. N.G. Minor
Rust or crack is (Top view only) N.G. Minor
7 Appearance of frame
A=( L + W )÷2
The scratched width of frame is ＞0.06mm.
(Top view only) N.G. Minor
The color of backlight is nonconforming N.G. Major
Backlight can’t work normally. N.G. Major
The LED lamp can’t work normally N.G. Major
The unsoldering area of pin for backlight,
A is ＞1/2 solder joint area. N.G. Minor
8
Electrical
characteristic of
backlight
A=( L + W )÷2 The height of solder pin for backlight is ＞2.0mm N.G. Minor
The mark or polarity of component is unidentifiable. N.G. Minor
The height between bottom of component and
surface of the PCB is floating ＞0.7mm N.G. Minor
D＞1/4W
W D
D’ Pad
N.G. Minor
End solder joint width, D’ is ＞50% width of
component termination or width of pad N.G. Minor
Side overhang, D is ＞25% width of component
termination. N.G. Minor
Component is cracked, deformed, and burned, etc. N.G. Minor
The polarity of component is placed in inverse
direction. N.G. Minor
10 Assembly parts
A=( L + W )÷2
Maximum fillet height of solder extends onto the
component body or minimum fillet height
is ＜0.5mm.
N.G. Minor
TECH. CORP.
PG12864LRF-NRA-H-Q Rev.0(DK) Page35
4. RELIABILITY TEST
4.1 Reliability Test Condition
NO Item Test Condition
1 High Temperature
Storage
Storage at 80 ±2℃ 96~100 hrs
Surrounding temperature, then storage at normal condition
4hrs
2 Low Temperature
Storage
Storage at -30 ±2℃ 96~100 hrs
Surrounding temperature, then storage at normal condition
4hrs
3 High Temperature
/Humidity Storage
1.Storage 96~100 hrs 60±2℃, 90~95%RH surrounding
temperature, then storage at normal condition 4hrs.
(Excluding the polarizer).
or
2.Storage 96~100 hrs 40±2℃, 90~95%RH surrounding
temperature, then storage at normal condition 4 hrs.
4 Temperature Cycling
-20℃ → 25℃ → 70℃ → 25℃
(30mins) (5mins) (30mins) (5mins)
10 Cycle
5 Vibration 10~55Hz ( 1 minute ) 1.5mm
X,Y and Z direction ﹡(each 2hrs)
Air Discharge:
Apply 6 KV with 5 times
discharge for each polarity +/-
Contact Discharge:
Apply 250V with 5 times
discharge for each polarity +/-
6 ESD Test
Testing location:
Around the face of LCD
Testing location:
1.Apply to bezel.
2.Apply to Vdd, Vss.
Packing Weight (Kg) Drop Height (cm)
0 ~ 45.4 122
45.4 ~ 90.8 76
90.8 ~ 454 61
7 Drop Test
Over 454 46
TECH. CORP.
PG12864LRF-NRA-H-Q Rev.0(DK) Page36
5. PRECAUTION RELATING PRODUCT HANDLING
5.1 SAFETY
5.1.1 If the LCD panel breaks , be careful not to get the liquid crystal to touch your skin.
5.1.2 If the liquid crystal touches your skin or clothes , please wash it off immediately by
using soap and water.
5.2 HANDLING
5.2.1 Avoid any strong mechanical shock which can break the glass.
5.2.2 Avoid static electricity which can damage the CMOS LSI—When working with the
module , be sure to ground your body and any electrical equipment you may be using.
5.2.3 Do not remove the panel or frame from the module.
5.2.4 The polarizing plate of the display is very fragile. So , please handle it very
carefully ,do not touch , push or rub the exposed polarizing with anything harder
than an HB pencil lead (glass , tweezers , etc.)
5.2.5 Do not wipe the polarizing plate with a dry cloth , as it may easily scratch the surface of plate.
5.2.6 Do not touch the display area with bare hands , this will stain the display area.
5.2.7 Do not use ketonics solvent & aromatic solvent. Use with a soft cloth soaked with
a cleaning naphtha solvent.
5.2.8 To control temperature and time of soldering is 320±10℃and 3-5 sec.
5.2.9 To avoid liquid (include organic solvent) stained on LCM .
5.3 STORAGE
5.3.1 Store the panel or module in a dark place where the temperature is 25℃ ±5℃
and the humidity is below 65% RH.
5.3.2 Do not place the module near organics solvents or corrosive gases.
5.3.3 Do not crush , shake , or jolt the module.
5.4 TERMS OF WARRANTY
5.4.1 Applicable warrant period
The period is within thirteen months since the date of shipping out under normal
using and storage conditions.
5.4.2 Unaccepted responsibility
This product has been manufactured to your company’s specification as a part for
use in your company’s general electronic products. It is guaranteed to perform
according to delivery specifications. For any other use apart from general
electronic equipment , we cannot take responsibility if the product is used in
nuclear power control equipment , aerospace equipment , fire and security
systems or any other applications in which there is a direct risk to human life
and where extremely high levels of reliability are required.
