Order this data sheet by MC13011/D (MA) MOTOROLA SEMICONDUCTORS MC13011 P.O. BOX 20912 PHOENIX, ARIZONA 85036 Product Preview HIGH PERFORMANCE COLOR TV IF HIGH PERFORMANCE COLOR TV IF SILICON MONOLITHIC INTEGRATED CIRCUIT The MC13011 is a single channel TV IF and PLL detector system for all standard transmission systems. This device enables the designer to produce a high quality IF system with white spot inversion, AFT and AGC. The MC13011 was designed with an emphasis on linearity to minimize sound/picture intermodulation. @ Single Coil Adjustment for AFT and PLL P SUFFIX @ VCO at 1/2 IF for Minimum Beats 24 PLASTIC PACKAGE @ Simple Circuitry for Low System Cost 1 CASE 724-03 @ White Spot Inversion e Symmetrical + 2.0 MHz Pull-In @ Detects Positive or Negative Modulation , CERP MIO PACKAGE @ Auxiliary AM Detector for AM Sound 5 CASE 751E-01 e Simple Alignment Procedure ' FIGURE 1 BLOCK DIAGRAM ---- Liber {10 | saw] bee ey Dig AFT TD fart AFT Vv g Output = 9 Switch CC, 22 be 54 Out witc | | : | lout Filter Digital |_ AFT | | | AFT AFT Amp | Clamp 17 | A = ree) } 19 o> o> ~ t i . a vi Vec Lim} 7S {uM x h ew) YOO LI Satna f | | VCO X2 | | LIM |} Sweep 77 | 4 A 4 4 vco | ; 16 Offset n 14 > AM LIM 7 | Out Detector A oA | > tm | dDet | | >| 90 >| Video) 1 -F l | >| QO Det 4" Sound | 1 rm (Sound) Output 10 RF AGC bs << e 7 Video 412 A AGC Delay '*O- GC ly | Switch 1] Video ial y A, YY Y | Outputs AGC Gate Acquisition Circuit White 2 | [| Spot Inv Lael aheoa go oa RF AGC [11 PLL _L15 20 4 Mode Switch Filter TD Lock 7T> Ground This document contains information on a product under development. MOTOROLA INC., 1987 NP210 Motorola reserves the riaht to chanae or discontinue this product without notice.MC13011 MAXIMUM RATINGS Rating Symbol Value Units Power Supply Voltage Pin 22 Vcc 7.0 Vde Gating Pulse Amplitude V13 +500 mApk Operating Temperature TA -40 to +85 C Storage Temperature Tstg ~65 to +150 C Junction Temperature TJ Max 150 C Power Dissipation Pp 1.25 WwW Derate above 25C 10 mw/c ELECTRICAL CHARACTERISTICS (Vcc = 5.0 Vdc, Ta = 25C unless noted) Characteristic Pins Min Typ Max Units Operating Supply Voltage Range 22 4.5 _ 5.5 Vde Supply Current 22 _ 50 _ mAdc Differential Input Sensitivity for Full Output 6,7 _- 20 _ uVims Bandwidth _ _ 120 _ MHz AGC Range _ _ 80 _ dB Noise Figure _ _ 7.0 _ dB Lock-Up Time _ _ 5.0 _ ms Video Amplitude (100% mod depth) 2,3 _ 2.4 _ Vpp Tuner AGC Current 10 5.0 _ _ mAdc Differential Gain Distortion 2 _ _ 5.0 % Differential Phase Distortion 2 _ 2.0 degrees Video Bandwidth 2,3 _ 8.0 _ MHz Sound Subcarrier Output (-20 dB to PIX) 24 _ 0.1 _ Vems AGC Gate Pulse (R pin 13 ~ 5.0 k) 13 _ +0.3 mApk Differential Input Impedance Rin 6,7 _ 3.4 _ kQ Cin _ 3.0 _ pF FIGURE 2 TEST CIRCUIT VS NC }4 24 tT -e0 Sound Output White I Connection _| Spot Inverted O___ 2 23|NC 1 For AM Video 0 | Modulated utputs To Sync Sep oyeemeas 13 22 oVcc 1 Sound a _| Sub- Carrier _ 4 Mode Switch 21|/NC 0.1 T AFT Output < 20 5 | = = 56 IF 6 19 P 7 $3 3k Input 1.7 pH 18 0.1 7 | = jl 1 Digital 3 17 = = AFT Output oVec 16 i 5 Envelope Off 0 9 AFT Switch 0.1. Lock Detector Detector In J Filter RF AGC 10 18 = 01 = Vec = / . 14> ~Envelope CH 11 RF AGC Filter Detector Out RFAGCO, 2 13 aon 5 AGC Adjust + Gate Pulse (MA) MOTOROLA Semiconductor Products Inc.MC13011 MC13011 CIRCUIT DESCRIPTION Design Aims The MC13011 performs the functions of IF amplifi- cation, AGC, AFT and demodulation of a T.V. IF signal for both positive and negative modulation systems. In this respect it is similar to other circuits already on the market. However, in the means of obtaining these func- tions the MC13011 is very different compared to tradi- tional designs. A unique approach was needed for sev- eral reasons. Tuned circuits associated with the IF amplifier output had to be eliminated to enable the part to be easy to use with the minimum of adjustments and external components. With this approach a high degree of IF stability could be obtained with a reduction in cost. Secondly, new techniques were required to improve performance in certain critical areas (differential phase and gain, etc.). This was especially so in view of the removal of the above mentioned tuned circuits. The basic idea therefore, was to produce an advanced, high performance multi standard IF system which would be economical and easy to use. Such a device can suc- cessfully compete with the already-established IF ampli- fiers now available. System Description Despite the extra complications compared to pseudo synchronous demodulation, true synchronous demo- dulation seemed to be the only way in which enhanced performance could be achieved. The basic system is shown in Figure 1 in block diagram form. The IF ampli- fier is a four stage, AC coupled design having a sensi- tivity of about 20 nV. With a low loss SAW filter and 3.0 to 6.0 dB extra gain in the tuner, there is no need for a SAW pre-amp. The T.V. set signal to noise performance is acceptable, while the net savings in cost is consid- erable. The AGC is a conventional gated system with the usual RF AGC output and RF AGC adjustment. Three stages of the amplifier are gain controlled to give an extended AGC range of 80 dB with improved intermo- dulation, signal handling, and differential phase and gain performance. The AGC reference is switched when positive modulation is selected, via the mode switch, to ensure the video level remains constant. Under these circumstances the AGC must be gated by a pulse which will sample the back porch, as opposed to negative modulation where flyback can be used. In both cases a positive or negative-going pulse may be used. To ensure that the improvements in performance men- tioned above were not lost elsewhere, great care was taken in the design of the video demodulator and video amplifiers. An example of this care is the placing of the phase shift required by the video demodulator on the signal side instead of on the oscillator side of the demo- dulator as is common practice. The 90 phase shift is produced by replacing the usual emitter resistors by capacitors in the diff. amp (Figure 3) feeding the video demodulator. The output currents are 90 with respect to the input voltage over a wide band of frequencies and the small phase errors caused by the transistor Ee (AA) MOTOROLA Semiconductor Products Inc. small signal emitter resistances (re) are corrected by the cross-coupled resistors. This arrangement leads to a simpler design, the ability to adjust the demodulation angle, and lower distortion than is normal at the IF amplifier/demodulator interface. The dynamic emitter resistances, which can give rise to distortion, are now in quadrature with the capacitive reactance and, there- fore, contribute very little to the resultant output. FIGURE 3 90 PHASE SHIFT AMPLIFIER + lout lout + Vret Vine ye Vi +t +_|C Vv WA Following the IF amp and preceding the PLL phase detector is a two stage limiter with a gain of 100 and overall dc feedback. This contrasts with the usual single stage of limiting with no dc feedback and a tuned circuit with diodes at its output. With two stages of limiting, the minimum gain required to remove signal amplitude modulation can be designed-in without the large volt- age swings of a single stage with the same gain. Large voltage swings lead to poor differential phase and gain performance, hence the need for a tuned circuit and diodes as used in previous designs. The dc feedback removes the effects of input offsets which are another source of differential phase and gain problems. The combination of low swing per stage and dc feedback removes the need for having a tuned circuit at the out- put of the limiter and reduces the danger of IF instability and radiation. The only problem in using this technique is the potential for extra static phase shift and resultant errors in the demodulating angles at the video and sound demodulators. However, by putting a similar two stage limiter, with matching phase shift, on the oscil- lator side of the phase detector, the demodulating angles can be restored to the correct phases (0, 90). Having processed the signal in this way, the VCO is then phase locked at 90 to the non-limited signal. The only unusual feature of the loop just described is that the VCO runs at half frequency, and is frequency doubled on-chip. This means radiation from the external fre- quency determining components will be at half IF and so will not desensitize the system even if picked up by the amplifier input leads (this could cause what is known as PLL push-off). Running the oscillator at twice IF fre- quency and dividing down, which is another way ofMC13011 solving this problem has several disadvantages. First and foremost, radiation into the antenna at twice IF pro- duces channel 6 and channel 8 problems in the U.S.A. Secondly, it is easier to produce a stable VCO at half IF. After attaining phase lock, demodulation of the video is achieved by multiplying the signal (non limited) with the regenerated vision carrier (VCO) in a double bal- anced multiplier, the phase relationship between the two waveforms being zero degrees. Both positive and negative sync video outputs are produced. FIGURE 4 PIN 2 VIDEO OUTPUT WITH WHITE-SPOT INVERSION Volts 3.7 -- Soot > Normal 0% 25 J{ and 100% Carrier Levels 1.3 - White Spot Clamp Level T >t FIGURE 5 PIN 3 VIDEO OUTPUT FOR DRIVE TO A SYNC SEPARATOR Volts 3.7 ---Mms-eooC --T Normal 0% and 100% Carrier Levels 1.3, L_ wwf White Spot Sense Threshold | ~ t The negative sync output is intended to be used as the actual video and is acted upon by the white spot noise inverter. This effectively removes the whiter than white noise produced by a true synchronous demo- dulator and prevents the C.R.T. from being over-driven and defocused. The positive sync video output is not acted on by a white spot noise inverter and of course the noise output from a synchronous detector does not contain a dc component. Hence, this drive should be used as the sync separator drive because a simple pre- separator low pass noise filter will produce optimum sync performance. Note the sense of the video signals at the outputs remain the same whether positive or negative modulation is being received. Positive or neg- ative modulation is selected externally by the mode switch pin. The sound intercarrier is recovered by (3) MOTOROLA Semiconductor Products Inc. another demodulator similar to the video, except that the phase relationship between the signal and the VCO is 90 instead of 0. A consequence of this phase rela- tionship is that video interference of the intercarrier sig- nal at the detector output is minimized by suppression of the lower frequency video components. Should the sound carrier contain amplitude information, as in the French T.V. system or as in some scrambied cable sig- nals, this information can be recovered by feeding the sound intercarrier output back into the circuit through a bandpass filter if so desired, to the amplitude detector provided on chip. The AFT portion of the circuit is the most unconven- tional in form. Essentially, AFT is derived by amplifying the error signal driving the VCO after phase lock, and applying this to the local oscillator in the tuner, thus eliminating a coil and a potential IF instability problem. After acquisition, and when the circuit has settled down, due to the much higher gain in the LO loop, the VCO will have moved a small amount (Afv) from its nominal frequency, and almost all the original error frequency (Afe) between LO and VCO will have been corrected by the change in LO frequency (Afl). In this way, provided the PLL can be initially locked to the incoming IF signal, the VCO can be used as the frequency reference for the AFT system. It follows from the above therefore, because the system is phase locked, that Afe = (Afl + Afv). The combination of the local VCO loop and the loop produced by feedback to the LO forms a double loop PLL. Analysis shows that overall system stability can be assured by treating the VCO loop as a stand alone PLL, provided its bandwidth is much wider than the LO loop. The VCO loop therefore is a low gain wide band loop which guarantees initial capture, while the LO loop is basically a high gain de loop used to keep frequency and phase offsets to a minimum. Large phase offsets can also be caused by dc offsets in the phase detector and AFT amplifier. These are removed by the use of commutation on both the phase and AFT outputs. This eliminates the need for external phase adjustment, while at the same time minimizing distortion by main- taining the correct phase angles at the demodulators. The AFT system has been designed to acquire the vision carrier, without false locking to the sound or adja- cent sound carriers, with an initial LO frequency error of + 2.0 MHz, reducing this initial error to 3.0 to 10 kHz when locked. This contrasts to the discriminator type of AFTs which have highly asymmetric lock characteris- tics (~2.0 MHz + 1.0 MHz), because of the effects of the IF filter, and large frequency errors caused by limited loop gain. To achieve this level of performance without encountering the normal AFT problems associated with high loop gain, a novel approach has been taken to locking up to the PLL. In the absence of an IF signal, the acquisition circuitry examines the state of the video (I) and sound (Q) demodulators and detects the lack of a signal. It then clamps the LO drive to a reference dc level and applies a 2.0 MHz offset to the VCO. This is done so that the nominal IF (should a signal appear), and the VCO, are sitting in the center of the IF filter passband. Therefore, even if the LO drifts high by +2.0MC13011 Mz, the signal will not be significantly attenuated by the filter. When the acquisition circuit detects the appearance of a signal, beat notes are produced at the output of the demodulators, a sweep generator is switched on, and immediately sweeps the VCO an addi- tional 2.0 MHz from its out of lock nominal frequency. During this negative sweep, the PLL phase detector is switched off so phase lock cannot be obtained. The VCO is then swept positive from 2.0 MHz to + 2.0 MHz of nominal with the phase detector switched on. The PLL will therefore lock to the first carrier it encounters. This in fact must be the vision carrier because the sound carrier is more negative than ~2.0 MHz from nominal and the adjacent sound carrier is higher than the vision carrier. On achieving phase lock, the AFT clamp is released, the VCO offset is slowly removed, the sweep is inhibited and the phase detector remains enabled. With the AFT clamp removed, a large error voltage appears at the AFT output, driving the system back towards the correct frequency. Since the LO loop is slow and the VCO is fast, the IF changes slowly and the VCO tracks it, maintaining phase lock until the final static conditions are reached. For large frequency errors dur- ing this period the slew rate of the LO loop is increased, but not to the extent where it would cause any VCO tracking problems. This technique allows the acquisi- tion time of the circuit to be considerably shortened while still using a larger than normal time constant in the LO loop. To accommodate all types of tuners and LOs, positive or negative LO drive can be selected externally by operation of the AFT switch. The AFT switch also has a third position which disconnects the drive to the tuner. Under this condition the T.V. set can be tuned in the normal manner and so appears to have a conventional type of AFT. Other PLL AFT systems can- not be manually tuned in this way having an abrupt capture characteristic when tuned, and because of this, have not gained general acceptance in industry. ALIGNMENT The alignment is very simple and cheap compared to other IF amplifier circuits, especially those using a PLL. With a CW input signal of correct picture carrier fre- quency, the LO side of the 22 k resistor in series with the loop is connected to a dc supply. The dc supply (approximately 2.5 V) is adjusted until the output of the tuner is 45.75 MHz. The VCO coil is adjusted until lock is obtained and the voltage across the 22 k resistor is FIGURE 6 THE AFT SYSTEM IN ACTION | | : | | ff ly l Typical IF Input Filter Response IF Bandpass 39.75 41.75 43.75 45.75 47.25 MHz Trap | | | | bo | 41.25 4 Adjacent 4 4 | Desired / | Adjacent 4 Properly Tuned Channel AP Os | P AS y Adjacent t Desired 4 |__ Adjacent 4 Nominal Channel with Initia! 2.0 MHz Offset AP ( P AS | | Initial nominal offset of VCO and LO (AFT). When a beat note | is detected, AFT bias is held and VCO is swept another 2.0 MHz low with phase detector inhibited, then the VCO is swept high with the phase detector active. Upon phase lock, LL the AFT clamp is removed and the initial VCO offset is slowly | removed. Capture of desired picture carrier is assured even IF | mistuned +2.0 MHz. | | | i | Desired 4 | | 4 a t 4 P Desired 4 4 AP S P AS 2.0 MHz Mistuning with Initia! 2.0 MHz Offset oO => +2.0 MHz Mistuning with Initial 2.0 MHz Offest (AA) MOTOROLA Semiconductor Products Inc.MC13011 zero. The dc supply is then removed. Note: A digital AFT up/down output having a + 30 kHz dead zone is also provided by the circuit. Again, as in the case of the analog output, the digital output polarity can be controlled externally by the AFT switch. Most pins on the IC have electrostatic protection diodes to Vcc and ground. It is therefore imperative that no pin is taken below ground or above Vcc by more than one diode drop without current limiting. FIGURE 7 ALIGNMENT CONFIGURATION cw. | Picture Carrier Tuner Input = _. 5 Filter ; Mc13011 L a 19 . 4 A | Amp | ~ Sy i] | o Vcc _ ~ 1 iF x PIVCO {18 4 : te = A | {7 ! ounter 45.75 MHz L Se OUTLINE DIMENSIONS [A-] | rz] PAAAnArAAA AA CAPD eR gl O 24 3 \4 12 t [-B- | PrP RTE RT RT he LG he GP ad Ge a 2 = TEE AEE EEA Ee + N Lf sto rs) cis RX 45 ar [ 4 Te i iS t om igh He ew] ie Lae [+ 0.2510.010@ [T]/B@ | [4]o250.010@ [T]A | 26 PL 24 PL NOTES: NOTES: 1. DIMENSIONS A AND B ARE DATUMS AND TIS A 1. CHAMFERRED CONTOUR OPTIONAL. DATUM SURFACE, 2. DIML TO CENTER OF LEADS WHEN FORMED 2, POSITIONAL TOLERANCE FOR D DIMENSION PARALLEL. {24 PLACES): 3, DIMENSIONS AND TOLERANCES PER ANSI [4] 0.25 (0.010) [T1B OIA ] Y14.5M, 1982. 4. CONTROLLING DIMENSION: INCH. * PAGES) ov . DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. , CONTROLLING DIMENSION: MILLIMETER, , DIMENSION A AND B DO NOT INCLUDE MOLD > Oan PROTRUSION. 7. MAXIMUM MOLD PROTRUSION 0.15 (0.006} PER SIDE. P SUFFIX DW SUFFIX Pee roo CERAMIC PACKAGE CASE 724- CASE 751E-01 _____ (S) MOTOROLA Semiconductor Products Inc. This page intentionally left blank.Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Typical parameters can and do vary in different applications. All operating parameters, including Typicals must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. 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Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. Literature Distribution Centers: USA: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. EUROPE: Motorola Ltd.; European Literature Centre; 88 Tanners Drive, Blakelands, Milton Keynes, MK14 5BP, England. JAPAN: Nippon Motorola Ltd.; 4-32-1, Nishi-Gotanda, Shinagawa-ku, Tokyo 141, Japan. ASIA PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. = (S) MOTOROLA 21640 PRINTED IN USA (1994) MPS/POD MC13011/D