IS61WV20488FALL IS61/64WV20488FBLL 2Mx8 HIGH-SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V/1.8V SUPPLY FEATURES High-speed access time: 8ns, 10ns, 20ns High- performance, low power CMOS process Multiple center power and ground pins for greater noise immunity TTL compatible inputs and outputs Single power supply - 1.65V-2.2V VDD (IS61WV20488FALL) - 2.4V-3.6V VDD (IS61/64WV20488FBLL) Packages available : - 44 pin TSOP (Type II) - 48 ball mini BGA (6mm x 8mm) - 54 pin TSOP (Type II) Industrial and Automotive temperature support Lead-free available Data Control for upper and lower bytes PRELIMINARY INFORMATION DECEMBER 2016 DESCRIPTION The ISSI IS61/64WV20488FALL/BLL are high-speed, 16M bit static RAMs organized as 2048K words by 8 bits. It is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields high-performance and low power consumption devices. When CS# is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs. The active LOW Write Enable (WE#) controls both writing and reading of the memory. The devices are packaged in the JEDEC standard 44-Pin TSOP (TYPE II), 48-pin mini BGA (6mm x 8mm), and 54-Pin TSOP (TYPE II).. FUNCTIONAL BLOCK DIAGRAM A0 - A20 DECODER 2048K x 8 MEMORY ARRAY VDD GND I/O 0 - I/O7 CS# or CS1#/CS2 OE# WE# I/ O DATA CIRCUIT COLUMN /IO CONTROL CIRCUIT Copyright (c) 2016 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc.- www.issi.com Rev. 0A 12/13/2016 1 IS61WV20488FALL IS61/64WV20488FBLL 48-Pin mini BGA, Single Chip Select 1 2 3 4 5 6 NC OE# A0 A1 A2 NC B NC NC A3 A4 CS# I/O0 C NC NC A5 A6 I/O1 D VSS NC A17 A7 E VDD NC NC F NC NC G NC H A18 A 48-Pin mini BGA, Dual Chip Select 1 2 3 4 5 6 NC OE# A0 A1 A2 CS2 B NC NC A3 A4 CS1# I/O0 I/O2 C NC NC A5 A6 I/O1 I/O2 I/O3 VDD D VSS NC A17 A7 I/O3 VDD A16 I/O4 VSS E VDD NC NC A16 I/O4 VSS A14 A15 I/O5 I/O6 F NC NC A14 A15 I/O5 I/O6 A19 A12 A13 WE# I/O7 G NC A19 A12 A13 WE# I/O7 A8 A9 A10 A11 A20 H A18 A8 A9 A10 A11 A20 Integrated Silicon Solution, Inc.- www.issi.com Rev. 0A 12/13/2016 A 2 IS61WV20488FALL IS61/64WV20488FBLL 44-Pin TSOP II 54-Pin TSOP II NC 1 54 NC 1 44 NC VDD 53 VSS NC 2 43 NC NC 2 3 52 A0 3 42 A20 I/O6 4 51 NC I/O5 A1 4 41 A18 VSS 5 50 VDD A2 5 40 A17 I/O7 6 49 I/O4 NC A3 6 39 A16 A4 7 48 A5 A4 7 38 A15 A3 8 47 A6 CS# 37 9 46 A7 36 OE# I/O7 A2 I/O0 8 9 A1 45 A8 I/O1 10 35 I/O6 A0 10 11 A9 VDD 11 34 VSS NC 12 44 43 VSS 12 VDD CS1# OE# 13 I/O5 VDD 13 14 42 I/O2 33 32 41 VSS I/O3 14 31 I/O4 WE# 15 40 NC WE# 15 30 A14 CS2 16 39 A20 A5 16 29 A13 A19 17 38 A10 A6 17 28 A12 A18 18 37 A11 NC A7 18 27 A11 A17 19 36 A12 A8 19 26 A10 A16 20 35 A13 A9 20 21 25 A19 34 A14 24 NC A15 I/O0 21 NC 22 I/O3 NC 22 23 NC VDD 23 33 32 I/O1 24 31 I/O2 VSS NC 25 26 30 29 NC VSS NC 27 28 NC VDD Pin Descriptions A0-A20 Address Inputs I/O0-I/O7 CS# or CS1#/CS2 OE# WE# NC VDD VSS Data Inputs/Outputs Chip Enable Input(s) Output Enable Input Write Enable Input No Connection Power Ground Integrated Silicon Solution, Inc.- www.issi.com Rev. 0A 12/13/2016 3 IS61WV20488FALL IS61/64WV20488FBLL FUNCTION DESCRIPTION SRAM is one of random access memories. Each byte or word has an address and can be accessed randomly. SRAM has three different modes supported. Each function is described below with Truth Table. STANDBY MODE Device enters standby mode when deselected (CS# HIGH). The input and output pins (I/O0-7) are placed in a high impedance state. CMOS input in this mode will maximize saving power. WRITE MODE Write operation issues with Chip selected (CS#) and Write Enable (WE#) input LOW. The input and output pins (I/O0-7) are in data input mode. Output buffers are closed during this time even if OE# is LOW. READ MODE Read operation issues with Chip selected (CS# LOW) and Write Enable (WE#) input HIGH. When OE# is LOW, output buffer turns on to make data output. Any input to I/O pins during READ mode is not permitted. In the READ mode, output buffers can be turned off by pulling OE# HIGH. In this mode, internal device operates as READ but I/Os are in a high impedance state. Since device is in READ mode, active current is used. TRUTH TABLE Mode CS# WE# OE# I/O Operation VDD Current Not Selected H X X High-Z ISB1, ISB2 Output Disabled L H H High-Z ICC,ICC1 Read L H L DOUT ICC,ICC1 Write L L X DIN ICC,ICC1 Note: 1. CS# = H means CS1#=HIGH, and CS2= LOW in Dual Chip Select Device. Integrated Silicon Solution, Inc.- www.issi.com Rev. 0A 12/13/2016 4 IS61WV20488FALL IS61/64WV20488FBLL POWER UP INITIALIZATION The device includes on-chip voltage sensor used to launch POWER-UP initialization process. When VDD reaches stable level, the device requires 150us of tPU (Power-Up Time) to complete its self-initialization process. When initialization is complete, the device is ready for normal operation. tPU 150 us Stable VDD VDD Device Initialization Device for Normal Operation 0V ABSOLUTE MAXIMUM RATINGS AND Operating Range ABSOLUTE MAXIMUM RATINGS (1) Symbol Vt erm Parameter Terminal Voltage with Respect to VSS Value -0.5 to VDD + 0.5V Unit V VDD V DD Related to VSS -0.3 to 4.0 V tStg Storage Temperature -65 to +150 PT Power Dissipation 1.0 C W Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. PIN CAPACITANCE (1) Parameter Symbol Input capacitance DQ capacitance (IO0-IO7) CIN CI/O Test Condition TA = 25C, f = 1 MHz, VDD = VDD(typ) Max Units 6 8 pF pF Note: 1. These parameters are guaranteed by design and tested by a sample basis only. OPERATING RANGE Range Industrial Automotive (A3) Ambient Temperature -40C to +85C -40C to +125C IS61WV20488FALL VDD (20ns) 1.65V - 2.2V - Integrated Silicon Solution, Inc.- www.issi.com Rev. 0A 12/13/2016 IS61WV20488FBLL VDD (8, 10ns) 2.4V - 3.6V - IS64WV20488FBLL VDD (10ns) - 2.4V - 3.6V 5 IS61WV20488FALL IS61/64WV20488FBLL AC TEST CONDITIONS (OVER THE OPERATING RANGE) Parameter Input Pulse Level Unit (1.65V~2.2V) 0V to VDD Unit (2.4V~3.6V) 0V to VDD 1.5 ns 1/2 VDD 13500 10800 1.8V 1.5 ns 1/2 VDD 319 353 3.3V Input Rise and Fall Time Output Timing Reference Level R1 (ohm) R2 (ohm) VTM (V) Output Load Conditions Refer to Figure 1 and 2 AC TEST LOADS FIGURE 1 FIGURE 2 R1 VTM TM V Zo = 50 ohm Output 50 ohm VDD/2 30 pF, Including jig and scope Integrated Silicon Solution, Inc.- www.issi.com Rev. 0A 12/13/2016 OUTPUT 5pF, Including jig and scope R2R2 6 IS61WV20488FALL IS61/64WV20488FBLL DC ELECTRICAL CHARACTERISTICS DC ELECTRICAL CHARACTERISTICS-I (OVER THE OPERATING RANGE) VDD = 1.65V - 2.2V Symbol Parameter VOH Output HIGH Voltage VOL Output LOW Voltage (1) VIH Input HIGH Voltage (1) VIL Input LOW Voltage ILI Input Leakage ILO Output Leakage Test Conditions I OH = -0.1 mA IOL = 0.1 mA GND < VIN < VDD GND < VIN < VDD, Output Disabled Min. 1.4 -- 1.4 -0.2 -1 -1 Max. -- 0.2 VDD + 0.2 0.4 1 1 Unit V V V V A A Notes: 1. VILL(min) = -1.0V AC (pulse width < 10ns). Not 100% tested. VIHH (max) = VDD + 1.0V AC (pulse width < 10ns). Not 100% tested. DC ELECTRICAL CHARACTERISTICS-I (OVER THE OPERATING RANGE) VDD = 2.4V - 3.6V Symbol Parameter VOH Output HIGH Voltage VOL Output LOW Voltage (1) VIH Input HIGH Voltage VIL(1) ILI ILO Input LOW Voltage 2.4V 2.7V 2.4V 2.7V 2.4V 2.7V 2.4V 2.7V ~ ~ ~ ~ ~ ~ ~ ~ 2.7V 3.6V 2.7V 3.6V 2.7V 3.6V 2.7V 3.6V Input Leakage Output Leakage Test Conditions V DD = Min., I OH = -1.0 mA V DD = Min., I OH = -4.0 mA V DD = Min., IOL = 2.0 mA V DD = Min., I OL = 8.0 mA VSS < VIN < VDD VSS < VIN < VDD, Output Disabled Min. 2.0 2.2 -- -- 2.0 2.0 -0.3 -0.3 -2 -2 Max. -- 0.4 0.4 VDD + 0.3 0.6 0.8 2 2 Unit V V V V A A Notes: 1. VIL(min) = -0.3V DC ; VIL(min) = -2.0V AC (pulse width 2.0ns). Not 100% tested. VIH (max) = VDD + 0.3V DC ; VIH(max) = VDD + 2.0V AC (pulse width 2.0ns). Not 100% tested. Integrated Silicon Solution, Inc.- www.issi.com Rev. 0A 12/13/2016 7 IS61WV20488FALL IS61/64WV20488FBLL POWER SUPPLY CHARACTERISTICS-II FOR POWER (1) (OVER THE OPERATING RANGE) Symbol Parameter ICC VDD Dynamic Operating Supply Current ICC1 Operating Supply Current ISB1 TTL Standby Current (TTL Inputs) ISB2 CMOS Standby Current (CMOS Inputs) Test Conditions VDD = MAX, IOU T = 0 mA, f = fMAX VDD = MAX, IOUT = 0 mA, f = 0 VDD = MAX, VIN = VIH or VIL CS# VIH , f = 0 VDD = MAX, CS# VDD - 0.2V VIN VDD - 0.2V , or VIN 0.2V , f =0 Notes: 1. 2. 3. Grade Com. Ind. Auto. Com. Ind. Auto. Com. Ind. Auto. Com. Ind. Auto. -8 Max. 90 100 80 90 40 50 30 -10 Max. 85 95 135 80 90 110 40 50 60 30 -20 Max 80 90 80 90 40 50 30 40 40 40 - 50 - Typ. (2) Unit mA mA mA mA 10 At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input line change. Typical values are measured at VDD = 3.0V/1.8V, TA = 25 C and not 100% tested. CS#=H means CS1#=HIGH, and CS2=LOW in Dual Chip Select Device Integrated Silicon Solution, Inc.- www.issi.com Rev. 0A 12/13/2016 8 IS61WV20488FALL IS61/64WV20488FBLL AC CHARACTERISTICS (OVER OPERATING RANGE) READ CYCLE AC CHARACTERISTICS Parameter Symbol Read Cycle Time Address Access Time Output Hold Time CS# Access Time OE# Access Time tRC tAA tOHA tACE tDOE OE# to High-Z Output OE# to Low-Z Output CS# to High-Z Output CS# to Low-Z Output tHZOE tLZOE tHZCE tLZCE Notes: 1. 2. -8(1) -10(1) -20(1) unit Min Min Min Max Min Max 8 2.5 - 8 8 5.5 10 2.5 - 10 10 6 20 2.5 - 20 20 8 ns ns ns ns ns 0 0 0 3 4 4 - 0 0 0 3 5 5 - 0 0 0 3 8 8 - ns ns ns ns notes 2 2 2 2 Test conditions assume signal transition times of 3 ns or less, timing reference levels of VDD/2, and output loading specified in Figure 1. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. Not 100% tested. Integrated Silicon Solution, Inc.- www.issi.com Rev. 0A 12/13/2016 9 IS61WV20488FALL IS61/64WV20488FBLL AC WAVEFORMS READ CYCLE NO. 1(1) (Address Controlled, CS# = OE# = UB# = LB# = LOW, WE# = HIGH) tRC Address tAA tOHA tOHA DQ 0 - 7 Notes: 1. PREVIOUS DATA VALID DATA VALID The device is continuously selected. READ CYCLE NO. 2(1) (OE# CONTROLLED, WE# = HIGH) tRC ADDRESS tAA tOHA tDOE OE# tHZOE tLZOE CS# tHZCS tACS DOUT Notes: 1. HIGH-Z tLZCS LOW-Z DATA VALID HIGH-Z Address is valid prior to or coincident with CS# LOW transition. Integrated Silicon Solution, Inc.- www.issi.com Rev. 0A 12/13/2016 10 IS61WV20488FALL IS61/64WV20488FBLL WRITE CYCLE AC CHARACTERISTICS Parameter Symbol -8(1) Min Max Write Cycle Time tWC tSCS 8 6.5 tAW tHA tSA tPWE1 tPWE2 tSD tHD tHZWE tLZWE CS# to Write End Address Setup Time to Write End Address Hold from Write End Address Setup Time WE# Pulse Width WE# Pulse Width (OE# = LOW) Data Setup to Write End Data Hold from Write End WE# LOW to High-Z Output WE# HIGH to Low-Z Output Notes: 1 2 3 4 5 -10(1) -20(1) unit Min Max Min Max - 10 8 - 20 12 - ns ns 6.5 0 0 6.5 8 5 - 8 0 0 8 10 6 - 12 0 0 12 17 9 - ns ns ns ns ns ns 0 2 3.5 - 0 2 4 - 0 3 9 - ns ns ns notes 2 Test conditions assume signal transition times of 3 ns or less, timing reference levels of VDD/2, and output loading specified in Figure 1. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. Not 100% tested. The internal write time is defined by the overlap of CS# = LOW, UB# or LB# = LOW, and WE# = LOW. All signals must be in valid states to initiate a Write, but anyone can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. CS#=H means CS1#=HIGH, and CS2=LOW in Dual Chip Select Device If OE# is LOW during write cycle, (WE# controlled, CS# = UB# = LB# = LOW), the minimum Write cycle time for write cycle NO.3 is the sum of tHZWE and tSD Integrated Silicon Solution, Inc.- www.issi.com Rev. 0A 12/13/2016 11 IS61WV20488FALL IS61/64WV20488FBLL AC WAVEFORMS WRITE CYCLE NO. 1(1) (CS# CONTROLLED, OE# = HIGH OR LOW) tWC ADDRESS tSCS tSA tHA CS# tAW tPWE1/2 WE# tHZWE DATA UNDEFINED DOUT HIGH-Z (1) tSD DATA UNDEFINED DIN (1) tLZWE tHD DATA IN VALID Note: 1. tHZWE is is based on the assumption when tSA=0nS after READ operation. Actual DOUT for tHZWE may not appear if OE# goes high before Write Cycle. WRITE CYCLE NO. 2(1, 2) (WE# CONTROLLED: OE# IS HIGH DURING WRITE CYCLE) tWC ADDRESS tSCS tHA CS# tAW WE# tPWE1 tSA OE# DOUT tHZOE DATA UNDEFINED HIGH-Z (1) tSD DIN DATA UNDEFINED (2) tHD DATA IN VALID Notes: 1. tHZOE is the time DOUT goes to High-Z after OE# goes high. 2. During this period, the I/Os are in output state. Do not apply input signals. Integrated Silicon Solution, Inc.- www.issi.com Rev. 0A 12/13/2016 12 IS61WV20488FALL IS61/64WV20488FBLL WRITE CYCLE NO. 3(1) (WE# CONTROLLED: OE# IS LOW DURING WRITE CYCLE) tWC ADDRESS tSCS tHA CS# tAW WE# tPWE2 tSA tHZWE DOUT DATA UNDEFINED (1) HIGH-Z tSD DIN Note: 1. DATA UNDEFINED (2) tLZWE tHD DATA IN VALID If OE# is low during write cycle, tHZWE must be met in the application. Do not apply input signal during this period. Data output from the previous READ operation will drive IO BUS. Integrated Silicon Solution, Inc.- www.issi.com Rev. 0A 12/13/2016 13 IS61WV20488FALL IS61/64WV20488FBLL DATA RETENTION CHARACTERISTICS Symbol Parameter VDR VDD for Data Retention Data Retention Current IDR Test Condition OPTION Min. VDD = 2.4V to 3.6V 2.0 Typ.(2) Max. Unit 3.6 See Data Retention Waveform V VDD = 1.65V to 2.2V 1.2 Com. - 10 30 Ind. - - 40 Auto - - 50 VDD= VDR(min), CS# VDD - 0.2V 3.6 mA tSDR Data Retention Setup Time See Data Retention Waveform 0 - - ns tRDR Recovery Time See Data Retention Waveform tRC - - ns Note: 1. 2. 3. If CS# > VDD-0.2V, all other inputs must meet this condition. CS#=H means CS1#=HIGH, and CS2=LOW in Dual Chip Select Device Typical values are measured at VDD = VDR (Min), TA = 25 C and not 100% tested. DATA RETENTION WAVEFORM (CS# CONTROLLED) tSDR Data Retention Mode tRDR VDD VDR CS# CS# > VDD - 0.2V GND Integrated Silicon Solution, Inc.- www.issi.com Rev. 0A 12/13/2016 14 IS61WV20488FALL IS61/64WV20488FBLL ORDERING INFORMATION Industrial Range: -40C to +85C, Voltage Range: 1.65V to 2.2V Speed (ns) Order Part No. Package 20 IS61WV20488FALL-20BLI mini BGA (6mm x 8mm), Single Chip Select, Lead-free 20 IS61WV20488FALL-20B2LI mini BGA (6mm x 8mm), Dual Chip Select, Lead-free 20 IS61WV20488FALL-20TLI 44-pin TSOP (Type II), Lead-free 20 IS61WV20488FALL-20T2LI 54-pin TSOP (Type II), Lead-free Industrial Range: -40C to +85C, Voltage Range: 2.4V to 3.6V Speed (ns) Order Part No. Package 8 IS61WV20488FBLL-8BI mini BGA (6mm x 8mm), Single Chip Select 8 IS61WV20488FBLL-8BLI mini BGA (6mm x 8mm), Single Chip Select, Lead-free 8 IS61WV20488FBLL-8B2I mini BGA (6mm x 8mm), Dual Chip Select 8 IS61WV20488FBLL-8B2LI mini BGA (6mm x 8mm), Dual Chip Select, Lead-free 8 IS61WV20488FBLL-8TLI 44-pin TSOP (Type II), Lead-free 8 IS61WV20488FBLL-8T2LI 54-pin TSOP (Type II), Lead-free 10 IS61WV20488FBLL-10BI mini BGA (6mm x 8mm), Single Chip Select 10 IS61WV20488FBLL-10BLI mini BGA (6mm x 8mm), Single Chip Select, Lead-free 10 IS61WV20488FBLL-10B2I mini BGA (6mm x 8mm), Dual Chip Select 10 IS61WV20488FBLL-10B2LI mini BGA (6mm x 8mm), Dual Chip Select, Lead-free 10 IS61WV20488FBLL-10TLI 44-pin TSOP (Type II), Lead-free 10 IS61WV20488FBLL-10T2LI 54-pin TSOP (Type II), Lead-free Automotive (A3) Range: -40C to +125C, Voltage Range: 2.4V to 3.6V Speed (ns) Order Part No. Package 10 IS64WV20488FBLL-10BA3 mini BGA (6mm x 8mm), Single Chip Select 10 IS64WV20488FBLL-10BLA3 mini BGA (6mm x 8mm), Single Chip Select, Lead-free 10 IS64WV20488FBLL-10B2A3 mini BGA (6mm x 8mm), Dual Chip Select 10 IS64WV20488FBLL-10B2LA3 mini BGA (6mm x 8mm), Dual Chip Select, Lead-free 10 IS64WV20488FBLL-10CTLA3 44-pin TSOP (Type II), Copper Leadframe, Lead-free 10 IS64WV20488FBLL-10CT2LA3 54-pin TSOP (Type II), Copper Leadframe, Lead-free Integrated Silicon Solution, Inc.- www.issi.com Rev. 0A 12/13/2016 15 IS61WV20488FALL IS61/64WV20488FBLL PACKAGE INFORMATION Integrated Silicon Solution, Inc.- www.issi.com Rev. 0A 12/13/2016 16 IS61WV20488FALL IS61/64WV20488FBLL Integrated Silicon Solution, Inc.- www.issi.com Rev. 0A 12/13/2016 17 IS61WV20488FALL IS61/64WV20488FBLL Integrated Silicon Solution, Inc.- www.issi.com Rev. 0A 12/13/2016 18