IS61WV20488FALL
IS61/64WV20488FBLL
Integrated Silicon Solution, Inc.- www.issi.com 1
Rev. 0A
12/13/2016
2Mx8 HIGH-SPEED ASYNCHRONOUS
CMOS STATIC RAM WITH 3.3V/1.8V SUPPLY
FEATURES
High-speed access time: 8ns, 10ns, 20ns
High- performance, low power CMOS process
Multiple center power and ground pins for
greater noise immunity
TTL compatible inputs and outputs
Single power supply
– 1.65V-2.2V VDD (IS61WV20488FALL)
– 2.4V-3.6V VDD (IS61/64WV20488FBLL)
Packages available :
- 44 pin TSOP (Type II)
- 48 ball mini BGA (6mm x 8mm)
- 54 pin TSOP (Type II)
Industrial and Automotive temperature support
Lead-free available
Data Control for upper and lower bytes
DESCRIPTION
The ISSI IS61/64WV20488FALL/BLL are high-speed, 16M
bit static RAMs organized as 2048K words by 8 bits. It is
fabricated using ISSI's high-performance CMOS technology.
This highly reliable process coupled with innovative circuit
design techniques, yields high-performance and low power
consumption devices.
When CS# is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be reduced
down with CMOS input levels. Easy memory expansion is
provided by using Chip Enable and Output Enable inputs.
The active LOW Write Enable (WE#) controls both writing
and reading of the memory.
The devices are packaged in the JEDEC standard 44-Pin
TSOP (TYPE II), 48-pin mini BGA (6mm x 8mm), and 54-Pin
TSOP (TYPE II)..
FUNCTIONAL BLOCK DIAGRAM
COLUMN I/O
CS# or
CS1#/CS2
WE#
OE#CONTROL
CIRCUIT
I/O
DATA
CIRCUIT
2048K x 8
MEMORY
ARRAY
DECODER
VDD
GND
A0 – A20
I/O0 – I/O7
Copyright © 2016 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can
reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such
applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
PRELIMINARY INFORMATION
DECEMBER 2016
IS61WV20488FALL
IS61/64WV20488FBLL
Integrated Silicon Solution, Inc.- www.issi.com 2
Rev. 0A
12/13/2016
48-Pin mini BGA, Single Chip Select 48-Pin mini BGA, Dual Chip Select
NC A0OE# A1 A2 NC
NC A3NC A4 CS# I/O0
NC A5NC A6 I/O1 I/O2
VSS A17NC A7 I/O3 VDD
VDD NCNC A16 I/O4 VSS
NC A14NC A15 I/O5 I/O6
NC A12A19 A13 WE# I/O7
A18 A9A8 A10 A11 A20
1 2 3 4 5 6
A
B
C
D
E
F
G
H
NC A0OE# A1 A2 CS2
NC A3NC A4 CS1# I/O0
NC A5NC A6 I/O1 I/O2
VSS A17NC A7 I/O3 VDD
VDD NCNC A16 I/O4 VSS
NC A14NC A15 I/O5 I/O6
NC A12A19 A13 WE# I/O7
A18 A9A8 A10 A11 A20
1 2 3 4 5 6
A
B
C
D
E
F
G
H
IS61WV20488FALL
IS61/64WV20488FBLL
Integrated Silicon Solution, Inc.- www.issi.com 3
Rev. 0A
12/13/2016
44-Pin TSOP II 54-Pin TSOP II
NC
NC
A0
A1
A2
A3
A4
CS#
I/O0
I/O1
VDD
VSS
I/O2
I/O3
WE#
A5
A6
A7
A8
A9
NC
NC
NC
NC
A20
A18
A17
A16
A15
OE#
I/O7
I/O6
VDD
VSS
I/O5
I/O4
A14
A13
A12
A11
A10
A19
NC
NC
1
2
3
4
5
6
7
8
9
10
12
11
13
14
15
16
32
31
30
29
28
27
26
25
24
23
21
22
20
19
18
17
42
41
40
39
38
37
36
35
34
33
44
43 NC
I/O6
VSS
I/O7
A4
A3
A2
A1
A0
NC
CS1#
VDD
WE#
CS2
A19
A18
A16
A15
I/O0
VDD
I/O1
NC
I/O5
VDD
I/O4
A5
A6
A7
A8
A9
OE#
NC
VSS
NC
A20
A10
A12
A13
A14
I/O3
VSS
I/O2
3
4
5
6
7
8
9
10
11
12
14
13
15
16
17
18
40
39
38
37
36
35
34
33
32
31
23
24
22
21
20
19
50
49
48
47
46
45
44
43
42
41
51
NC
VDD
NC
VSS
1
2
54
53
52
A17
A11
NC
VSS
NC
NC
VDD
NC
30
29
28
26
27
25
Pin Descriptions
A0-A20
Address Inputs
I/O0-I/O7
Data Inputs/Outputs
CS# or
CS1#/CS2
Chip Enable Input(s)
OE#
Output Enable Input
WE#
Write Enable Input
NC
No Connection
VDD
Power
VSS
Ground
IS61WV20488FALL
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Rev. 0A
12/13/2016
FUNCTION DESCRIPTION
SRAM is one of random access memories. Each byte or word has an address and can be accessed randomly. SRAM
has three different modes supported. Each function is described below with Truth Table.
STANDBY MODE
Device enters standby mode when deselected (CS# HIGH). The input and output pins (I/O0-7) are placed in a high
impedance state. CMOS input in this mode will maximize saving power.
WRITE MODE
Write operation issues with Chip selected (CS#) and Write Enable (WE#) input LOW. The input and output pins (I/O0-7)
are in data input mode. Output buffers are closed during this time even if OE# is LOW.
READ MODE
Read operation issues with Chip selected (CS# LOW) and Write Enable (WE#) input HIGH. When OE# is LOW, output
buffer turns on to make data output. Any input to I/O pins during READ mode is not permitted.
In the READ mode, output buffers can be turned off by pulling OE# HIGH. In this mode, internal device operates as
READ but I/Os are in a high impedance state. Since device is in READ mode, active current is used.
TRUTH TABLE
Mode
WE#
OE#
I/O Operation
VDD Current
Not Selected
X
X
High-Z
ISB1, ISB2
Output Disabled
H
H
High-Z
ICC,ICC1
Read
H
L
DOUT
ICC,ICC1
Write
L
X
DIN
ICC,ICC1
Note:
1. CS# = H means CS1#=HIGH, and CS2= LOW in Dual Chip Select Device.
IS61WV20488FALL
IS61/64WV20488FBLL
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Rev. 0A
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POWER UP INITIALIZATION
The device includes on-chip voltage sensor used to launch POWER-UP initialization process.
When VDD reaches stable level, the device requires 150us of tPU (Power-Up Time) to complete its self-initialization
process.
When initialization is complete, the device is ready for normal operation.
tPU 150 us
VDD
Stable VDD
0V Device Initialization Device for Normal Operation
ABSOLUTE MAXIMUM RATINGS
AND Operating Range
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Parameter
Value
Unit
Vterm
Terminal Voltage with Respect to VSS
–0.5 to VDD + 0.5V
V
VDD
VDD Related to VSS
–0.3 to 4.0
V
tStg
Storage Temperature
–65 to +150
C
PT
Power Dissipation
1.0
W
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
PIN CAPACITANCE (1)
Parameter
Symbol
Test Condition
Max
Units
Input capacitance
CIN
TA = 25°C, f = 1 MHz, VDD = VDD(typ)
6
pF
DQ capacitance (IO0–IO7)
CI/O
8
pF
Note:
1. These parameters are guaranteed by design and tested by a sample basis only.
OPERATING RANGE
Range
Ambient
Temperature
IS61WV20488FALL
VDD (20ns)
IS61WV20488FBLL
VDD (8, 10ns)
IS64WV20488FBLL
VDD (10ns)
Industrial
-40C to +85C
1.65V – 2.2V
2.4V – 3.6V
–
Automotive (A3)
-40C to +125C
–
–
2.4V – 3.6V
IS61WV20488FALL
IS61/64WV20488FBLL
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Rev. 0A
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AC TEST CONDITIONS (OVER THE OPERATING RANGE)
Parameter
Unit
(1.65V~2.2V)
Unit
(2.4V~3.6V)
Input Pulse Level
0V to VDD
0V to VDD
Input Rise and Fall Time
1.5 ns
1.5 ns
Output Timing Reference Level
½ VDD
½ VDD
R1 (ohm)
13500
319
R2 (ohm)
10800
353
VTM (V)
1.8V
3.3V
Output Load Conditions
Refer to Figure 1 and 2
AC TEST LOADS
Output
Zo = 50 ohm 50 ohm
30 pF,
Including
jig
and scope
VDD/2
R1
R2
VTM
OUTPUT 5pF,
Including
jig
and scope
R1
R2
VTM
OUTPUT 5pF,
Including
jig
and scope
FIGURE 1 FIGURE 2
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DC ELECTRICAL CHARACTERISTICS
DC ELECTRICAL CHARACTERISTICS-I
(OVER THE OPERATING RANGE)
VDD = 1.65V – 2.2V
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
VOH
Output HIGH Voltage
IOH = -0.1 mA
1.4
—
V
VOL
Output LOW Voltage
IOL = 0.1 mA
—
0.2
V
VIH
(1)
Input HIGH Voltage
1.4
VDD + 0.2
V
VIL
(1)
Input LOW Voltage
–0.2
0.4
V
ILI
Input Leakage
GND < VIN < VDD
–1
1
µA
ILO
Output Leakage
GND < VIN < VDD, Output Disabled
–1
1
µA
Notes:
1. VILL(min) = -1.0V AC (pulse width < 10ns). Not 100% tested.
VIHH (max) = VDD + 1.0V AC (pulse width < 10ns). Not 100% tested.
DC ELECTRICAL CHARACTERISTICS-I
(OVER THE OPERATING RANGE)
VDD = 2.4V – 3.6V
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
VOH
Output HIGH
Voltage
2.4V ~ 2.7V
VDD = Min., IOH = -1.0 mA
2.0
—
V
2.7V ~ 3.6V
VDD = Min., IOH = -4.0 mA
2.2
VOL
Output LOW
Voltage
2.4V ~ 2.7V
VDD = Min., IOL = 2.0 mA
—
0.4
V
2.7V ~ 3.6V
VDD = Min., IOL = 8.0 mA
—
0.4
VIH
(1)
Input HIGH Voltage
2.4V ~ 2.7V
2.0
VDD + 0.3
V
2.7V ~ 3.6V
2.0
VIL
(1)
Input LOW Voltage
2.4V ~ 2.7V
–0.3
0.6
V
2.7V ~ 3.6V
–0.3
0.8
ILI
Input Leakage
VSS < VIN < VDD
–2
2
µA
ILO
Output Leakage
VSS < VIN < VDD, Output
Disabled
–2
2
µA
Notes:
1. VIL(min) = -0.3V DC ; VIL(min) = -2.0V AC (pulse width 2.0ns). Not 100% tested.
VIH (max) = VDD + 0.3V DC ; VIH(max) = VDD + 2.0V AC (pulse width 2.0ns). Not 100% tested.
IS61WV20488FALL
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POWER SUPPLY CHARACTERISTICS-II FOR POWER
(1) (OVER THE OPERATING RANGE)
Symbol
Parameter
Test Conditions
Grade
-8
Max.
-10
Max.
-20
Max
Unit
ICC
VDD Dynamic Operating
Supply Current
VDD = MAX, IOU T = 0 mA, f = fMAX
Com.
90
85
80
mA
Ind.
100
95
90
Auto.
-
135
-
ICC1
Operating Supply
Current
VDD = MAX,
IOUT = 0 mA, f = 0
Com.
80
80
80
mA
Ind.
90
90
90
Auto.
-
110
-
ISB1
TTL Standby Current
(TTL Inputs)
VDD = MAX,
VIN = VIH or VIL
CS# ≥ VIH , f = 0
Com.
40
40
40
mA
Ind.
50
50
50
Auto.
-
60
-
ISB2
CMOS Standby Current
(CMOS Inputs)
VDD = MAX,
CS# ≥ VDD - 0.2V
VIN ≥ VDD - 0.2V , or VIN ≤ 0.2V , f
= 0
Com.
30
30
30
mA
Ind.
40
40
40
Auto.
-
50
-
Typ. (2)
10
Notes:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input line change.
2. Typical values are measured at VDD = 3.0V/1.8V, TA = 25 °C and not 100% tested.
3. CS#=H means CS1#=HIGH, and CS2=LOW in Dual Chip Select Device
IS61WV20488FALL
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AC CHARACTERISTICS
(OVER OPERATING RANGE)
READ CYCLE AC CHARACTERISTICS
Parameter
Symbol
-8(1)
-10(1)
-20(1)
unit
notes
Min
Min
Min
Max
Min
Max
Read Cycle Time
tRC
8
-
10
-
20
-
ns
Address Access Time
tAA
-
8
-
10
-
20
ns
Output Hold Time
tOHA
2.5
-
2.5
-
2.5
-
ns
CS# Access Time
tACE
-
8
-
10
-
20
ns
OE# Access Time
tDOE
-
5.5
-
6
-
8
ns
OE# to High-Z Output
tHZOE
0
4
0
5
0
8
ns
2
OE# to Low-Z Output
tLZOE
0
-
0
-
0
-
ns
2
CS# to High-Z Output
tHZCE
0
4
0
5
0
8
ns
2
CS# to Low-Z Output
tLZCE
3
-
3
-
3
-
ns
2
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of VDD/2, and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
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AC WAVEFORMS
READ CYCLE NO. 1(1) (Address Controlled, CS# = OE# = UB# = LB# = LOW, WE# = HIGH)
tRC
Address
DQ 0 - 7
tOHA tOHA
tAA
PREVIOUS DATA VALID DATA VALID
Notes:
1. The device is continuously selected.
READ CYCLE NO. 2(1) (OE# CONTROLLED, WE# = HIGH)
OE#
CS#
DOUT
tAA
ADDRESS
tRC
tOHA
tDOE
tLZOE
tACS
tLZCS
tHZOE
tHZCS
HIGH-Z DATA VALIDLOW-Z HIGH-Z
Notes:
1. Address is valid prior to or coincident with CS# LOW transition.
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WRITE CYCLE AC CHARACTERISTICS
Parameter
Symbol
-8(1)
-10(1)
-20(1)
unit
notes
Min
Max
Min
Max
Min
Max
Write Cycle Time
tWC
8
-
10
-
20
-
ns
CS# to Write End
tSCS
6.5
-
8
-
12
-
ns
Address Setup Time to Write End
tAW
6.5
-
8
-
12
-
ns
Address Hold from Write End
tHA
0
-
0
-
0
-
ns
Address Setup Time
tSA
0
-
0
-
0
-
ns
WE# Pulse Width
tPWE1
6.5
-
8
-
12
-
ns
WE# Pulse Width (OE# = LOW)
tPWE2
8
-
10
-
17
-
ns
2
Data Setup to Write End
tSD
5
-
6
-
9
-
ns
Data Hold from Write End
tHD
0
-
0
-
0
-
ns
WE# LOW to High-Z Output
tHZWE
-
3.5
-
4
-
9
ns
WE# HIGH to Low-Z Output
tLZWE
2
-
2
-
3
-
ns
Notes:
1 Test conditions assume signal transition times of 3 ns or less, timing reference levels of VDD/2, and output loading specified in Figure 1.
2 Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3 The internal write time is defined by the overlap of CS# = LOW, UB# or LB# = LOW, and WE# = LOW. All signals must be in valid states to
initiate a Write, but anyone can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or
falling edge of the signal that terminates the write.
4 CS#=H means CS1#=HIGH, and CS2=LOW in Dual Chip Select Device
5 If OE# is LOW during write cycle, (WE# controlled, CS# = UB# = LB# = LOW), the minimum Write cycle time for write cycle NO.3 is the
sum of tHZWE and tSD
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AC WAVEFORMS
WRITE CYCLE NO. 1(1) (CS# CONTROLLED, OE# = HIGH OR LOW)
ADDRESS
CS#
WE#
DOUT
DIN
tWC
tHA
tAWtPWE1/2
tSA
tHZWE tLZWE
tSD tHD
DATA IN VALID
DATA UNDEFINED HIGH-Z
DATA UNDEFINED
tSCS
(1)
(1)
Note:
1. tHZWE is is based on the assumption when tSA=0nS after READ operation. Actual DOUT for tHZWE may not appear if OE# goes high before
Write Cycle.
WRITE CYCLE NO. 2(1, 2) (WE# CONTROLLED: OE# IS HIGH DURING WRITE CYCLE)
ADDRESS
CS#
WE#
DOUT
DIN
tWC
tHA
tAW tPWE1
tSA
tHZOE
tSD tHD
DATA IN VALID
DATA UNDEFINED HIGH-Z
DATA UNDEFINED
tSCS
(1)
(2)
OE#
Notes:
1. tHZOE is the time DOUT goes to High-Z after OE# goes high.
2. During this period, the I/Os are in output state. Do not apply input signals.
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WRITE CYCLE NO. 3(1) (WE# CONTROLLED: OE# IS LOW DURING WRITE CYCLE)
ADDRESS
CS#
WE#
DOUT
DIN
tWC
tHA
tAW tPWE2
tSA tHZWE tLZWE
tSD tHD
DATA IN VALID
DATA UNDEFINED HIGH-Z
DATA UNDEFINED
tSCS
(1)
(2)
Note:
1. If OE# is low during write cycle, tHZWE must be met in the application. Do not apply input signal during this period. Data output from the
previous READ operation will drive IO BUS.
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DATA RETENTION CHARACTERISTICS
Symbol
Parameter
Test Condition
OPTION
Min.
Typ.(2)
Max.
Unit
VDR
VDD for Data
Retention
See Data Retention Waveform
VDD = 2.4V to 3.6V
2.0
3.6
V
VDD = 1.65V to 2.2V
1.2
3.6
IDR
Data Retention
Current
VDD= VDR(min),
CS# ≥ VDD – 0.2V
Com.
-
10
30
mA
Ind.
-
-
40
Auto
-
-
50
tSDR
Data Retention
Setup Time
See Data Retention Waveform
0
-
-
ns
tRDR
Recovery Time
See Data Retention Waveform
tRC
-
-
ns
Note:
1. If CS# > VDD–0.2V, all other inputs must meet this condition.
2. CS#=H means CS1#=HIGH, and CS2=LOW in Dual Chip Select Device
3. Typical values are measured at VDD = VDR (Min), TA = 25 °C and not 100% tested.
DATA RETENTION WAVEFORM (CS# CONTROLLED)
GND
CS#
VDR
VDD
CS# > VDD – 0.2V
Data Retention Mode
tSDR tRDR
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ORDERING INFORMATION
Industrial Range: -40°C to +85°C, Voltage Range: 1.65V to 2.2V
Speed (ns)
Order Part No.
Package
20
IS61WV20488FALL-20BLI
mini BGA (6mm x 8mm), Single Chip Select, Lead-free
20
IS61WV20488FALL-20B2LI
mini BGA (6mm x 8mm), Dual Chip Select, Lead-free
20
IS61WV20488FALL-20TLI
44-pin TSOP (Type II), Lead-free
20
IS61WV20488FALL-20T2LI
54-pin TSOP (Type II), Lead-free
Industrial Range: -40°C to +85°C, Voltage Range: 2.4V to 3.6V
Speed (ns)
Order Part No.
Package
8
IS61WV20488FBLL-8BI
mini BGA (6mm x 8mm), Single Chip Select
8
IS61WV20488FBLL-8BLI
mini BGA (6mm x 8mm), Single Chip Select, Lead-free
8
IS61WV20488FBLL-8B2I
mini BGA (6mm x 8mm), Dual Chip Select
8
IS61WV20488FBLL-8B2LI
mini BGA (6mm x 8mm), Dual Chip Select, Lead-free
8
IS61WV20488FBLL-8TLI
44-pin TSOP (Type II), Lead-free
8
IS61WV20488FBLL-8T2LI
54-pin TSOP (Type II), Lead-free
10
IS61WV20488FBLL-10BI
mini BGA (6mm x 8mm), Single Chip Select
10
IS61WV20488FBLL-10BLI
mini BGA (6mm x 8mm), Single Chip Select, Lead-free
10
IS61WV20488FBLL-10B2I
mini BGA (6mm x 8mm), Dual Chip Select
10
IS61WV20488FBLL-10B2LI
mini BGA (6mm x 8mm), Dual Chip Select, Lead-free
10
IS61WV20488FBLL-10TLI
44-pin TSOP (Type II), Lead-free
10
IS61WV20488FBLL-10T2LI
54-pin TSOP (Type II), Lead-free
Automotive (A3) Range: –40°C to +125°C, Voltage Range: 2.4V to 3.6V
Speed (ns)
Order Part No.
Package
10
IS64WV20488FBLL-10BA3
mini BGA (6mm x 8mm), Single Chip Select
10
IS64WV20488FBLL-10BLA3
mini BGA (6mm x 8mm), Single Chip Select, Lead-free
10
IS64WV20488FBLL-10B2A3
mini BGA (6mm x 8mm), Dual Chip Select
10
IS64WV20488FBLL-10B2LA3
mini BGA (6mm x 8mm), Dual Chip Select, Lead-free
10
IS64WV20488FBLL-10CTLA3
44-pin TSOP (Type II), Copper Leadframe, Lead-free
10
IS64WV20488FBLL-10CT2LA3
54-pin TSOP (Type II), Copper Leadframe, Lead-free
IS61WV20488FALL
IS61/64WV20488FBLL
Integrated Silicon Solution, Inc.- www.issi.com 16
Rev. 0A
12/13/2016
PACKAGE INFORMATION
IS61WV20488FALL
IS61/64WV20488FBLL
Integrated Silicon Solution, Inc.- www.issi.com 17
Rev. 0A
12/13/2016
IS61WV20488FALL
IS61/64WV20488FBLL
Integrated Silicon Solution, Inc.- www.issi.com 18
Rev. 0A
12/13/2016