SIEMENS . 16x-Family of SAB 80C166W/ High-Performance CMOS 16-Bit Microcontrollers 83C166W/ 83C166W Preliminary SAB 80C166W/83C166W /83C166W 16-Bit Microcontroller High Performance 16-bit CPU with 4-Stage Pipeline 100 ns Instruction Cycle Time at 20 MHz CPU Clock 500 ns Multiplication (16 x 16 bits), 1 us Division (32 / 16 bit) Enhanced Boolean Bit Manipulation Facilities Register-Based Design with Multiple Variable Register Banks Single-Cycie Context Switching Support Up to 256 KBytes Linear Address Space for Code and Data 1 KByte On-Chip RAM 32 KBytes On-Chip ROM (SAB 83C166W only) Programmable External Bus Characteristics for Different Address Ranges 8-Bit or 16-Bit External Data Bus Multiplexed or Demultiplexed External Address/Data Buses Hold and Hold-Acknowledge Bus Arbitration Support 512 Bytes On-Chip Special Function Register Area idle and Power Down Modes 8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via Peripheral Event Controller (PEC) 16-Priority-Level Interrupt System 10-Channel 10-bit A/D Converter with 9.7 us Conversion Time 16-Channel Capture/Compare Unit Two Multi-Functional General Purpose Timer Units with 5 Timers Two Serial Channels (USARTs) Programmable Watchdog Timer Up to 76 General Purpose 1/O Lines Direct clock input without prescaler Supported by a Wealth of Development Tools like C-Compilers, Macro-Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers, Simulators, Logic Analyzer Disassemblers, Programming Boards On-Chip Bootstrap Loader 100-Pin Plastic MQFP Package (EIAJ) Semiconductor Group 655 10.94SIEMENS SAB 80C166W/83C166W Introduction The SAB 80C166W/83C166W is a representative of the Siemens SAB 80C166 family of full featured single-chip CMOS microcontrollers. It combines high CPU performance (up to 10 million instructions per second) with high peripheral functionality and enhanced |O-capabilities. These devices derive the CPU clock signal (operating clock) directly from the on-chip oscillator without using a prescaler. This reduces the devices EME. Yeo Msg XTAL1 <> Port 0 XTAL2 116 Bit RSTIN Jo Port 1 RSTOUT Nooo 168 Bit V, A\" Port 2 Viv S16 Bit SAB Nu foK, Port 3 NMI 80C166W F< 16 ai BUSACT EBCO 4 N Port 4 FBC! \o- 2 Bit / Port 5 oo Cte ee MCLOO75S Figure 1 Logic Symbol Ordering Information Type Ordering Code | Package Function SAB 83C166W-5M On Request P-MQFP-100-2 | 16-bit microcontroller, 0 C to +70 C, 1 KByte RAM and 32 KByte ROM SAB 83C166W-5M- | Q67120-D... P-MQFP-100-2 | 16-bit microcontroller, -40 C to +85 C, T3 1 KByte RAM and 32 KByte ROM SAB 83C166W-5M- | Q67120-D... P-MQFP-100-2 | 16-bit microcontroller, -40 C ta +110 C T4 1 KByte RAM and 32 KByte ROM SAB 80C166W/ On Request P-MOQFP-100-2 16-bit microcontroller, 0 C to +70 C 83C166W-M |1 KByte RAM Semiconductor Group 656SIEMENS SAB 80C166W/83C166W Type Ordering Code | Package Function SAB 80C166W/ Q67120-C864 | P-MQFP-100-2 | 16-bit microcontroller, -40 C to +85 C 83C166W-M-T3 1 KByte RAM SAB 80C166W/ Q67120-C917 | P-MQFP-100-2/ 16-bit microcontroller, -40 C to +110 C 83C166W-M-T4 | 1 KByte RAM Note: The ordering codes (Q67120-D...) for the Mask-ROM versions are defined for each product after verification of the respective ROM code. Pin Configuration Rectangular P-MQFP-100-2 (top view) _ 3/8 wSSn- S525 2SeS Bee PP ARSRE EE Sere Sefer sgeseat SRRRVSLSL LLLP RPP ek eee DASA a Ae 97 95 93 Of 89 87 8S 83 BI Pc.3/A03 80 [2 P3.0/TOIN PO.4/AD4 J 79 TF Veg PC.5/AD5 T13 [> Vs55 P0.6/aD6 C] 77 F2 2,15/0C1510/HOLO PCF /AO7 TAS [> 2,14/0C1410/HUDA Vsg 75 [2 ?2.13/0C1310/BREG Veg TF E> 92.12/CC12iC Po.8/AD8 <| 73? 2.11 /ect he Po.9/AD9 <] 9 [2 2.10/cc10'0 Pd.10/AD10 71? 72.9/c09. POAT/ADL ST 11 [2 72.8/CC8C PO.12/ADI2 SJ 63 [2 2.7/07 | PO.13/AD13 13 [? P2.6/cc6 0 ' PO.14/AD14 67 E> P2.5/C05C PO.15/a015 415 SAB 80C166W/ [> p2.4/ccac Pao/Al6 TH] 65 [2 P2.3/CC36 Pat /ai7 17 [2 P2.2/02 0 Yoo 63 (7? P2.1/CC10 XTAL2 [2 P2.0/cco'c XTALI 611? Kec __Yss BUSACT 59 2 P5.9/AN9 EBC! [2 P5.8/ ANB EBCO 57 2 P5.7/AN7 ALE [> PS.6/AN6 i RO 55? Mone ! RSTIN 4 [> Viper | RSTOUT 4 53 [2 P5.5/4N5 | AM [> P5.4/AN4 | P1.0/a0 5) 30 512 P5.3/4N3 | 310633) 35) 379 41 4B 4S? 95 | NUUCUUUY JIUOC TTT TI j BARSELLSBYRSLLAP TL BSE | SSHSRSS SRS SSSessas eee ee ee Heer are ynNgoltsY aaeacaaca aa TU TI Ira | aaacaagee* MCPO2187 Figure 2 Semiconductor Group 657SIEMENS SAB 80C166W/83C166W Pin Definitions and Functions Pin Symbol | Input (I) Function No. Output (O) 16-17 | P4.0- vO Port 4 is a 2-bit bidirectional I/O port. It is bit-wise P4.1 programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high- | impedance state. In case of an external bus configuration, Port 4 can be used to output the segment address lines: 16 0 P4.0 A16 Least Significant Segment Addr. Line 17 0 P4.4 Al7 Most Significant Segment Addr. Line 20 XTAL1 I XTAL1: Input to the oscillator amplifier and input to the internal clock generator 19 XTAL2 (O XTAL2: Output of the oscillator amplifier circuit. To clock the device from an external source, drive XTAL1, while leaving XTAL2 unconnected. Minimum and maximum high/low and rise/fall times specified in the AC Characteristics must be observed. 22 BUSACT, || External Bus Configuration seijection inputs. These pins are 23 EBC1, | sampled during reset and select either the single chip mode or 24 EBCO | one of the four external bus configurations: ; BUSACT EBC1 EBCO Mode/Bus Configuration 0 0 0 8-bit demultiplexed bus 0 0 1 8-bit multiplexed bus 0 1 0 16-bit muliplexed bus 0 4 1 16-bit demultiplexed bus 1 0 0 Single chip mode 1 ) 1 Reserved. 1 1 0 Reserved. 1 1 1 Reserved. ROMless versions must have pin BUSACT tied to 0. 27 RSTIN Reset Input with Schmitt-Trigger characteristics. A low level at this pin for a specified duration while the oscillator is running resets the SAB 80C166W/83C166W. An internal pullup resistor permits power-on reset using only a capacitor connected to Mss. 28 RSTOUT |O Internal Reset Indication Output. This pin is set to a low level when the part is executing either a hardware-, a software- or a watchdog timer reset. RSTOUT remains low until the EINIT (end of initialization) instruction is executed. Semiconductor Group 658SIEMENS SAB 80C166W/83C166W Pin Definitions and Functions (cont'd) Pin Symbol _. Input (i) Function No. Output (O) 29 NMI I Non-Maskable Interrupt Input. A high to low transition at this pin causes the CPU to vector to the NMI trap routine. When the PWRDN (power down) instruction is executed, the NMI pin must be low in order to force the SAB 80C166W/83C166W to go into power down made. If NMI is high, when PWRDN is : executed, the part will continue to run in normal mode. If not used, pull NMI high externally. 29 ALE 0 Address Latch Enable Output. Can be used for latching the address into external memory or an address latch in the multiplexed bus modes. =] a Oo 26 External Memory Read Strobe. RD is activated for every external instruction or data read access. 30-37 P1.0- VO Port 1 is a 16-bit bidirectional /O port. It is bit-wise 40-47 P1.15 programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high- impedance state. Port 1 is used as the 16-bit address bus (A) in demultiplexed bus modes and also after switching from a demultiplexed bus mode to a multiplexed bus mode.. 48 - 53 | P5.0- | Port 5 is a 10-bit input-only port with Schmitt-Trigger 56 - 59 | P5.9 I characteristics. The pins of Port 5 also serve as the (up to 10) analog input channels for the A/D converter, where P5.x equals ANx (Analog input channel x). 62-77 | P2.0 - VO Port 2 is a 16-bit bidirectional 1/O port. It is bit-wise P2.15 programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high- impedance state. The following Port 2 pins also serve for alternate functions: 62 vO P2.0 CCOlIO ==CAPCOM: CCO Cap.-in/Comp.Out 75 vO P2.13 CC13I0 CAPCOM: CC13 Cap.-In/Comp.Out, BREQ External Bus Request Output 76 | VO P2.14 CC14IO CAPCOM: CC14 Cap.-In/Comp.Out, |O HLDA External Bus Hold Acknowl. Output 77 | VO P2.15 CC151I0 CAPCOM: CC15 Cap.-In/Comp.Out, I HOLD External Bus Hold Request Input Semiconductor Group 659SIEMENS SAB 80C166W/83C166W Pin Definitions and Functions (cont'd) Pin Symbol Input(l) = Function No. Output (O) 80 - 92, | P3.0 - VO Port 3 is a 16-bit bidirectional I/O port. It is bit-wise 95-97 |P3.15 vO programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high- impedance state. The following Port 3 pins also serve for alternate functions: 80 | P3.0 TOIN CAPCOM Timer TO Count Input 81 O P3.1 T6QUT GPT2 Timer T6 Toggle Latch Output 82 I P3.2 CAPIN GPT2 Register CAPREL Capture Input 83 0 P3.3 T3O0UT GPT1 Timer T3 Toggle Latch Output 84 | P3.4 T38EUD = GPT1 Timer T3 Ext.Up/Down Ctrl. Input 85 | P3.5 T4iN GPT1 Timer T4 Input for Count/Gate/Reload/Capture 86 | P3.6 TRIN GPT1 Timer T3 Count/Gate Input 87 | P3.7 T2IN GPT1 Timer T2 Input for Count/Gate/Reload/Capture 88 0 P3.8 TxD1 ASC1 Clock/Data Output (Asyn./Syn.) 89 ie) P3.9 RxD1 ASC1 Data Input (Asyn.) or I/O (Syn.) 90 O P3.10 TxDO ASCO Clock/Data Output (Asyn./Syn.) 91 VO P3.44 RxDO ASCO Data Input (Asyn.) or I/O (Syn.) 92 0 P3.12 BHE Ext. Memory High Byte Enable Signal, 95 O P3.13 WR External Memory Write Strobe 96 I P3.14 READY Ready Signal Input 97 0 P3.15 CLKOUT System Clock Output (=CPU Clock) 98-5 | P0.0- VO Port 0 is a 16-bit bidirectional IO port. It is bit-wise 8-15 |P0.15 programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high- impedance state. In case of an external bus configuration, Port 0 serves as the address (A) and address/data (AD) bus in multiplexed bus modes and as the data (D) bus in demultiplexed bus modes. Demultiplexed bus modes: Data Path Width: 8-bit 16-bit P0.0 PO.7: DO - D7 DO - D7 P0.8 PO.15: output! D8 - D15 Multiplexed bus modes: Data Path Width: 8-bit 16-bit P0.0 PO.7: ADO AD7 ADO - AD7 PO.8 PO.15: A8 - A15 AD8 - AD15 54 Varer - Reference voltage for the A/D converter. 55 Vseno - Reference ground for the A/D converter. Semiconductor Group 660SIEMENS SAB 80C166W/83C166W Pin Definitions and Functions (cont'd) Pin Symbol | Input (1) Function No. Output (0) 7,18, | Voo - Digital Supply Voltage: 38, 61, + 5 V during norma! operation and idle mode. 79, 93 > 2.5 V during power down mode 6,21, | Mss - , Digital Ground. 39, 60, 78, 94 Semiconductor Group 661SIEMENS SAB 80C166W/83C166W Functional Description The architecture of the SAB 80C166W/83C166W combines advantages of both RISC and CISC processors and of advanced peripheral subsystems in a very well-balanced way. The following block diagram gives an overview of the different on-chip components and of the advanced, high bandwidth internal bus structure of the SAB 80C166W/83C166W. Note: All time specifications refer to a CPU clock of 20 MHz (see definition in the AC Characteristics section). | Internal 32 16 J 1 | ROM CPU~Core ee ! Area 1 16 | | | I | | _ a) EY | eo i | i YTAL > Osc. interrupt Controfler | Watchdog | i.) 1 I | I I TT I ! Dod do do fee ! dt i u | \ Ext, | [10~bit} ]USART| [USART] [| GPT1 GPT2 CAPCOM I Bus ADC asco | | asct] [-#7 ' a 16 S| Port] Icontrol| <2 cal ee-[) | | 0 3)} | 5] |S a | ls o0 BRG Bec | \j T4 1 T6 2 \.| Port I _ I I t I I Za 4 | Port 1 | Port 5 | Port 3 | Port 2 Figure 3 Block Diagram Semiconductor Group - <e ~------- 4 Bee eee a 5 Ve i ie MCBO2165, 662SIEMENS SAB 80C166W/83C166W Memory Organization The memory space of the SAB 80C166W/83C166W is configured in a Von Neumann architecture which means that code memory, data memory, registers and I/O ports are organized within the same linear address space which includes 256 KBytes. Address space expansion to 16 MBytes is provided for future versions. The entire memory space can be accessed bytewise or wordwise. Particular portions of the on-chip memory have additionally been made directly bit addressable. The SAB 83C166W contains 32 KBytes of on-chip mask-programmable ROM for code or constant data. The ROM can be mapped to either segment 0 or segment 1. 1 KByte of on-chip RAM is provided as a storage for user defined variables, for the system stack, general purpose register banks and even for code. A register bank can consist of up to 16 wordwide (RO to R15) and/or bytewide (RLO, RHO, .... RL7, RH7) so-called General Purpose Registers (GPRs). 512 bytes of the address space are reserved for the Special Function Register area. SFRs are wordwide registers which are used for controlling and monitoring functions of the different on-chip units. 98 SFRs are currently implemented. Unused SFR addresses are reserved for future members of the SAB 80C166 family. In order to meet the needs of designs where more memory is required than is provided on chip, up to 256 KBytes of external RAM and/or ROM can be connected to the microcontroller. External Bus Controller All of the external memory accesses are performed by a particular on-chip External Bus Controller (EBC). It can be programmed either to Single Chip Mode when no external memory is required, or to one of four different external memory access modes, which are as follows: 16-/18-bit Addresses, 16-bit Data, Demultiplexed 16-/18-bit Addresses, 16-bit Data, Multiplexed 16-/18-bit Addresses, 8-bit Data, Multiplexed 16-/18-bit Addresses, 8-bit Data, Demultiplexed In the demultiplexed bus modes, addresses are output on Port 1 and data is input/output on Port 0. In the multiplexed bus modes both addresses and data use Port 0 for input/output. Important timing characteristics of the external bus interface (Memory Cycle Time, Memory Tri- State Time, Read/Write Delay and Length of ALE, ie. address setup/hold time with respect to ALE) have been made programmable to allow the user the adaption of a wide range of different types of memories. In addition, different address ranges may be accessed with different bus characteristics. Access to very slow memories is supported via a particular Ready function. A HOLD/HLDA protocol is available for bus arbitration. For applications which require less than 64 KBytes of external memory space, a non-segmented memory model can be selected. In this case all memory locations can be addressed by 16 bits and Port 4 is not required to output the additional segment address lines. Semiconductor Group 663SIEMENS SAB 80C166W/83C166W Central Processing Unit (CPU) The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit (ALU) and dedicated SFRs. Additional hardware has been spent for a separate multiply and divide unit, a bit-mask generator and a barrel shifter. Based on these hardware provisions, most of the SAB 80C166W/83C166Ws instructions can be executed in just one machine cycle which requires 100 ns at 20-MHz CPU clock. For example, shift and rotate instructions are always processed during one machine cycle independent of the number of bits to be shifted. All multiple-cycle instructions have been optimized so that they can be executed very fast as well: branches in 2 cycles, a 16 x 16 bit multiplication in 5 cycles and a 32-/16 bit division in 10 cycles. Another pipeline optimization, the so-called Jump Cache, allows reducing the execution time of repeatedly performed jumps in a loop from 2 cycles to 1 cycle. The CPU disposes of an actual register cantext consisting of up to 16 wordwide GPRs which are physically allocated within the on-chip RAM area. A Context Pointer (CP) register determines the base address of the active register bank to be accessed by the CPU at a time. The number of register banks is only restricted by the available internal RAM space. For easy parameter passing, a register banks may overlap others. SP. STKOV STKUN 16 internal = f RAM R15 \ Exec.Unit Instr.Pir. Instr.Reg. General 4-Stage Purpose Internal Pipeline ROM Registers TTT WE Lib pepper tit 7S NN TITTTTTTTtrere jli/ RO , Vv BUSCON} ADDRSEL1 SYSCON MCB02166 32 KByte in the 1 KByte SAB 83C166W i Figure 4 CPU Block Diagram Semiconductor Group 664SIEMENS SAB 80C166W/83C166W A system stack of up to 512 bytes is provided as a storage for temporary data. The system stack is allocated in the on-chip RAM area, and it is accessed by the CPU via the stack pointer (SP) register. Two separate SFRs, STKOV and STKUN, are implicitly compared against the stack pointer value upon each stack access for the detection of a stack overflow or underflow. The high performance offered by the hardware implementation of the CPU can efficiently be utilized by a programmer via the highly efficient SAB 80C 166W/83C 1 66W instruction set which includes the following instruction classes: Arithmetic Instructions ~ Logical Instructions Boolean Bit Manipulation Instructions Compare and Loop Control Instructions Shift and Rotate Instructions Prioritize Instruction Data Movement Instructions System Stack Instructions Jump and Call Instructions Return Instructions System Control Instructions Miscellaneous Instructions The basic instruction length is either 2 or 4 bytes. Possible operand types are bits, bytes and words. A variety of direct, indirect or immediate addressing modes are provided to specify the required operands. Semiconductor Group 665SIEMENS SAB 80C166W/83C166W Interrupt System With an interrupt response time within a range from just 250 ns to 600 ns (in case of internal program execution), the SAB 80C166W/83C166W is capable of reacting very fast to the occurence of non-deterministic events. The architecture of the SAB 80C 166W/83C 166W supports several mechanisms for fast and flexible response to service requests that can be generated from various sources internal or external to the microcontroller. Any of these interrupt requests can be programmed to being serviced by the Interrupt Controller or by the Peripheral Event Controller (PEC). In contrast to a standard interrupt service where the current program execution is suspended and a branch to the interrupt vector table is performed, just one cycle is stolen from the current CPU activity to perform a PEC service. A PEC service implies a single byte or word data transfer between any two memory locations with an additional increment of either the PEC source or the destination pointer. An individual PEC transfer counter is implicity decremented for each PEC service except when performing in the continuous transfer mode. When this counter reaches zero, a standard interrupt is performed to the corresponding source related vector location. PEC services are very well suited, for example, for supporting the transmission or reception of blocks of data, or for transferring A/D converted results to a memory table. The SAB 80C166W/83C166W has 8 PEC channels each of which offers such fast interrupt-driven data transfer capabilities. A separate control register which contains an interrupt request flag, an interrupt enable flag and an interrupt priority bitfield exists for each of the possible interrupt sources. Via its related register, each source can be programmed to one of sixteen interrupt priority levels. Once having been accepted by the CPU, an interrupt service can only be interrupted by a higher prioritized service request. For the standard interrupt processing, each of the possible interrupt sources has a dedicated vector location. Software interrupts are supported by means of the TRAP instruction in combination with an individual trap (interrupt) number. The following table shows all of the possible SAB 80C166W/83C166W interrupt sources and the corresponding hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers: Semiconductor Group 666SIEMENS SAB 80C166W/83C166W Source of interrupt or ] Request Enable Interrupt Vector Trap PEC Service Request Flag Flag Vector Location Number CAPCOM Register 0 CCOIR CCOIE CCOINT 40, 1014 CAPCOM Register 1 CC1IR CCIE |CCIINT | 44, 14 CAPCOM Register 2 CC2IR CC2IE CC2INT | 48, 124 CAPCOM Register 3 CC3IR CC3IE | CC3INT [acy 134 CAPCOM Register 4 CCAIR CC4IE CC4INT | 50, 144 CAPCOM Register 5 CC5IR CCSIE |CCSINT 54, yo CAPCOM Register 6 CCIR CCEIE CCBINT 584 16y CAPCOM Register 7 CC7IR CC7IE CC7INT 5Cy 174 CAPCOM Register8 | CC8IR CC8IE CC8INT 60, 18 OO CAPCOM Register 9 CC9IR CC9IE CCSINT 64, 194 CAPCOM Register 10. |CC10IR = |CC1OIE | CCIOINT | 68, 1Ay CAPCOM Register 11 |CC11IR_s (CCIE. | CCTIINT. | 6Cy, 1By CAPCOM Register12.|CC12IR_ | CC12IE_ | CC12INT_ | 704 Cy CAPCOM Register 13. |CC13IR_ [CC13IE CCI3INT 74, 1Dy CAPCOM Register 14. /CC14IR_-|CCI4IE_ CCI4INT | 78, 1Ey. CAPCOM Register 15. CC15IR_ | CC15IE.- | CCI5INT | 7Cy 1Fy CAPCOM TimerO =TOIR TOIE ~*| TOINT 80, 204 CAPCOM Timer 1 THR THE T1INT | 844, 244 GPT1 Timer 2 | T2IR T2IE T2INT ' 88, 224 GPT1 Timer 3 T3IR T3IE *| TSINT 8Cy 234 GPT1 Timer 4 | T4IR T4le T4INT 904 244 GPT2 Timer 5 TSIR TSIE TSINT 9444 254 GPT2 Timer 6 TIR T6IE T6INT - | 984 264 GPT2 CAPREL Register | CRIR CRIE CRINT 9Cy 274 A/D Conversion Complete | ADCIR ADCIE | ADCINT | AO, 284, AD OverrunEror | ADEIR ADEIE ADEINT | Ady, 294; ASCO Transmit ~ | SOTIR SOTIE SOTINT | A8y 2Ay ASCO Receive SORIR SORIE SORINT | ACy 2B, ASCO Error SOEIR SOEIE SOEINT | BO, 2Cy ASC1 Transmit SITIR SITIE SITINT =| Bay, 2Dy ASC1 Receive SIRIR SIRIE SIRINT | B8, 2Ey ASC1 Error 'SIEIR S1EIE S1EINT | BCy 2Fy Semiconductor Group 667SIEMENS SAB 80C166W/83C166W The SAB 80C166W/83C166W also provides an excellent mechanism to identify and to process exceptions or error conditions that arise during run-time, so-called Hardware Traps. Hardware traps cause immediate non-maskable system reaction which is similar to a standard interrupt service (branching to a dedicated vector table location). The occurence of a hardware trap is additionally signified by an individual bit in the trap flag register (TFR). Except when another higher prioritized trap service is in progress, a hardware trap will interrupt any actual program execution. In turn, hardware trap services can normally not be interrupted by standard or PEC interrupts. The following table shows all of the possible exceptions or error conditions that can arise during run- time: Exception Condition | Trap ! Trap Vector Trap | Trap | Flag | Vector Location Number : Priority Reset Functions: | Hardware Reset RESET 00004 004 IN Software Reset RESET 0000, 00, ff Watchdog Timer Overflow RESET =| 0000, 004 Hi Class A Hardware Traps: Non-Maskable Interrupt NMI NMITRAP | 0008, 02y ll Stack Overflow STKOF STOTRAP ; 0010), 044 HT] Stack Underflow STKUF STUTRAP | 0018} 064 It Class B Hardware Traps: | Undefined Opcode UNDOPC 'BTRAP 0028, OAy | Protected Instruction PRTFLT . BTRAP 0028, OAy | Fault Illegal Word Operand ILLOPA BTRAP 0028, OAy I Access illegal Instruction Access ILLINA BTRAP 0028, OAy I Illegal External Bus HILLBUS BTRAP 0028, OAy J Access ee ee Reserved | (002Cy | (OB OF] | 003Cy] Software Traps | | Any Any Current TRAP Instruction | [0000,,- | (004~7FY} | CPU | O1FCy) Priority in steps of O04, Semiconductor Group 668SIEMENS SAB 80C166W/83C166W Capture/Compare (CAPCOM) Unit The CAPCOM unit supports generation and control of timing sequences on up to 16 channels with a maximum resolution of 400 ns (@ 20 MHz CPU clock). The CAPCOM unit is typically used to handle high speed I/O tasks such as pulse and waveform generation, pulse width modulation (PMW), Digital to Analog (D/A) conversion, software timing, or time recording relative to external events. Two 16-bit timers (T0/T1) with reload registers provide two independent time bases for the capture/ compare register array. The input clock for the timers is programmable to several prescaled values of the CPU clack, or may be derived from an overflow/underflow of timer T6 in module GPT2. This provides a wide range of variation for the timer period and resolution and allows precise adjustments to the application specific requirements. In addition, an external count input for CAPCOM timer TO allows event scheduling for the capture/compare registers relative to external events. The capture/compare register array contains 16 dual purpose capture/compare registers, each of which may be individually allocated to either CAPCOM timer TO or T1, and programmed for capture or compare function. Each register has one port pin associated with it which serves as an input pin for triggering the capture function, or as an output pin to indicate the occurence of a compare event. When a capture/compare register has been selected for capture mode, the current contents of the allocated timer will be latched (captured) into the capture/compare register in response to an external event at the port pin which is associated with this register. In addition, a specific interrupt request for this capture/compare register is generated. Either a positive, a negative, or both a positive and a negative external signal transition at the pin can be selected as the triggering event. The contents of all registers which have been selected for one of the five compare modes are continuously compared with the contents of the allocated timers. When a match occurs between the timer value and the value in a capture/compare register, specific actions will be taken based on the selected compare mode. Compare Modes Function Mode 0 Interrupt-only compare mode; several compare interrupts per timer period are possible Mode 1 Pin toggles on each compare match; several compare events per timer period are possible Mode 2 Interrupt-only compare mode; only one compare interrupt per timer period is generated Mode 3 Pin set 1 on match; pin reset 0 on compare time overflow; only one compare event per timer period is generated Double Two registers operate on one pin; pin toggles on each compare match; Register Mode several compare events per timer period are possible. Semiconductor Group 669SIEMENS SAB 80C166W/83C166W CPU Clock #12" n=3...10 Reload Reg. TxREL Tx Tun [+>] Input Control GPT2 Timer T6 Over/Underflow O+> Mode o7r Sixteen (777 16 Control TT) 16-Bit 22 LL Capture Inputs (Capture -o7- Capture/ ---- Compare Outputs or "77> Compare ~~~ Compare) - Registers O+> c oe CPU Clock >[2" n=3...10 | Ty Input Control Over /Underflow | | GPT2 Timer T6 | { | tou +o <> Figure 5 CAPCOM-Unit Block Diagram Semiconductor Group Interrupt Request 16 Capture/Compare Interrupt Requests Interrupt Request Reload Reg. TyREL MCB02143SIEMENS SAB 80C166W/83C166W General Purpose Timer (GPT) Unit The GPT unit represents a very flexible multifunctional timer/counter structure which may be used for many different time related tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation, or pulse multiplication. The GPT unit incorporates five 16-bit timers which are organized in two separate modules, GPT1 and GPT2. Each timer in each module may operate independently in a number of different modes, or may be concatenated with another timer of the same module. Each of the three timers T2, T3, T4 of module GPT1 can be configured individually for one of three basic modes of operation, which are Timer, Gated Timer, and Counter Mode. In Timer Mode, the input clock for a timer is derived from the CPU clock, divided by a programmable prescaler, while Counter Mode allows a timer to be clocked in reference to external events. Pulse width or duty cycle measurement is supported in Gated Timer Mode, where the operation of a timer is controlled by the gate level on an external input pin. For these purposes, each timer has one associated port pin (TxIN) which serves as gate or clock input. The maximum resolution of the timers in module GPT1 is 400 ns (@ 20 MHz CPU clock). Lu/o Interrupt GPT1 Timer 12 Re quest CPU Clock_, 5 if T2 Tan [ ++] Node [Reload _ Control Capture _ VA CPU Clock_,. W n=3.10 13 Toggle FF Mode }->| Control tin [}>+ y/o T3EUD L. Capture , interrupt ~ Request T4 Reload VA TAIN [}-> Mode Control CPU Clock 7 nn310 >>| T30TL rf 7 T3OUT . Interrupt GPT1 Timer T4 Request u/D MCTO2163 L_ Figure 6 Block Diagram of GPT1 Semiconductor Group 671SIEMENS SAB 80C166W/83C166W The count direction (up/down) for each timer is programmable by software. For timer T3 the count direction may additionally be altered dynamically by an external signal on a port pin (T3EUD) to facilitate e. g. position tracking. Timer T3 has an output toggle latch (T3OTL) which changes its state on each timer overflow/ underflow. The state of this latch may be output on a port pin (T3OUT) e.g. for timeout monitoring of external hardware components, or may be used internally to clock timers T2 and T4 for measuring long time periods with high resolution. In addition to their basic operating modes, timers T2 and T4 may be configured as reload or capture registers for timer T3. When used as capture or reload registers, timers T2 and T4 are stopped. The contents of timer T3 is captured into T2 or T4 in response to a signal at their associated input pins (TxIN). Timer T3 is reloaded with the contents of T2 or T4 triggered either by an external signal or by a selectable state transition of its toggle latch T3OTL. When both T2 and T4 are configured to alternately reload T3 on opposite state transitions of T3OTL with the low and high times of a PWM signal, this signal can be constantly generated without software intervention. 15 y/ p CPU Clock 05" n=2...9 | Mode [>] GPT2 Timer 15 Interrupt Control x Request Clear Capture aa V TT [ } | interrupt CAPIN Request GPT2 CAPREL __ Reload __, Interrupt Voie ~ Request Toggle FF CPU Clock__ GPT2 Timer 16 [>| T6OTL LO TOUT to CAPCOM Timers weTo2164 Figure 7 Block Diagram of GPT2 Semiconductor Group 672SIEMENS SAB 80C166W/83C166W With its maximum resolution of 200 ns (@ 20 MHz), the GPT2 module provides precise event control and time measurement. It includes two timers (T5, T6) and a capture/reload register (CAPREL). Both timers can be clocked with an input clock which is derived from the CPU clock via a programmable prescaler. The count direction (up/down) for each timer is programmable by software. Concatenation of the timers is supported via the output toggle latch (T6OTL) of timer T6, which changes its state on each timer overflow/underflow. The state of this latch may be used to clock timer T5, or it may be output on a port pin (T6OUT). The overflows/underflows of timer T6 can additionally be used to clock the CAPCOM timers TO or T1, and to cause a reload from the CAPREL register. The CAPREL register may capture the contents of timer T5 based on an external signal transition on the corresponding port pin (CAPIN), and timer T5 may optionally be cleared after the capture procedure. This allows absolute time differences to be measured or pulse multiplication to be performed without software overhead. A/D Converter For analog signal measurement, a 10-bit A/D converter with 10 multiplexed input channels and a sample and hold circuit has been integrated on-chip. It uses the method of successive approximation. The sample time (for loading the capacitors) and the conversion time adds up to 9.7 us @ 20 MHz CPU clock. Overrun error detection/protection is provided for the conversion result register (ADDAT): an interrupt request will be generated when the result of a previous conversion has not been read from the result register at the time the next conversion is complete. For applications which require less than 10 analog input channels, the remaining channel inputs can be used as digital input port pins. The A/D converter of the SAB 80C 166W/83C166W supports four different conversion modes. In the standard Single Channel conversion made, the analog level on a specified channel is sampled once and converted to a digital result. In the Single Channel Continuous mode, the analog level on a specified channel is repeatedly sampled and converted without software intervention. In the Auto Scan mode, the analog levels on a prespecified number of channels are sequentially sampled and converted. In the Auto Scan Continuous mode, the number of prespecified channels is repeatedly sampled and converted. The Peripheral Event Controller (PEC) may be used to automatically store the conversion results into a table in memory for later evaluation, without requiring the overhead of entering and exiting interrupt routines for each data transfer. Semiconductor Group 673SIEMENS SAB 80C166W/83C166W Parallel Ports The SAB 80C166W/83C 1 66W provides up to 76 I/O lines which are organized into five input/output ports and one input port. All port lines are bit-addressable, and all input/output lines are individually (bit-wise) programmable as inputs or outputs via direction registers. The I/O ports are true bidirectional ports which are switched to high impedance state when configured as inputs. During the internal reset, all port pins are configured as inputs. All port lines have programmable alternate input or output functions associated with them. Port 0 and Port 1 may be used as address and data lines when accessing external memory, while Port 4 outputs the additional segment address bits Ai17/A16 in systems where segmentation is enabled to access more than 64 KBytes of memory. Port 2 is associated with the capture inputs or compare outputs of the CAPCOM unit and/or with optional bus arbitration signals (BREQ, HLDA, HOLD). Port 3 includes alternate functions of timers, serial interfaces, optional bus control signals (WR, BHE, READY) and the system clock output (CLKOUT). Port 5 is used for the analog input channels to the A/D converter. All port lines that are not used for these alternate functions may be used as general purpose I/O lines. Serial Channels Serial communication with other microcontrollers, processors, terminals or external peripheral components is provided by two serial interfaces with identical functionality, Asynchronous/ Synchronous Serial Channels ASCO and ASC1. They are upward compatibie with the serial ports of the Siemens SAB 8051x microcontroller family and support full-duplex asynchronous communication up to 625 Kbaud and haif-duplex synchronous communication up to 2.5 Mbaud @ 20 MHz CPU clock. Two dedicated baud rate generators allow to set up all standard baud rates without oscillator tuning. For transmission, reception, and erroneous reception 3 separate interrupt vectors are provided for each serial channel. In asynchronous mode, 8- or 9-bit data frames are transmitted or received, preceded by a start bit and terminated by one or two stop bits. For multiprocessor communication, a mechanism to distinguish address from data bytes has been included (8-bit data + wake up bit mode). In synchronous mode one data byte is transmitted or received synchronously to a shift clock which is generated by the SAB 80C166W/83C166W. A loop back option is available for testing purposes. A number of optional hardware error detection capabilities has been included to increase the reliability of data transfers. A parity bit can automatically be generated on transmission or be checked on reception. Framing error detection allows to recognize data frames with missing stop bits. An overrun error will be generated, if the last character received has not been read out of the receive buffer register at the time the reception of a new character is complete. Semiconductor Group 674SIEMENS SAB 80C166W/83C166W Watchdog Timer The Watchdog Timer represents one of the fail-safe mechanisms which have been implemented to prevent the controller from malfunctioning for longer periods of time. The Watchdog Timer is always enabled after a reset of the chip, and can only be disabled in the time interval until the EINIT (end of initialization) instruction has been executed. Thus, the chips start-up procedure is always monitored. The software has to be designed to service the Watchdog Timer before it overflows. If, due to hardware or software related failures, the software fails to do so, the Watchdog Timer overflows and generates an internal hardware reset and pulls the RSTOUT pin low in order to allow external hardware components to be reset. The Watchdog Timer is a 16-bit timer, clocked with the CPU clock divided either by 2 or by 128. The high byte of the Watchdog Timer register can be set to a prespecified reload value (stored in WDTREL) in order to allow further variation of the monitored time interval. Each time it is serviced by the application software, the high byte of the Watchdog Timer is reloaded. Thus, time intervals between 25 ps and 420 ms can be monitored (@ 20 MHz CPU clock). The default Watchdog Timer interval after reset is 6.55 ms (@ 20 MHz CPU clock). Bootstrap Loader The SAB 80C166W/83C166W provides a built-in bootstrap loader (BSL), which allows to start program execution out of the SAB 80C166W/83C166W's internal RAM. This start program is loaded via the serial interface ASCO and does not require external memory or an internal ROM. The SAB 80C166W/83C166W enters BSL mode, when ALE is sampled high at the end of a hardware reset and if NMI becomes active direcily after the end of the internal reset sequence. BSL mode is entered independent of the bus mode selected via EBCO, EBC1 and BUSACT. After entering BSL mode the SAB 80C166W/83C166W scans the RXD0 line to receive a zero byte, ie. one start bit, eight 0 data bits and one stop bit. From the duration of this zero byte it calculates the corresponding baudrate factor with respect to the current CPU clock and initializes ASCO accordingly. Using this baudrate, an acknowledge byte is returned to the host that provides the loaded data. The SAB 80C166W/83C166W returns the value <55,)>. The next 32 bytes received via ASCO are stored sequentially into locations OFA40,, through OFA5F,, of the internal RAM. To execute the loaded code the BSL then jumps to location OFA40,,. The loaded program may load additional code / data, change modes, etc. The SAB 80C166W/83C166W exits BSL mode upon a software reset (ignores the ALE level) or a hardware reset (remove conditions for entering BSL mode before). instruction Set Summary The summary on the following pages lists the instructions of the SAB 80C166W/83C166W ordered into logical groups. Semiconductor Group 675SIEMENS SAB 80C166W/83C166W Instruction Set Summary Mnemonic Description Bytes Arithmetic Operations ADD Rw, Rw Add direct word GPR to direct GPR 2 ADD Rw, [Rw] Add indirect word memory to direct GPR 2 ADD Rw, [Rw +] Add indirect word memory to direct GPR and post- 2 increment source pointer by 2 ADD Rw, #data3 Add immediate word data to direct GPR 2 ADD reg, #datai6 Add immediate word data to direct register la ADD reg, mem Add direct word memory to direct register 4 ADD mem, reg Add direct word register to direct memory 4 ADDB Rb, Rb Add direct byte GPR to direct GPR 2 ADDB Rb, [Rw] Add indirect byte memory to direct GPR 2 ADDB Rb, [Rw +] Add indirect byte memory to direct GPR and 2 post-increment source pointer by 1 ADDB Rb, #data3 Add immediate byte data to direct GPR i 2 ADDB reg, #data8 Add immediate byte data to direct register 4 ADDB reg, mem Add direct byte memory to direct register 4 ADDB mem, reg Add direct byte register to direct memory 4 ADDC Rw, Rw Add direct word GPR to direct GPR with Carry 2 ADDC Rw, [Rw] Add indirect word memory to direct GPR with Carry 2 ADDC Rw, [Rw +] Add indirect word memory to direct GPR with Carry and 2 | post-increment source pointer by 2 ADDC Rw, #data3 Add immediate word data to direct GPR with Carry 2 ADDC reg, #data16 Add immediate word data to direct register with Carry 4 ADDC reg, mem ' Add direct word memory to direct register with Carry 4 ADDC mem, reg Add direct word register to direct memory with Carry 4 ADDCB Rb, Rb Add direct byte GPR to direct GPR with Carry 2 ADDCB Rb, [Rw] Add indirect byte memory to direct GPR with Carry 2 ADDCB _ Rb, [Rw +] Add indirect byte memory to direct GPR with Carry and 2 post-increment source pointer by 1 ADDCB _ Rb, #data3 | Add immediate byte data to direct GPR with Carry 2 ADDCB _ reg, #data8 Add immediate byte data to direct register with Carry 4 ADDCB reg, mem Add direct byte memory to direct register with Carry 4 Semiconductor Group 676SIEMENS SAB 80C166W/83C166W Instruction Set Summary (cont'd) Mnemonic | Description | Bytes Arithmetic Operations (cont'd) ADDCB mem, reg Add direct byte register to direct memory with Carry 4 SUB Rw, Rw Subtract direct word GPR from direct GPR 2 SUB Rw, [Rw] Subtract indirect word memory from direct GPR 2 SUB Rw, [Rw +] Subtract indirect word memory from direct GPR and 2 post-increment source pointer by 2 SUB Rw, #data3 ; Subtract immediate word data from direct GPR 2 SUB reg, #datal6 Subtract immediate word data from direct register 4 SUB reg, mem Subtract direct word memory from direct register 4 SUB mem, reg Subtract direct word register from direct memory 4 SUBB Rb, Rb Subtract direct byte GPR from direct GPR 2 SUBB Rb, [Rw] Subtract indirect byte memory from direct GPR 2 SUBB Rb, {Rw +] Subtract indirect byte memory from direct GPR and 2 post-increment source pointer by 1 SUBB Rb, #data3 Subtract immediate byte data from direct GPR 2 SUBB reg, #data8 Subtract immediate byte data from direct register 4 SUBB reg, mem | Subtract direct byte memory from direct register 4 SUBB mem, reg Subtract direct byte register fram direct memory 4 SUBC Rw, Rw Subtract direct word GPR from direct GPR with Carry 2 SUBC Rw, [Rw] Subtract indirect word memory from direct GPR with Carry | 2 SUBC Rw, [Rw +] Subtract indirect word memory from direct GPR with 2 Carry and post-increment source pointer by 2 SUBC Rw, #data3 Subtract immediate word data from direct GPR with Carry 2 SUBC reg, #data16 Subtract immediate word data from direct register with 4 Carry SUBC reg, mem Subtract direct word memory from direct register with Carry 4 SUBC mem, reg Subtract direct word register from direct memory with Carry | 4 SUBCB Rb, Rb Subtract direct byte GPR from direct GPR with Carry 2 SUBCB Rb, [Rw] Subtract indirect byte memory from direct GPR with Carry | 2 SUBCB __ Rb, [Rw +] Subtract indirect byte memory from direct GPR with Carry | 2 and post-increment source pointer by 1 SUBCB Rb, #data3 | Subtract immediate byte data from direct GPR with Carry | 2 SUBCB _ reg, #data8 | Subtract immediate byte data from direct register with Carry | 4 Semiconductor Group 677SIEMENS SAB 80C166W/83C166W Instruction Set Summary (cont'd) Mnemonic | Description Bytes Arithmetic Operations (cont'd) SUBCB reg, mem Subtract direct byte memory from direct register with Carry | 4 SUBCB mem, reg Subtract direct byte register from direct memory with Carry | 4 MUL Rw, Rw Signed multiply direct GPR by direct GPR (16-16-bit) 2 MULU Rw, Rw Unsigned multiply direct GPR by direct GPR (16-16-bit) 2 DIV Rw Signed divide register MDL by direct GPR (16-/16-bit) 2 DIVL Rw Signed long divide register MD by direct GPR (32-/16-bit) | 2 DIVLU Rw Unsigned long divide register MD by direct GPR 2 (32-/16-bit) DIVU Rw Unsigned divide register MDL by direct GPR (16-/16-bit) 2 CPL Rw Complement direct word GPR 2 CPLB Rb Complement direct byte GPR 2 NEG Rw Negate direct word GPR 2 NEGB Rb Negate direct byte GPR |2 Logical Instructions AND Rw, Rw Bitwise AND direct word GPR with direct GPR AND Rw, [Rw] Bitwise AND indirect word memory with direct GPR 2 AND Rw, (Rw +] Bitwise AND indirect word memory with direct GPR and 2 post-increment source pointer by 2 AND Rw, #data3 Bitwise AND immediate word data with direct GPR 2 AND reg, #data16 | Bitwise AND immediate word data with direct register 4 AND reg, mem Bitwise AND direct word memory with direct register 4 AND mem, reg Bitwise AND direct word register with direct memory 4 ANDB Rb, Rb Bitwise AND direct byte GPR with direct GPR 2 ANDB Rb, [Rw] Bitwise AND indirect byte memory with direct GPR 2 ANDB Rb, [Rw +] Bitwise AND indirect byte memory with direct GPR 2 and post-increment source pointer by 1 ANDB Rb, #data3 Bitwise AND immediate byte data with direct GPR 2 ANDB reg, #data8 Bitwise AND immediate byte data with direct register 4 ANDB reg, mem Bitwise AND direct byte memory with direct register 4 ANDB mem, reg Bitwise AND direct byte register with direct memory 4 Semiconductor Group 678SIEMENS SAB 80C166W/83C166W Instruction Set Summary (cont'd) Mnemonic Description | Bytes Logical Instructions (cont'd) OR Rw, Rw Bitwise OR direct word GPR with direct GPR 2 OR Rw, [Rw] Bitwise OR indirect word memory with direct GPR 2 OR Rw, [Rw +] Bitwise OR indirect word memory with direct GPR 2 and post-increment source pointer by 2 OR Rw, #data3 Bitwise OR immediate word data with direct GPR 2 OR reg, #data16 Bitwise OR immediate word data with direct register 4 OR reg, mem Bitwise OR direct word memory with direct register 4 OR mem, reg Bitwise OR direct word register with direct memory 4 ORB Rb, Rb Bitwise OR direct byte GPR with direct GPR 2 ORB Rb, [Rw] Bitwise OR indirect byte memory with direct GPR 2 ORB Rb, [Rw +] Bitwise OR indirect byte memory with direct GPR and 12 post-increment source pointer by 1 ORB Rb, #data3 Bitwise OR immediate byte data with direct GPR 2 ORB reg, #data8 Bitwise OR immediate byte data with direct register 4 ORB reg, mem Bitwise OR direct byte memory with direct register 4 ORB mem, reg Bitwise OR direct byte register with direct memory 4 XOR Rw, Rw Bitwise XOR direct word GPR with direct GPR 2 XOR Rw, [Rw] Bitwise XOR indirect word memory with direct GPR 2 XOR Rw, [Rw +] Bitwise XOR indirect word memory with direct GPR and 2 post-increment source pointer by 2 XOR Rw, #data3 Bitwise XOR immediate word data with direct GPR 2 XOR reg, #data16 Bitwise XOR immediate word data with direct register 4 XOR reg, mem Bitwise XOR direct word memory with direct register 4 XOR mem, reg Bitwise XOR direct word register with direct memory 4 XORB Rb, Rb Bitwise XOR direct byte GPR with direct GPR 2 XORB Rb, [Rw] Bitwise XOR indirect byte memory with direct GPR 2 XORB Rb, [Rw +] Bitwise XOR indirect byte memory with direct GPR and 2 post-increment source pointer by 1 XORB Rb, #data3 Bitwise XOR immediate byte data with direct GPR 2 XORB reg, #data8 Bitwise XOR immediate byte data with direct register 4 XORB reg, mem Bitwise XOR direct byte memory with direct register 4 XORB mem, reg Bitwise XOR direct byte register with direct memory 4 Semiconductor Group 679SIEMENS SAB 80C166W/83C166W Instruction Set Summary (cont'd) Mnemonic Description ! Bytes Boolean Bit Manipulation Operations BCLR _bitaddr Clear direct bit }2 BSET bitaddr Set direct bit 2 BMOV bitaddr, bitaddr | Move direct bit to direct bit 4 BMOVN _bitaddr, bitaddr | Move negated direct bit to direct bit 4 BAND bitaddr, bitaddr | AND direct bit with direct bit 4 BOR bitaddr, bitaddr | OR direct bit with direct bit 4 BXOR bitaddr, bitaddr | XOR direct bit with direct bit 4 BCMP bitaddr, bitaddr | Compare direct bit to direct bit 4 BFLDH _bitoff, #mask8, | Bitwise modify masked high byte of bit-addressable 4 #data8 direct word memory with immediate data BFLDL _bitoff, #mask8, | Bitwise modify masked low byte of bit-addressable 4 #data8 direct ward memory with immediate data CMP Rw, Rw Compare direct word GPR to direct GPR 2 CMP Rw, [Rw] Compare indirect word memory to direct GPR 2 CMP Rw, [Rw +] Compare indirect word memory to direct GPR and 2 post-increment source pointer by 2 CMP Rw, #data3 Compare immediate word data to direct GPR 2 CMP reg, #data16 Compare immediate word data to direct register 4 CMP reg, mem Compare direct ward memory to direct register 4 CMPB Rb, Rb Compare direct byte GPR to direct GPR 2 CMPB Rb, [Rw] Compare indirect byte memory to direct GPR 2 CMPB Rb, [Rw +] Compare indirect byte memory to direct GPR and 2 post-increment source pointer by 1 CMPB Rb, #data3 Compare immediate byte data to direct GPR | CMPB reg, #data8 Compare immediate byte data to direct register ; CMPB reg, mem Compare direct byte memory to direct register Compare and Loop Control instructions CMPD1__ Rw, #data4 | Compare immediate word data to direct GPR and 2 / decrement GPR by 1 CMPD1_ Rw, #data16 Compare immediate word data to direct GPR and 4 _| decrement GPR by 1 Semiconductor Group 680SIEMENS SAB 80C166W/83C166W Instruction Set Summary (cont'd) Mnemonic | Description Bytes Compare and Loop Control Instructions (cont'd) CMPD1 Rw, mem Compare direct word memory to direct GPR and 4 decrement GPR by 1 CMPD2 = Aw, #data4 Compare immediate word data to direct GPR and 2 decrement GPR by 2 CMPD2_ Rw, #data16 Compare immediate ward data to direct GPR and 4 decrement GPR by 2 CMPD2_ Rw, mem Compare direct word memory to direct GPR and 4 decrement GPR by 2 CMPH Rw, #data4 Compare immediate word data to direct GPR and 2 increment GPR by 1 CMPI1 Rw, #data16 Compare immediate word data to direct GPR and 4 increment GPR by 1 CMPI1 Rw, mem Compare direct word memory to direct GPR and 4 increment GPR by 1 CMPil2 Rw, #data4 Compare immediate word data to direct GPR and 2 increment GPR by 2 CMPI2 Rw, #data16 Compare immediate word data to direct GPR and 4 increment GPR by 2 CMPI2 Rw, mem Compare direct word memory to direct GPR and 4 increment GPR by 2 Prioritize Instruction PRIOR ~~ Rw, Rw Determine number of shift cycles to normalize direct 2 word GPR and store result in direct word GPR Shift and Rotate instructions SHL Rw, Rw Shift left direct word GPR; 2 number of shift cycles specified by direct GPR SHL Rw, #data4 Shift left direct word GPR; 2 number of shift cycles specified by immediate data SHR Rw, Rw Shift right direct word GPR; 2 number of shift cycles specified by direct GPR Semiconductor Group 681SIEMENS SAB 80C166W/83C166W Instruction Set Summary (cont'd) Mnemonic | Description | Bytes Shift and Rotate Instructions (cont'd) SHR Rw, #data4 | Shift right direct word GPR; 2 number of shift cycles specified by immediate data ROL Rw, Rw Rotate left direct word GPR; 2 number of shift cycles specified by direct GPR ROL Rw, #data4 Rotate left direct word GPR; 2 number of shift cycles specified by immediate data ROR Rw, Rw Rotate right direct word GPR; 2 number of shift cycles specified by direct GPR ROR Rw, #data4 Rotate right direct word GPR; 2 number of shift cycles specified by immediate data ASHR Rw, Rw Arithmetic (sign bit) shift right direct word GPR; 2 number of shift cycles specified by direct GPR ASHR Rw, #data4 Arithmetic (sign bit) shift right direct word GPR; 2 number of shift cycles specified by immediate data Data Movement MOV Rw, Rw Move direct word GPR to direct GPR 2 MOV Rw, #data4 Move immediate word data to direct GPR 2 MOV reg, #data16 Move immediate word data to direct register 4 MOV Rw, [Rw] Move indirect word memory to direct GPR 2 MOV Rw, [Rw+] Move indirect word memory to direct GPR and 2 | post-increment source pointer by 2 MOV [Rw], Rw Move direct word GPR to indirect memory 2 MOV [-Rw], Rw Pre-decrement destination pointer by 2 and move direct 2 word GPR to indirect memory MOV [Rw], [Rw] Move indirect word memory to indirect memory MOV {Rw+], [Rw] Move indirect word memory to indirect memory and 2 post-increment destination pointer by 2 MOV [Rw], [Rw+] Move indirect word memory to indirect memory and 2 post-increment source pointer by 2 MOV Rw, Move indirect word memory by base plus constant to 4 [Rw + #data16} | direct GPR MOV {Rw + #data16], | Move direct word GPR to indirect memory by base plus 4 Rw constant Semiconductor Group 682SIEMENS SAB 80C166W/83C166W Instruction Set Summary (cont'd) Mnemonic | Description Bytes Data Movement (cont'd) MOV [Rw], mem Move direct word memory to indirect memory 4 MOV mem, [Rw] Move indirect word memory to direct memory 4 MOV reg, mem Move direct word memory to direct register 4 MOV mem, reg Move direct word register to direct memory 4 MOVB Rb, Rb Move direct byte GPR to direct GPR 2 MOVB Rb, #data4 Move immediate byte data to direct GPR 2 MOVB reg, #data8 Move immediate byte data to direct register 4 MOVB Rb, [Rw] Move indirect byte memory to direct GPR 2 MOVB Rb, [Rw +] Move indirect byte memory to direct GPR and 2 post-increment source pointer by 1 MOVB [Rw], Rb Move direct byte GPR to indirect memory 2 MOVB [-Rw], Rb Pre-decrement destination pointer by 1 and move 2 direct byte GPR to indirect memory MOVB [Rw], [Rw] Move indirect byte memory to indirect memory MOVB (Rw +], [Rw] Move indirect byte memory to indirect memory and post-increment destination pointer by 1 MOVB [Rw], [Rw +] Move indirect byte memory to indirect memory and 2 post-increment source pointer by 1 MOVB Rb, Move indirect byte memory by base plus constant to 4 [Rw + #datai6] | direct GPR MOVB (Rw + #data16], | Move direct byte GPR to indirect memory by base plus 4 Rb constant MOVB [Rw], mem Move direct byte memory to indirect memory 4 MOVB mem, [Rw] Move indirect byte memory to direct memory 4 MOVB reg, mem Move direct byte memory to direct register 4 MOVB mem, reg Move direct byte register to direct memory 4 MOVBS Rw, Rb Move direct byte GPR with sign extension to direct 2 word GPR MOVBS _ reg, mem Move direct byte memory with sign extension to direct 4 word register MOVBS mem, reg Move direct byte register with sign extension to direct 4 word memory Semiconductor Group 683SIEMENS SAB 80C166W/83C166W Instruction Set Summary (contd) Mnemonic | Description | Bytes Data Movement (cont'd) MOVBZ Rw, Rb Move direct byte GPR with zero extension to direct 2 word GPR MOVBZ reg, mem Move direct byte memory with zero extension to direct 4 word register MOVBZ mem, reg Move direct byte register with zero extension to direct 4 word memory Jump and Call Operations JMPA cc, caddr Jump absolute if condition is met 4 JMPI cc, [Rw] Jump indirect if condition is met 2 JMPR cc, rel Jump relative if condition is met 2 JMPS seg, caddr Jump absolute to a code segment 4 JB bitaddr, rel Jump relative if direct bit is set 4 JBC bitaddr, rel Jump relative and clear bit if direct bit is set 4 JNB bitaddr, rel Jump relative if direct bit is not set 4 JNBS bitaddr, rei Jump relative and set bit if direct bit is not set i 4 CALLA cc, caddr Call absolute subroutine if condition is met 4 CALLI ce, [Rw] Call indirect subroutine if condition is met 2 CALLR rel Call relative subroutine 2 CALLS _ seg, caddr Call absolute subroutine in any code segment 4 PCALL reg, caddr Push direct word register onto system stack and call 4 absolute subroutine TRAP #trap7 Call interrupt service routine via immediate trap number 2 System Stack Operations POP reg [Pop direct word register from system stack | 2 PUSH reg Push direct word register onto system stack SCXT reg, #data16 Push direct word register onto system stack und update 4 register with immediate data SCXT reg, mem Push direct word register onto system stack und update 4 register with direct memory Semiconductor Group 684SIEMENS SAB 80C166W/83C166W Instruction Set Summary (cont'd) Mnemonic | Description Bytes Return Operations RET Return from intra-segment subroutine RETS Return from inter-segment subroutine RETP reg Return from intra-segment subroutine and pop direct word register from system stack RETI Return from interrupt service subroutine 2 System Control SRST Software Reset 4 IDLE Enter Idle Mode PWRDN Enter Power Down Mode 4 (supposes NMI-pin being low) SRVWDT Service Watchdog Timer 4 DISWDT Disable Watchdog Timer EINIT Signify End-of-Initialization on RSTOUT-pin 4 Miscellaneous NOP Null! operation 2 Semiconductor Group 685SIEMENS SAB 80C166W/83C166W Instruction Set Summary Notes Data Addressing Modes Rw: Word GPR (RO, R1, ... , R15) Rb: Byte GPR (RLO, RHO, ..., RL7, RH7) reg: SFRor GPR {in case of a byte operation on an SFR, only the low byte can be accessed via reg) mem: Direct word or byte memory location [...]: Indirect word or byte memory location (Any word GPR can be used as indirect address pointer, except for the arithmetic, lagical and compare instructions, where only RO to R3 are allowed) bitaddr: Direct bit in the bit-addressable memory area bitoft: Direct word in the bit-addressable memory area #data: Immediate constant (The number of significant bits which can be specified by the user is represented by the respective appendix 'x) #mask8: Immediate 8-bit mask used for bit-field modifications Multiply and Divide Operations The MDL and MDH registers are implicit source and/or destination operands of the multiply and divide instructions. Branch Target Addressing Modes caddr: Direct 16-bit jump target address (Updates the Instruction Pointer) seg: Direct 2-bit segment address (Updates the Code Segment Pointer) rel: Signed 8-bit jump target word offset address relative to the Instruction Pointer of the following instruction #trap7: Immediate 7-bit trap or interrupt number. Semiconductor Group 686SIEMENS SAB 80C166W/83C166W Branch Condition Codes ce: Symbolically specifiable condition codes cc_UC Unconditional cco_Z Zero cc_NZ Not Zero co _V Overflow cce_NV No Overflow cc_N Negative cc_NN Not Negative cc_C Carry cc_NC No Carry ec_EQ Equal cc_NE Not Equal ec_ULT Unsigned Less Than cc_ULE Unsigned Less Than or Equal cc_UGE Unsigned Greater Than or Equal cc_UGT Unsigned Greater Than cc_SLE Signed Less Than or Equal cc_SGE Signed Greater Than or Equal cc_SGT Signed Greater Than cc_NET Not Equal and Not End-of-Table Instruction Op Codes in Hexadecimal Order The table on the following pages lists the SAB 80C166W/83C166Ws instruction opcodes in a hexadecimal order. This table allows to find the instruction which is associated with a given opcode. Semiconductor Group 687SIEMENS SAB 80C166W/83C166W Hex- |Num- |Mnemonic | Operands Hex- |Num- |Mnemonic | Operands code | ber of code | ber of Bytes Bytes 00 2 ADD Rw, Rw 19 2 ADDCB Rb, [Rw +] or or j2 ADDB Rb, Rb Rb, [Rw] or Rb, #data3 02 4 ADD reg, mem . 1A 4 BFLDH bitoff, #mask8, 03 4 ADDB reg, mem #data8 04 |4 | ADD mem, reg 1B }2 MULU Rw, Rw 05/4 | ADDB mem, reg 1c }2 | ROL Rw, #data4 06 74 ADD reg, #datal6 ip 12) | MPR cc_NET, rel 07 |4 | ADDB reg, #datas 1E /2 | BCLR bitoff.1 08 j2 ADD Rw, [Rw +]or 4F 2 BSET bitoft.1 Rw, [Rw] or Rw, #data3 " 20 2 SUB Rw, Rw 09 j2 | ADDB Rb,[Rw+Jor 21 (2 | SUBB Rb, Ro Rb, [Rw] or 22 4 SUB reg, mem | Rb, #datas 93 [4 | SUBB feg, mem OA 4 BFLDL bitoff, #mask8, 94 4 SUB mem, reg #data8 25 4 SUBB mem, reg 0B 2 MUL Rw, Rw 26 4 SUB reg, #data6 oe |? ROL Rw, Rw 27 4 SUBB #datas reg, #data oD \2 |uMPR cc_UC, rel 9 . 28 2 SUB Rw, [Rw +] or OF 2 BSET bitoff.0 Rw, #data3 ) 10 2 ADDC Rw, Rw 29 2 SUBB Rb, [Rw +] or 1 (j2 ADDCB Rb, Rb | Rb, [Rw] or Rb, #data3 ") 12 4 ADDC reg, mem . . 2A 4 BCMP bitaddr, bitaddr 13 4 ADDCB reg, mem 2B 2 PRIOR Rw, Rw 14 4 ADDC mem, reg 15 4 ADDCB 2c 2 ROR Rw, Rw m, re me 9 2D 2 JMPR cc_EQ, rel or 16 (| 4 ADDC reg, #data16 cc_Z, rel 17 4 ADDCB reg, #data8 2E 2 BCLR bitoff.2 18 2 ADDC Rw, [Rw +]or ae la BSET bitoff.2 Rw, [Rw] or Rw, #data3 1) 30 2 SUBC Rw, Rw 31 2 SUBCB Rb, Rb 32 4 SUBC reg, mem Semiconductor Group 688SIEMENS SAB 80C166W/83C166W Hex- | Num- | Mnemonic Operands Hex- | Num- | Mnemonic Operands code | ber of code | ber of Bytes Bytes 33 4 SUBCB reg, mem 4c 2 SHL Rw, Rw 34 4 SUBC mem, reg 4D 2 JMPR cc_V, rel 35 4 SUBCB mem, reg 4E 2 BCLR bitoff.4 36 4 SUBC reg, #datai6 4F 2 BSET bitoff.4 37 4 SUBCB reg, #data8 50 2 XOR Rw, Rw 38 2 SUBC Rw, [Rw +] or 51 2 XORB Rb, Rb Rw, [Rw] or 52 4 XOR reg, mem Rw, #data3 1) 53 4 XORB reg, mem 39 2 SUBCB Rb, [Rw +] or Rb, [Rw] or 54 4 XOR mem, reg Rb, #data3 " 55 4 XORB mem, reg 3A 4 BMOVN bitaddr, bitaddr 56 4 XOR reg, #datai6 3B - - 57 4 XORB reg, #data8 3c. CO 2 ROR Rw, #data4 58 2 XOR Rw, [Rw +] or 3D 2 JMPR cc_NE, rel or Rw, [Rj or cc_NZ, rel Rw, #data3 " 3E j2 |BCLR bitoff.3 59 2 | XORB Rb, [Rw +] or a Rb, [Rw] or 3F 2 BSET _ bitoff.3 Rb, #data3 40, j2 | GMP Rw, Rw 5A |4 | BOR bitaddr, bitaddr 41/2 CMPB ) Rb, Ro 5B 2 DIVU Rw 420 \4 | MP reg, mem BC 2 ~~ |SHL Rw, #data4 430 [4 | CMPB reg, mem 5D (2 |JMPR cc_NV, rel 44 |- 5E 2 BCLR bitoff.5 450 - - 5F 2 BSET bitoff.5 46 4 CMP reg, #data16 60 2 AND Aw, Rw 47 4 CMPB reg, #data8 61 i 2 ANDB Rb, Rb 48 2 CMP Rw, [Rw +] or 62 4 AND reg, mem Rw, [Rw] or Rw, #data3 1) 63 4 ANDB reg, mem 49. |2 CMPB Rb, [Rw+]or 64 (4 | AND mem, reg Rb, [Rw] or 65 4 ANDB mem, reg Rb, #datag" ggg AND reg, #data16 4A BMOV bitaddr, bitaddr 67 4 ANDB reg, #datas 4B 2 DIV Rw Semiconductor Group 689SIEMEN Ss SAB 80C166W/83C166W Hex- | Num- | Mnemonic Operands Hex- |Num- |Mnemonic | Operands code | ber of code | ber of : Bytes Bytes 68 2 AND Rw, [Rw +] or 82 4 CMPI1 Rw, mem Rw, [Rw] or 83 . . Rw, #data3 ") 84 4 MOV [Rw], mem 69 (2 ANDB Rb, [Rw +] or Rb, [Rw] or 85: - Rb, #data3 ") 86 4 CMPI1 Rw, #data16 6A 4 BAND bitaddr, bitaddr 87 4 IDLE 6B 2 DIVL Rw 88 2 MOV i [-Rw], Rw | 6C 12 SHR Rw, Rw sg 2 MOVB [-Rw], Rb 6D 2 JMPR cc_N, rel 8A 4 JB bitaddr, rel 6E 2 ; BCLR bitoff.6 8B - - 6F 2 BSET bitoff.6 . 8C - - - 70 2 OR Rw, Rw 8D 2 JMPR cc_C, rel or 71/2 ORB Rb, Rb cc_ULT, rel 72 4 OR reg, mem 8E 2 BCLR bitoff.8 73 4 ORB reg, mem 8F 2 BSET bitoff.8 7 (4 OR mem, rag 90 2 CMPI2 Rw, #data4 75 4 ORB / mem, reg 91 | 2 CPL Rw 76 4 OR reg, #data16 92 4 CMPI2 Rw, mem 77 4 ORB reg, #data8 93 - 78/2 OR Rw, [Rw+]or 94 4 MOV mem, [Rw] Rw, [Rw] or 95 - - Rw, #datas gg ig CMPI2 Rw, #datat 79 2 ORB Rb, [Rw +] or 97 4 PWRDN Rb, [Rw] or Rb, #data3 98 }2 MOV Rw, [Rw+] 7A 4 BXOR bitaddr, biaddr 99 |2 | MOVB Rb, [Rw+] 7B 2 DIVLU Rw 9A 4 JNB bitaddr, rel 7 2 SHR Aw, #data4 9B je TRAP #trap7 7D |2 JMPR cc_NN, rel 9c 2 JMPI _c, [Rw] JE 2 BCLR bitoff.7 9D 2 JMPR cc_NC, rel or . cc_UGE, rel 7F 2 BSET bitoff.7 9E 2 BCLR bitoff.9 80 2 CMPI1 Rw, #data4 OF 2 BSET bitoff.9 81 2 NEG Rw AO 2 CMPD1 Rw, #data4 Semiconductor Group 690SIEMENS SAB 80C166W/83C166W Hex- |Num- | Mnemonic Operands Hex- |Num- | Mnemonic Operands code | ber of code | ber of Bytes Bytes Al 2 NEGB Rb C1 - - A2 4 CMPD1 Rw, mem C2 4 MOVBZ reg, mem A3 - - - C3 - - A4 4 MOVB [Rw], mem C4 4 MOV [Rw + AS |4 DISWDT Batat) Ww AG 4 CMPD1 Rw, #data16 C5 4 MOVBZ mem, reg A7 4 SRVWDT C6 4 SCXT reg, #data16 A8& 2 MOV Rw, [Rw] C7 AQ 2 MOVB Rb, [Rw] ; C8 2 MOV . [Rw], [Rw] AA 4 JBC bitaddr, rel : cg 2 MOVB [Rw], [Rw] AB 2 CALLI cc, [Rw] CA 4 CALLA cc, addr AC 2 ASHR Rw, Rw CB 2 RET AD 2 JMPR cc_SGT, rel cc 2 NOP AE 2 BCLR bitoff.10 cD 2 JMPR cc_SLT, rel AF 2 BSET bitoff.10 ; CE 2 BCLR bitoff.12 BO 2 CMPD2 Rw, #data4 ; CF 2 BSET bitoff.12 B1 2 CPLB Rb DO 2 MOVBS Rw, Rb B2 4 CMPD2 Rw, mem Dt B3 - D2 4 MOVBS reg, mem B4 4 MOVB mem, [Rw] D3 BS 4 EINIT D4 4 MOV reg, mem B6 4 CMPD2 Rw, #data16 D5 4 MOVBS mem, reg B7 4 SRST D6 4 SCXT reg, mem B8 2 MOV [Rw], Rw D7 B9 2 | MOVB [Rw], Rb D8 2 MOV [Rw+], [Rw] BA 4 JNBS bitaddr, rel D9 2 MOVB [Rw+], [Rw] BB 2 CALLR rel DA 4 CALLS seg, caddr BC 2 ASHR Rw, #data4 : DB 2 RETS BD 2 JMPR cc_SLE, rel bc BE 2 BCLR bitoff.11 BE > RSET bitoff 14 DD 2 JMPR cc_SGE, rel co 2 Mover 7 in DE 2 |BCLR bitoff.13 as DF 2 |BSET bitoff.13 Semiconductor Group 691SIEMENS SAB 80C166W/83C166W Hex- |Num- |Mnemonic | Operands Hex- | Num- | Mnemonic Operands code | ber of code | ber of Bytes Bytes EO 2 MOV Rw, #data4 FE 2 BCLR bitoff.15 E1 2 MOVB Rb, #data4 FF 2 BSET bitoff.15 E2 4 PCALL reg, caddr E3 - - - E4 4 MOVB [Rw + #data16], Rb E5 - - - E6 4 MOV reg, #data16 E7 4 MOVB reg, #data8 E8 2 MOV [Rw], [Rw+] E9 2 MOVB [Rw], [Rw+] EA 4 JMPA cc, caddr EB 2 RETP reg EC 2 PUSH reg ED 2 JMPR cc_UGT, rel EE 2 BCLR bitoff.14 EF 2 BSET bitoff.14 FO 2 MOV Rw, Rw Fi 2 MOVB Rb, Rb F2 4 MOV reg, mem F3 4 MOVB reg, mem F4 4 MOVB Rb, i [Rw + #data16] F5 - - - F6 4 MOV mem, reg F7 4 MOVB mem, reg F8 - - - F9 - - FA 4 JMPS seg, caddr FB 2 RETI FC 2 POP reg FD 2 /NMPR cc_ULE, rel Semiconductor Group 692SIEMENS SAB 80C166W/83C166W Notes 1) These instructions are encoded by means of additional bits in the operand field of the instruction X04 X7y! Rw, #data3 or Rb, #data3 x8y XBy: Rw, [Rw] or Rb, [Rw] xCy XFy: Rw, [Rw +] or Rb, [Rw +] For these instructions only the lowest four GPRs, RO to R3, can be used as indirect address pointers. Notes on the JMPR Instructions The condition code to be tested for the JMPR instructions is specified by the opcode. Two mnemonic representation alternatives exist for some of the condition codes. Notes on the BCLR and BSET Instructions The position of the bit to be set or to be cleared is specified by the opcode. The operand bitoff.n (n = 0 to 15) refers to a particular bit within a bit-addressable word. Notes on the Undefined Opcodes A hardware trap occurs when one of the undefined opcodes signified by ---- is decoded by the CPU. Semiconductor Group 693