© 2000 Fairchild Semiconductor Corporation DS006109 www .fairchildsemi.com
September 1986
Revised February 2000
DM74ALS74A Dual D Positive-Edge-Triggered Flip-Flop with Preset and Clear
DM74ALS74A
Dual D Positive-Edge-Triggered Flip-Flop
with Preset and Clear
General Descript ion
The DM74ALS74A contains two independent positive
edge-triggered flip-flops. Each flip-flop has individual D,
clock, clea r and prese t inputs, and also compl ementary Q
and Q outputs.
Informati on at input D is transf erred to the Q ou tput o n the
positive going edge of the clock pulse. Clock triggering
occurs at a voltage level of the clock pulse and is not
directly related to the transition time of the positive going
pulse. Wh en the clock in put is at either the HIGH or LOW
level, the D input signal has no effect.
Asynchronous preset and clear inputs will set or clear Q
output respectively upon the application of low level signal.
Features
■Switching specifications at 50 pF
■Switching specifications guaranteed over full tempera-
ture and VCC range
■Advanced oxide-isolated, ion-implanted Schottky TTL
process
■Functionally and pin-for-pin compatible with Schottky
and LS TTL counterpart
■Improved AC performance over LS74 at approximately
half the power
Ordering Code:
Devices also available in Tape and R eel. Speci fy by appending the s uffix let t er “X” to the o rdering c ode.
Connection Diagram Function Table
L = LOW State
H = HIGH State
X = Don't Care
↑ = Positi v e Edge Transition
Q0 = Previou s Co ndition of Q
Note 1: This condit ion is nonstable; it wil l not persist whe n preset and clear
inputs ret urn to their inac tive (HIGH) level. The ou tput levels in th is condi-
tion are not guarant eed to me et th e VOH spec if ic at ion.
Order Number Package Number Package Description
DM74ALS74AM M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
DM74ALS74ASJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
DM74ALS74AN N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Inputs Outputs
PR CLR CLK D Q Q
LHXX H L
HLXX L H
L L X X H (Note 1) H (Note 1)
HH↑HH L
HH↑LL H
HHLX Q
0Q 0