MOTOROLA
SEMICONDUCTOR TECHNICAL DATA Order Number: MC100ES7111/D
Rev 0, 12/2002
Motorola, Inc. 2002
Preliminary Information
Low Voltage 1:10 Differential
LVDS Clock Fanout Buffer
The Motorola MC100ES7111 is a LVDS differential clock fanout buffer.
Designed for most demanding clock distribution systems, the
MC100ES7111 supports various applications that require the distribution
of precisely aligned differential clock signals. Using SiGe technology and
a fully differential architecture, the device offers very low skew outputs
and superior digital signal characteristics. Target applications for this
clock driver are high performance clock distribution in computing,
networking and telecommunication systems.
Features:
•1:10 differential clock fanout buffer
•50 ps maximum device skew1
•SiGe technology
•Supports DC to 1000 MHz operation1 of clock or data signals
•LVDS compatible dif ferential clock outputs
•PECL and HSTL/LVDS compatible differential clock inputs
•3.3V power supply
•Supports industrial temperature range
•Standard 32 lead LQFP package
Functional Description
The MC100ES71 11 is designed for low skew clock distribution systems and supports clock frequencies up to 1000 MHz1. The
device accepts two clock sources. The CLK0 input accepts LVDS or HSTL compatible signals and CLK1 accepts PECL
compatible signals. The selected input signal is distributed to 10 identical, differential LVDS compatible outputs.
The output enable control is synchronized internally preventing output runt pulse generation. Outputs are only disabled or
enabled when the outputs are already in logic low state (true outputs logic low, inverted outputs logic high). The internal
synchronizer eliminates the setup and hold time requirements for the external clock enable signal. The device is packaged in a
7x7 mm2 32-lead LQFP package.
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
1. AC specifications are design targets and subject to change
MC100ES7111
LOW–VOLTAGE
1:10 DIFFERENTIAL
LVDS CLOCK
FANOUT DRIVER
FA SUFFIX
32–LEAD LQFP PACKAGE
CASE 873A
DATA SHEET
MC100ES7111
IDT™ Low Voltage 1:10 Differential LVDS Clock Fanout Buffer
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MC100ES7111
1
Low Voltage 1:10 Differential LVDS
Clock Fanout Buffer
MC100ES7111
MOTOROLA TIMING SOLUTIONS2
Q8
Q7
Q0
Q1
Figure 1. MC100ES7111 Logic Diagram
VCC
Q2
Q1
Q0
VCC
Q7
Q9
Q3
Q3
Q4
Q4
Q5
Q5
Q6
Q6
VCC
CLK_SEL
CLK0
CLK0
OE
CLK1
CLK1
GND
25
26
27
28
29
30
31
32
15
14
13
12
11
10
9
12345678
24 23 22 21 20 19 18 17 16
MC100ES7111
Figure 2. 32–Lead Package Pinout (Top View)
VCC VCC
Q9
Q8
Q2
0
1
CLK0
CLK0
CLK1
CLK1
CLK_SEL
VCC
VCC
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q4
Q5
Q5
Q6
Q6
Q7
Q7
Q8
Q8
Q9
Q9
OE
OE
Table 1. PIN CONFIGURATION
Pin I/O Type Function
CLK0, CLK0 Input HSTL/LVDS Differential HSTL or LVDS reference clock signal input
CLK1, CLK1 Input PECL Differential PECL reference clock signal input
CLK_SEL Input LVCMOS Reference clock input select
OE Input LVCMOS Output enable/disable. OE is synchronous to the input reference clock which
eliminates possible output runt pulses when the OE state is changed.
Q[0–9], Q[0–9] Output LVDS Differential clock outputs
GND Supply Negative power supply
VCC Supply Positive power supply of the device (3.3V)
Table 2. FUNCTION TABLE
Control Default 0 1
CLK_SEL 0 CLK0, CLK0 (HSTL/LVDS) is the active differential
clock input CLK1, CLK1 (PECL) is the active differential clock
input
OE 0Q[0-9], Q[0-9] are active. Deassertion of OE can
be asynchronous to the reference clock without
generation of output runt pulses.
Q[0-9] = L, Q[0-9] =H (outputs disabled). Assertion
of OE can be asynchronous to the reference clock
without generation of output runt pulses.
MC100ES7111
Low Voltage 1:10 Differential LVDS Clock Fanout Buffer NETCOM
IDT™ Low Voltage 1:10 Differential LVDS Clock Fanout Buffer
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MC100ES7111
2
MC100ES7111
TIMING SOLUTIONS 3 MOTOROLA
Table 3. Absolute Maximum Ratingsa
Symbol Characteristics Min Max Unit Condition
VCC Supply Voltage -0.3 3.9 V
VIN DC Input Voltage -0.3 VCC + 0.3 V
VOUT DC Output Voltage -0.3 VCC + 0.3 V
IIN DC Input Current ±20 mA
IOUT DC Output Current ±50 mA
TSStorage temperature -65 125 °C
TFunc Functional temperature range TA = -40 TJ = +110 °C
a. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur . Exposure to these conditions
or conditions beyond those indicated may adversely affect device reliability . Functional operation at absolute-maximum-rated conditions is not
implied.
Table 4. General Specifications
Symbol Characteristics Min Typ Max Unit Condition
MM ESD Protection (Machine model) 200 V
HBM ESD Protection (Human body model) 2000 V
CDM ESD Protection (Charged device model) TBD V
LU Latch-up immunity 200 mA
CIN Input Capacitance 4.0 pF Inputs
θJA Thermal resistance junction to ambient
JESD 51-3, single layer test board
JESD 51-6, 2S2P multilayer test board
83.1
73.3
68.9
63.8
57.4
59.0
54.4
52.5
50.4
47.8
86.0
75.4
70.9
65.3
59.6
60.6
55.7
53.8
51.5
48.8
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
Natural convection
100 ft/min
200 ft/min
400 ft/min
800 ft/min
Natural convection
100 ft/min
200 ft/min
400 ft/min
800 ft/min
θJC Thermal resistance junction to case 23.0 26.3 °C/W MIL-SPEC 883E
Method 1012.1
TJOperating junction temperaturea
(continuous operation) MTBF = 9.1 years 110 °C
a. Operating junction temperature impacts device life time. Maximum continues operating junction temperature should be selected according
to the application life time requirements (See application note AN1545 and the application section in this datasheet for more information).
The device AC and DC parameters are specified up to 110°C junction temperature allowing the MC100ES7111 to be used in applications
requiring industrial temperature range. It is recommended that users of the MC100ES7111 employ thermal modeling analysis to assist in
applying the junction temperature specifications to their particular application.
MC100ES7111
Low Voltage 1:10 Differential LVDS Clock Fanout Buffer NETCOM
IDT™ Low Voltage 1:10 Differential LVDS Clock Fanout Buffer
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MC100ES7111
3
MC100ES7111
MOTOROLA TIMING SOLUTIONS4
Table 5. DC Characteristics (VCC = 3.3V±5%, TJ = 0°C to + 110°C)a
Symbol Characteristics Min Typ Max Unit Condition
Clock input pair CLK0, CLK0 (HSTL/LVDS differential signals)
VDIF Differential input voltageb0.2 V
VX, IN Differential cross point voltagec0.25 0.68 - 0.9 VCC-1.3 V
VIH Input high voltage VX+0.1 V
VIL Input low voltage VX-0.1 V
IIN Input Current ±150 mA VIN = VX ± 0.1V
Clock input pair CLK1, CLK1 (PECL differential signals)
VPP Differential input voltaged0.15 1.0 V Differential operation
VCMR Differential cross point voltagee1.0 VCC-0.6 V Dif ferential operation
VIH Input voltage high VCC-1.165 VCC-0.880 V
VIL Input voltage low VCC-1.810 VCC-1.475 V
IIN Input Currenta±150 mA VIN = VIH or VIN
LVCMOS control inputs OE, CLK_SEL
VIL Input voltage low 0.8 V
VIH Input voltage high 2.0 V
IIN Input Current ±150 mA VIN = VIH or VIN
LVDS clock outputs (Q[0-9], Q[0-9])
VPP Output Differential Voltage (peak–to–peak) 250 mV LVDS
VOS Output Offset Voltage 1125 1275 mV LVDS
Supply current
ICC Maximum Quiescent Supply Current without
output termination current TBD TBD mA VCC pin (core)
a. DC characteristics are design targets and pending characterization.
b. VDIF (DC) is the minimum differential HSTL/LVDS input voltage swing required for device functionality.
c. VX (DC) is the crosspoint of the differential HSTL/LVDS input signal. Functional operation is obtained when the crosspoint is within the VX
(DC) range and the input swing lies within the VPP (DC) specification.
d. VPP (DC) is the minimum differential input voltage swing required to maintain device functionality.
e. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC)
range and the input swing lies within the VPP (DC) specification.
MC100ES7111
Low Voltage 1:10 Differential LVDS Clock Fanout Buffer NETCOM
IDT™ Low Voltage 1:10 Differential LVDS Clock Fanout Buffer
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MC100ES7111
4
MC100ES7111
TIMING SOLUTIONS 5 MOTOROLA
Table 6. AC Characteristics (VCC = 3.3V±5%, TJ = 0°C to + 110°C) a
Symbol Characteristics Min Typ Max Unit Condition
Clock input pair CLK0, CLK0 (HSTL/LVDS differential signals)
VDIF Differential input voltagec (peak-to-peak) 0.4 V
VX, IN Differential cross point voltaged0.68 1.275 V
fCLK Input Frequency 1000 TBD MHz
tPD Propagation Delay CLK0 to Q[0-9] TBD ps
Clock input pair CLK1, CLK1 (PECL differential signals)
VPP Differential input voltagee (peak-to-peak) 0.2 1.0 V
VCMR Differential input crosspoint voltagef1 VCC-0.6 V
fCLK Input Frequency 1000 MHz Differential
tPD Propagation Delay CLK1 to Q[0-9] TBD ps Differential
LVDS clock outputs (Q[0-9], Q[0-9])
tsk(O) Output-to-output skew 50 ps Differential
tsk(PP) Output-to-output skew (part-to-part) TBD ps Differential
tJIT(CC) Output cycle-to-cycle jitter TBD
DCOOutput duty cycle TBD 50 TBD % DCfref= 50%
tr, tfOutput Rise/Fall Time 0.05 TBD ns 20% to 80%
tPDLgOutput disable time 2.5⋅T + tPD 3.5⋅T + tPD ns T=CLK period
tPLDhOutput enable time 3⋅T + tPD 4⋅T + tPD ns T=CLK period
a. AC characteristics are design targets and pending characterization.
b. AC characteristics apply for parallel output termination of 50Ω to VTT.
c. VDIF (DC) is the minimum differential HSTL/LVDS input voltage swing required for device functionality.
d. VX (DC) is the crosspoint of the differential HSTL/LVDS input signal. Functional operation is obtained when the crosspoint is within the VX
(DC) range and the input swing lies within the VDIF (DC) specification.
e. VPP (AC) is the minimum differential PECL input voltage swing required to maintain AC characteristics including tpd and device-to- device
skew.
f. VCMR (AC) is the crosspoint of the differential HSTL input signal. Normal AC operation is obtained when the crosspoint is within the VCMR
(AC) range and the input swing lies within the VPP (AC) specification. Violation of VCMR (AC) or VPP (AC) impacts the device propagation
delay, device and part-to-part skew.
g. Propagation delay OE deassertion to differential output disabled (differential low: true output low, complementary output high).
h. Propagation delay OE assertion to output enabled (active).
MC100ES7111
Low Voltage 1:10 Differential LVDS Clock Fanout Buffer NETCOM
IDT™ Low Voltage 1:10 Differential LVDS Clock Fanout Buffer
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MC100ES7111
5
MC100ES7111
MOTOROLA TIMING SOLUTIONS6
Figure 3. MC100ES7111 AC test reference
CLKx
tPDL (OE to Qx[])
50%
tPLD (OE to Qx[])
CLKx
OE
Qx[]
Qx[] Outputs disabled
Figure 4. MC100ES7111 AC test reference
Differential
Pulse Generator
Z = 50
W
RT = 50Ω
ZO = 50Ω
DUT
MC100ES7111
VTT=GND
RT = 100Ω
ZO = 50Ω
Figure 5. MC100ES7111 AC reference
measurement waveform (HSTL input) Figure 6. MC100ES7111 AC reference
measurement waveform (PECL input)
CLK0
tPD (CLK0 to Q[0-9])
VX=0.75V
VDIF=0.6V
tPD (CLK1 to Q[0-9])
VCMR=VCC-1.3V
VPP=0.8V
CLK0
Q[0–9]
Q[0–9]
CLK1
CLK1
Q[0–9]
Q[0–9]
Figure 7. MC100ES7111 AC reference
measurement waveform (LVDS input)
CLK0
tPD (CLK0 to Q[0-9])
VX=1.2V
VDIF=0.6V
CLK0
Q[0–9]
Q[0–9]
MC100ES7111
Low Voltage 1:10 Differential LVDS Clock Fanout Buffer NETCOM
IDT™ Low Voltage 1:10 Differential LVDS Clock Fanout Buffer
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MC100ES7111
6
MC100ES7111
TIMING SOLUTIONS 7 MOTOROLA
OUTLINE DIMENSIONS
FA SUFFIX
LQFP PACKAGE
CASE 873A-02
ISSUE A
ÉÉ
ÉÉ
ÉÉ
ÉÉ
DETAIL Y
A
S1
VB
1
8
9
17
25
32
AE
AE
P
DETAIL Y
BASE
N
J
DF
METAL
SECTION AE–AE
G
SEATING
PLANE
R
Q
_
WK
X
0.250 (0.010)
GAUGE PLANE
E
C
H
DETAIL AD
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE –AB– IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.
4. DATUMS –T–, –U–, AND –Z– TO BE DETERMINED
AT DATUM PLANE –AB–.
5. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE –AC–.
6. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS
0.250 (0.010) PER SIDE. DIMENSIONS A AND B
DO INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE –AB–.
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE D DIMENSION TO EXCEED
0.520 (0.020).
8. MINIMUM SOLDER PLATE THICKNESS SHALL BE
0.0076 (0.0003).
9. EXACT SHAPE OF EACH CORNER MAY VARY
FROM DEPICTION.
DIM
AMIN MAX MIN MAX
INCHES
7.000 BSC 0.276 BSC
MILLIMETERS
B7.000 BSC 0.276 BSC
C1.400 1.600 0.055 0.063
D0.300 0.450 0.012 0.018
E1.350 1.450 0.053 0.057
F0.300 0.400 0.012 0.016
G0.800 BSC 0.031 BSC
H0.050 0.150 0.002 0.006
J0.090 0.200 0.004 0.008
K0.500 0.700 0.020 0.028
M12 REF 12 REF
N0.090 0.160 0.004 0.006
P0.400 BSC 0.016 BSC
Q1 5 1 5
R0.150 0.250 0.006 0.010
V9.000 BSC 0.354 BSC
V1 4.500 BSC 0.177 BSC
__
____
DETAIL AD
A1
B1 V1
4X
S
4X
B1 3.500 BSC 0.138 BSC
A1 3.500 BSC 0.138 BSC
S9.000 BSC 0.354 BSC
S1 4.500 BSC 0.177 BSC
W0.200 REF 0.008 REF
X1.000 REF 0.039 REF
9
–T–
–Z–
–U–
T–U0.20 (0.008) Z
AC
T–U0.20 (0.008) ZAB
0.10 (0.004) AC
–AC–
–AB–
M
_
8X
–T–, –U–, –Z–
T–U
M
0.20 (0.008) ZAC
MC100ES7111
Low Voltage 1:10 Differential LVDS Clock Fanout Buffer NETCOM
IDT™ Low Voltage 1:10 Differential LVDS Clock Fanout Buffer
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MC100ES7111
7
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PART NUMBERS
INSERT PRODUCT NAME AND DOCUMENT TITLE NETCOM
MPC92459
900 MHz Low Voltage LVDS Clock Synthesizer NETCOM
MC100ES7111
Low Voltage 1:10 Differential LVDS Clock Fanout Buffer NETCOM
