1. General description
The 74HC597; 74HCT597 is an 8-bit shift register with input flip-flops. It consists of an
8-bit storage register feeding a parallel-in, serial-out 8-bit shift register. Both the storage
register and the shift register have positive edge-triggered clocks. The shift register also
has direct load (from stor age) and clear inputs. Inputs include clamp diodes that enable
the use of curren t lim it ing resis to rs to inter fac e inputs to voltages in excess of VCC.
2. Features and benefits
Complies with JEDEC standard JESD7A
Input levels:
For 74HC597: CMOS level
For 74HCT597: TTL level
8-bit parallel sto rage register inputs
Shift register has direct overriding load and clear
ESD protection:
HBM EIA/JESD22-A114F exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V
Specified from 40 Cto+85C and from 40 Cto+125C
Multiple package options
3. Ordering information
74HC597; 74HCT597
8-bit shift register with input flip-flops
Rev. 4 — 25 February 2016 Product data sheet
Table 1. Ordering information
Type number Package
Temper ature range Name Description Version
74HC597D 40 C to +125 C SO16 plastic small outline package; 16 leads; body width
3.9 mm SOT109-1
74HCT597D
74HC597DB 40 C to +125 C SSOP16 plastic shrink small outline package; 16 leads;
body width 5.3 mm SOT338-1
74HCT597DB
74HC597PW 40 C to +125 C TSSOP16 plastic thin shrink small outline package; 16 leads;
body width 4.4 mm SOT403-1
© Nexperia B.V. 2017. All rights reserved
74HC_HCT597 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 4 — 25 February 2016 2 of 22
Nexperia 74HC597; 74HCT597
8-bit shift register with input flip-flop s
4. Functional diagram
Fig 1. Functional di agram Fig 2. Logic symbol
DDD
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Fig 3. IEC Logic symbol
DDD
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© Nexperia B.V. 2017. All rights reserved
74HC_HCT597 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 4 — 25 February 2016 3 of 22
Nexperia 74HC597; 74HCT597
8-bit shift register with input flip-flop s
Fig 4. Logic diag ram
DDD
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© Nexperia B.V. 2017. All rights reserved
74HC_HCT597 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 4 — 25 February 2016 4 of 22
Nexperia 74HC597; 74HCT597
8-bit shift register with input flip-flop s
5. Pinning information
5.1 Pinning
5.2 Pin description
Fig 5. Pin configuratio n S O16, SSOP16 and TSSOP16
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Table 2. Pin de scription
Symbol Pin Description
GND 8 ground (0 V)
Q 9 serial data output
MR 10 asynchronous master reset input (active LOW)
SHCP 11 shift register clock input (LOW-to-HIGH, edge-triggered)
STCP 12 storage register clock input (LOW-to-HIGH, edge-triggered)
PL 13 parallel load input (active LOW)
DS 14 serial data input
D0, D1, D2, D3, D4, D5, D6, D7 15, 1, 2, 3, 4, 5, 6, 7 parallel data inputs
VCC 16 supply voltage
© Nexperia B.V. 2017. All rights reserved
74HC_HCT597 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 4 — 25 February 2016 5 of 22
Nexperia 74HC597; 74HCT597
8-bit shift register with input flip-flop s
6. Functional description
[1] H = HIGH voltage level.
L = LOW voltage level.
X = don’t care.
= positive-going transition.
Table 3. Function table[1]
Inputs Function
STCP SHCP PL MR
X X X data loaded to input latches
X L H data loaded from inputs to shift register
no clock edge X L H data transferred from input flip-flops to shift register
X X L L invalid logic, state of shift register is inde te rmi n at e
when signals removed
X X H L shift register cleared
XH H shift register clocked Qn = Qn1, Q0 = DS
Fig 6. Timing diagram
DDD
6+&3
67&3
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© Nexperia B.V. 2017. All rights reserved
74HC_HCT597 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 4 — 25 February 2016 6 of 22
Nexperia 74HC597; 74HCT597
8-bit shift register with input flip-flop s
7. Limiting values
[1] For SO16 package: Ptot derates linearly with 8 mW/K above 70 C.
For SSOP16 and TSSOP16 packages: Ptot derates linearly with 5.5 mW/K above 60 C.
8. Recommended operating conditions
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage 0.5 +7 V
IIK input clamping current VI < 0.5 V or VI>V
CC +0.5 V - 20 mA
IOK output clamping current VO<0.5 V or VO>V
CC +0.5V - 20 mA
IOoutput current VO = 0.5 V to (VCC +0.5V) - 25 mA
ICC supply current - +50 mA
IGND ground current 50 - mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation SO16, SSOP16 and TSSOP16 packages [1] - 500 mW
Table 5. Re commended operating conditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter Conditions 74HC597 74HCT597 Unit
Min Typ Max Min Typ Max
VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V
VIinput voltage 0 - VCC 0-V
CC V
VOoutput voltage 0 - VCC 0-V
CC V
Tamb ambient temperature 40 +25 +125 40 +25 +125 C
t/V input transition rise and fall rate VCC = 2.0 V - - 625 - - - ns/V
VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V
VCC = 6.0 V - - 83 - - - ns/V
© Nexperia B.V. 2017. All rights reserved
74HC_HCT597 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 4 — 25 February 2016 7 of 22
Nexperia 74HC597; 74HCT597
8-bit shift register with input flip-flop s
9. Static characteristics
Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ Max Min Max Min Max
74HC597
VIH HIGH-level
input voltage VCC = 2.0 V 1.5 1.2 - 1.5 - 1.5 - V
VCC = 4.5 V 3.15 2.4 - 3.15 - 3.15 - V
VCC = 6.0 V 4.2 3.2 - 4.2 - 4.2 - V
VIL LOW-level
input voltage VCC = 2.0 V - 0.8 0.5 - 0.5 - 0.5 V
VCC = 4.5 V - 2.1 1.35 - 1.35 - 1.35 V
VCC = 6.0 V - 2.8 1.8 - 1.8 - 1.8 V
VOH HIGH-level
output voltage VI=V
IH or VIL
IO=20 A; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V
IO=20 A; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V
IO=20 A; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V
IO=4.0 mA; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V
IO=5.2 mA; VCC = 6.0 V 5.48 5.81 - 5.34 - 5.2 - V
VOL LOW-level
output voltage VI=V
IH or VIL
IO=20A; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V
IO=20A; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V
IO=20A; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V
IO= 4.0 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V
IO= 5.2 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V
IIinput leakage
current VI=V
CC or GND;
VCC =6.0V --0.1 - 1.0 - 1.0 A
ICC supply current VI=V
CC or GND; IO=0A;
VCC =6.0V - - 8.0 - 80.0 - 160.0 A
CIinput
capacitance -3.5- - - - -pF
74HCT597
VIH HIGH-level
input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - 2.0 - V
VIL LOW-level
input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 - 0.8 V
VOH HIGH-level
output voltage VI=V
IH or VIL; VCC =4.5V
IO=20 A 4.4 4.5 - 4.4 - 4.4 - V
IO=4.0 mA 3.98 4.32 - 3.84 - 3.7 - V
VOL LOW-level
output voltage VI=V
IH or VIL; VCC =4.5V
IO=20A - 0 0.1 - 0.1 - 0.1 V
IO= 4.0 mA - 0.15 0.26 - 0.33 - 0.4 V
IIinput leakage
current VI=V
CC or GND;
VCC =5.5V --0.1 - 1.0 - 1.0 A
© Nexperia B.V. 2017. All rights reserved
74HC_HCT597 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 4 — 25 February 2016 8 of 22
Nexperia 74HC597; 74HCT597
8-bit shift register with input flip-flop s
10. Dynamic characteristics
ICC supply current VI=V
CC or GND; IO=0A;
VCC =5.5V - - 8.0 - 80.0 - 160.0 A
ICC additional
supply current VI=V
CC 2.1 V;
other inputs at VCC or GND;
VCC = 4.5 V to 5.5 V;
IO=0A
per input pin; DS input - 25 90 - 112.5 - 122.5 A
per input pin; Dn inputs - 30 108 - 135 - 147 A
per input pin; PL, MR
inputs - 150 540 - 675 - 735 A
per input pin; STCP,
SHCP inputs - 150 540 - 675 - 735 A
CIinput
capacitance -3.5- - - - -pF
Table 6. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ Max Min Max Min Max
Table 7. Dy namic characteristics
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 13.
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ Max Min Max Min Max
74HC597
tpd propagation
delay SHCP to Q; see Figure 7 [1]
VCC = 2.0 V - 55 175 - 220 - 265 ns
VCC = 4.5 V - 20 35 - 44 - 53 ns
VCC = 5.0 V; CL=15pF - 17 - - - - - ns
VCC = 6.0 V - 16 30 - 37 - 45 ns
MR to Q; see Figure 8 [1]
VCC = 2.0 V - 58 175 - 220 - 265 ns
VCC = 4.5 V - 21 35 - 44 - 53 ns
VCC = 6.0 V - 17 30 - 37 - 45 ns
STCP to Q; see Figure 7 [1]
VCC = 2.0 V - 80 250 - 315 - 375 ns
VCC = 4.5 V - 29 50 - 63 - 75 ns
VCC = 5.0 V; CL=15pF - 25 - - - - - ns
VCC = 6.0 V - 23 43 - 54 - 64 ns
PL to Q; see Figure 9 [1]
VCC = 2.0 V - 69 215 - 270 - 325 ns
VCC = 4.5 V - 25 43 - 54 - 65 ns
VCC = 5.0 V; CL=15pF - 21 - - - - - ns
VCC = 6.0 V - 20 37 - 46 - 55 ns
© Nexperia B.V. 2017. All rights reserved
74HC_HCT597 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 4 — 25 February 2016 9 of 22
Nexperia 74HC597; 74HCT597
8-bit shift register with input flip-flop s
tttransition
time see Figure 9 [2]
VCC = 2.0 V - 19 75 - 95 - 110 ns
VCC = 4.5 V - 7 15 - 19 - 22 ns
VCC = 6.0 V - 6 13 - 16 - 19 ns
tWpulse width STCP HIGH or LOW;
see Figure 7
VCC = 2.0 V 80 11 - 100 - 120 - ns
VCC = 4.5 V 16 4 - 20 - 24 - ns
VCC = 6.0 V 14 3 - 17 - 20 - ns
SHCP HIGH or LOW;
see Figure 7
VCC = 2.0 V 80 14 - 100 - 120 - ns
VCC = 4.5 V 16 5 - 20 - 24 - ns
VCC = 6.0 V 14 4 - 17 - 20 - ns
MR LOW; see Figure 8
VCC = 2.0 V 80 22 - 100 - 120 - ns
VCC = 4.5 V 16 8 - 20 - 24 - ns
VCC = 6.0 V 14 6 - 17 - 20 - ns
PL LOW; see Figure 9
VCC = 2.0 V 80 22 - 100 - 120 - ns
VCC = 4.5 V 16 8 - 20 - 24 - ns
VCC = 6.0 V 14 6 - 17 - 20 - ns
trec recovery
time MR to SHCP; see
Figure 10
VCC = 2.0 V 60 3 - 75 - 90 - ns
VCC = 4.5 V 12 1 - 15 - 18 - ns
VCC = 6.0 V 10 1 - 13 - 15 - ns
Table 7. Dy namic characteristics …continued
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 13.
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ Max Min Max Min Max
© Nexperia B.V. 2017. All rights reserved
74HC_HCT597 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 4 — 25 February 2016 10 of 22
Nexperia 74HC597; 74HCT597
8-bit shift register with input flip-flop s
tsu set-up time Dn to STCP; see
Figure 11
VCC = 2.0 V 60 8 - 75 - 90 - ns
VCC = 4.5 V 12 3 - 15 - 18 - ns
VCC = 6.0 V 10 2 - 13 - 15 - ns
DS to SHCP; see
Figure 11
VCC = 2.0 V 60 11 - 75 - 90 - ns
VCC = 4.5 V 12 4 - 15 - 18 - ns
VCC = 6.0 V 10 3 - 13 - 15 - ns
PL to SHCP; see
Figure 12
VCC = 2.0 V 60 11 - 75 - 90 - ns
VCC = 4.5 V 12 4 - 15 - 18 - ns
VCC = 6.0 V 10 3 - 13 - 15 - ns
thhold time Dn to STCP; see
Figure 11
VCC = 2.0 V 5 3- 5 - 5 -ns
VCC = 4.5 V 5 1- 5 - 5 -ns
VCC = 6.0 V 5 1- 5 - 5 -ns
PL, DS to SHCP; see
Figure 11
VCC = 2.0 V 5 6- 5 - 5 -ns
VCC = 4.5 V 5 2- 5 - 5 -ns
VCC = 6.0 V 5 2- 5 - 5 -ns
fmax maximum
frequency SHCP; see Figure 7
VCC = 2.0 V 6.0 29 - 4.8 - 4.0 - MHz
VCC = 4.5 V 30 87 - 24 - 20 - MHz
VCC = 5.0 V; CL = 15 pF - 96 - - - - - MHz
VCC = 6.0 V 35 104 - 28 - 24 - MHz
CPD power
dissipation
capacitance
CL= 50 pF; f = 1 MHz;
VI=GNDtoV
CC
[3] -29- - - - -pF
Table 7. Dy namic characteristics …continued
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 13.
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ Max Min Max Min Max
© Nexperia B.V. 2017. All rights reserved
74HC_HCT597 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 4 — 25 February 2016 11 of 22
Nexperia 74HC597; 74HCT597
8-bit shift register with input flip-flop s
74HCT597
tpd propagation
delay SHCP to Q; see Figure 7 [1]
VCC = 4.5 V - 23 40 - 50 - 60 ns
VCC = 5.0 V; CL=15pF - 20 - - - - - ns
MR to Q; see Figure 8 [1]
VCC = 4.5 V - 28 49 - 61 - 74 ns
STCP to Q; see Figure 7 [1]
VCC = 4.5 V - 33 57 - 71 - 86 ns
VCC = 5.0 V; CL=15pF - 29 - - - - - ns
PL to Q; see Figure 9 [1]
VCC = 4.5 V - 30 52 - 65 - 78 ns
VCC = 5.0 V; CL=15pF - 26 - - - - - ns
tttransition
time see Figure 7 [2]
VCC = 4.5 V - 7 15 - 19 - 22 ns
tWpulse width STCP HIGH or LOW;
see Figure 7
VCC = 4.5 V 16 6 - 20 - 24 - ns
SHCP HIGH or LOW;
see Figure 7
VCC = 4.5 V 16 7 - 20 - 24 - ns
MR LOW; see Figure 8
VCC = 4.5 V 25 14 - 31 - 38 - ns
PL LOW; see Figure 9
VCC = 4.5 V 20 10 - 25 - 30 - ns
trec recovery
time MR to SHCP; see
Figure 10
VCC = 4.5 V 12 2 - 15 - 18 - ns
tsu set-up time Dn to STCP; see
Figure 11
VCC = 4.5 V 12 5 - 15 - 18 - ns
DS to SHCP; see
Figure 11
VCC = 4.5 V 12 2 - 15 - 18 - ns
PL to SHCP; see
Figure 12
VCC = 4.5 V 12 4 - 15 - 18 - ns
Table 7. Dy namic characteristics …continued
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 13.
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ Max Min Max Min Max
© Nexperia B.V. 2017. All rights reserved
74HC_HCT597 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 4 — 25 February 2016 12 of 22
Nexperia 74HC597; 74HCT597
8-bit shift register with input flip-flop s
[1] tpd is the same as tPLH and tPHL.
[2] tt is the same as tTHL and tTLH.
[3] CPD is used to determine the dynamic power dissipation (PD in W).
PD=C
PD VCC2fiN+(CLVCC2fo) where:
fi = input frequency in MHz;
fo= output frequency in MHz;
CL= output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CLVCC2fo) = sum of outputs.
11. Waveforms
thhold time Dn to STCP; see
Figure 11
VCC = 4.5 V 5 1- 5 - 5 -ns
PL, DS to SHCP; see
Figure 11
VCC = 4.5 V 5 2- 5 - 5 -ns
fmax maximum
frequency SHCP; see Figure 7
VCC = 4.5 V 30 75 - 24 - 20 - MHz
VCC = 5.0 V; CL = 15 pF - 83 - - - - - MHz
CPD power
dissipation
capacitance
CL= 50 pF; f = 1 MHz;
VI=GND toV
CC 1.5 V [3] -32- - - - -pF
Table 7. Dy namic characteristics …continued
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 13.
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ Max Min Max Min Max
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 7. Shift clock and storage clock inputs to output, propagation delays, pulse widths and maximum clock
frequency
IPD[
W:
W3+/
W3/+
9,
*1'
92+
92/
4RXWSXW
67&36+&3
LQSXW 90
90
DDD
© Nexperia B.V. 2017. All rights reserved
74HC_HCT597 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 4 — 25 February 2016 13 of 22
Nexperia 74HC597; 74HCT597
8-bit shift register with input flip-flop s
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 8. input (MR) to (Q), outp ut propagation delays and (MR) pulse width
W:
W3+/
9,
*1'
92+
92/
4RXWSXW
05LQSXW 90
90
DDD
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 9. Input (PL) to (Q), output propagation dela ys, PL pulse width and output transition times
I
PD[
W:
W3/+
W3+/
9,
*1'
92+
92/
4RXWSXW
3/
LQSXW 90
90
DDD
W7+/ W7/+
Measurement points are given in Table 8.
Fig 10. Input (MR ) to shift clock (SHCP) and storage clock (STCP) recovery times
W
UHF
9
,
*1'
9
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*1'
6+&3
LQSXW
05LQSXW 9
0
9
0
DDD
© Nexperia B.V. 2017. All rights reserved
74HC_HCT597 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 4 — 25 February 2016 14 of 22
Nexperia 74HC597; 74HCT597
8-bit shift register with input flip-flop s
Measurement points are given in Table 8.
Fig 11. Hold and set-up times for (DS), (Dn) inputs to (SHCP), (STCP) inputs
DDD
SRVLWLYH
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6+&3LQSXW
9
0
9
0
9
0
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9
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*1'
9
,
*1'
9
,
QHJDWLYH
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67&3LQSXW 9
0
*1'
9
,
W
K
W
VX
W
K
W
VX
Measurement points are given in Table 8.
Fig 12. Set-up times for (PL) input to (SHCP) input
DDD
3/LQSXW
6+&3
LQSXW
9
0
9
0
*1'
9
,
*1'
9
,
W
K
W
VX
Table 8. Measurement points
Type Input Output
VMVIVM
74HC597 0.5 VCC GND to VCC 0.5 VCC
74HCT597 1.3 V GND to 3 V 1.3 V
© Nexperia B.V. 2017. All rights reserved
74HC_HCT597 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 4 — 25 February 2016 15 of 22
Nexperia 74HC597; 74HCT597
8-bit shift register with input flip-flop s
Test data is given in Table 9.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
S1 = Test selection switch.
Fig 13. Test circuit for measuring switching times
9
0
9
0
W
:
W
:
9
9
,
9
,
QHJDWLYH
SXOVH
SRVLWLYH
SXOVH
9
9
0
9
0
W
I
W
U
W
U
W
I
DDG
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9
&&
9
&&
9,92
57
5/6
&/
RSHQ
*
Table 9. Test data
Type Input Load S1 position
VItr, tfCLRLtPHL, tPLH tPZH, tPHZ tPZL, tPLZ
74HC597 VCC 6ns 15pF, 50 pF 1kopen GND VCC
74HCT597 3 V 6 ns 15 p F, 50 pF 1 kopen GND VCC
© Nexperia B.V. 2017. All rights reserved
74HC_HCT597 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 4 — 25 February 2016 16 of 22
Nexperia 74HC597; 74HCT597
8-bit shift register with input flip-flop s
12. Package outline
Fig 14. Package outline SOT109-1 (SO16)
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© Nexperia B.V. 2017. All rights reserved
74HC_HCT597 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 4 — 25 February 2016 17 of 22
Nexperia 74HC597; 74HCT597
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© Nexperia B.V. 2017. All rights reserved
74HC_HCT597 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 4 — 25 February 2016 18 of 22
Nexperia 74HC597; 74HCT597
8-bit shift register with input flip-flop s
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© Nexperia B.V. 2017. All rights reserved
74HC_HCT597 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 4 — 25 February 2016 19 of 22
Nexperia 74HC597; 74HCT597
8-bit shift register with input flip-flop s
13. Abbreviations
14. Revision history
Table 10. Abbreviations
Acronym Description
CMOS Complementary Metal Oxide Semiconductor
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model
MM Machine Model
TTL Transistor-Transistor Logic
Table 11. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74HC_HCT597 v.4 20160225 Product data sheet - 74HC_HCT597 v.3
Modifications: •Type numbers 74HC597N and 74HCT597N (SOT38-4) removed.
74HC_HCT597 v.3 20140415 Product data sheet - 74HC_HCT597_CNV v.2
Modifications: •The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
•Legal texts have been adapted to the new company name where appropriate.
74HC_HCT597_CNV v.2 19901201 Product specification - -
© Nexperia B.V. 2017. All rights reserved
74HC_HCT597 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 4 — 25 February 2016 20 of 22
Nexperia 74HC597; 74HCT597
8-bit shift register with input flip-flop s
15. Legal information
15.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device (s) descr ibed in th is document m ay have cha nged since thi s document w as publish ed and may di ffe r in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nexperia.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. Nexperia does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not b e relied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local Nexperia sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall pre va il.
Product specificat ion — The information and data provided in a Product
data sheet shall define the specification of the product as agreed be tween
Nexperia and its customer, unless Nexperia and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the Nexperia product is
deemed to off er functions and qualities beyond those described in the
Product data sheet.
15.3 Disclaimers
Limited warr a nty and liability — Information in this document is believed to
be accurate and reliable. However, Nexperia does not give any
representations or warrant ies, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. Nexperia takes no
responsibility for the content in this document if provided by an information
source outside of Nexperia.
In no event shall Nexperia be liable for any indirect, incidental,
punitive, special or consequ ential damages (including - wit hout limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whethe r or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, Nexperia’s aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of Nexperia.
Right to make changes — Nexperia reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for use — Nexperia products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of a Nexperia product can reasonably be expected
to result in perso nal injury, death or seve re property or environmental
damage. Nexperia and its suppliers accept no liability for
inclusion and/or use of Nexperia products in such equipment or
applications and ther efore such inclu sion and/or use is at the cu stomer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. Nexperia makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and ope ration of their applications
and products using Nexperia products, and Nexperia
accepts no liability for any assistance with applications or cu stomer product
design. It is customer’s sole responsibility to determine whether the Nexperia
product is suitable and fit for the customer’s applications and
products planned, as well as fo r the planned application and use of
customer’s third party customer(s). Custo mers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Nexperia does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the applicatio n or use by custo mer’s
third party custo mer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using Nexperia
products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). Nexperia does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — Nexperia
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nexperia.com/profile/terms, unless otherwise
agreed in a valid written individua l agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. Nexperia hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of Nexperia products by customer.
No offer to sell or license — Nothing i n this document may be interpreted or
construed as an of fer t o sell product s that is open for accept ance or the gr ant,
conveyance or implication of any license under any copyrights, patents or
other industrial or inte llectual property rights.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.
© Nexperia B.V. 2017. All rights reserved
74HC_HCT597 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 4 — 25 February 2016 21 of 22
Nexperia 74HC597; 74HCT597
8-bit shift register with input flip-flop s
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific Nexperia product is automotive qualified,
the product is not suitable for automo tive use. It i s neither qua lified nor test ed
in accordance with automotive testing or application requirements. Nexperia
accepts no liability for inclusion and/or use of
non-automotive qualified products in automo tive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automot ive specifications and standards, custome r
(a) shall use the product without Nexperia’s warranty of the
product for such au tomotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
Nexperia’s specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies Nexperia for any
liability, damages or failed product claims resulting from custome r design and
use of the product for automotive applications beyond Nexperia’s
standard warranty and Nexperia’s product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
15.4 Trademarks
Notice: All referenced b rands, produc t names, service names and trademarks
are the property of their respective ow ners.
16. Contact information
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Nexperia 74HC597; 74HCT597
8-bit shift register with input flip-flop s
17. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 1
4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
6 Functional description . . . . . . . . . . . . . . . . . . . 5
7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6
8 Recommended operating conditions. . . . . . . . 6
9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7
10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16
13 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 19
14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 19
15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 20
15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 20
15.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
15.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 20
15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 21
16 Contact information. . . . . . . . . . . . . . . . . . . . . 21
17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
© Nexperia B.V. 2017. All rights reserved
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release:
25 February 2016
