Product Folder Sample & Buy Support & Community Tools & Software Technical Documents LP5951 SNVS345G - JUNE 2006 - REVISED DECEMBER 2014 LP5951 Micropower, 150-mA Low-Dropout CMOS Voltage Regulator 1 Features 3 Description * * * The LP5951 regulator is designed to meet the requirements of portable battery-powered systems providing a regulated output voltage and low quiescent current. When switched to shutdown mode via a logic signal at the Enable (EN) pin, the power consumption is reduced to virtually zero. 1 * * * * * * * * * * Input Voltage Range: 1.8 V to 5.5 V Output Voltage Range: 1.3 V to 3.7 V Excellent Line Transient Response: 2 mV (typical) Excellent PSRR: -60 dB at 1 kHz typical Low Quiescent Current of 29 A typical Small SC70-5 and SOT-23-5 Packages Fast Turnon Time of 30 s typ. Typical < 1 nA Quiescent Current in Shutdown Ensured 150-mA Output Current Logic Controlled Enable 0.4 V/0.9 V Good Load Transient Response of 50 mVpp (typical) Thermal Overload and Short-Circuit Protection -40C to 125C Junction Temperature Range The LP5951 is designed to be stable with small 1-F ceramic capacitors. The device also features internal protection against short-circuit currents and overtemperature conditions. Performance is specified for a -40C to 125C temperature range. The device is available in fixed output voltages in the range of 1.3 V to 3.7 V. For availability, please contact your local TI sales office. Device Information(1) PART NUMBER 2 Applications LP5951 General Purpose PACKAGE BODY SIZE (NOM) SOT-23 (5) 2.90 mm x 1.60 mm SC70 (5) 2.00 mm x 1.25 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. Simplified Schematic LP5951 1 VIN IN OUT 1 PF 5 1 PF Enable Control, active high 3 NC 4 Load EN GND 2 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LP5951 SNVS345G - JUNE 2006 - REVISED DECEMBER 2014 www.ti.com Table of Contents 1 2 3 4 5 6 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 7 1 1 1 2 3 4 Absolute Maximum Ratings ...................................... 4 ESD Ratings.............................................................. 4 Recommended Operating Conditions....................... 4 Thermal Information .................................................. 4 Electrical Characteristics........................................... 5 Enable Control Characteristics ................................. 5 Transient Characteristics .......................................... 5 Output Capacitor, Recommended Specification ....... 6 Typical Characteristics .............................................. 6 Detailed Description .............................................. 8 7.1 Overview ................................................................... 8 7.2 Functional Block Diagram ......................................... 8 7.3 Feature Description................................................... 8 7.4 Device Functional Modes.......................................... 9 8 Application and Implementation ........................ 10 8.1 Application Information............................................ 10 8.2 Typical Application ................................................. 10 9 Power Supply Recommendations...................... 13 9.1 Output Current Derating......................................... 13 10 Layout................................................................... 14 10.1 Layout Guidelines ................................................. 14 10.2 Layout Example .................................................... 14 11 Device and Documentation Support ................. 15 11.1 11.2 11.3 11.4 11.5 Device Support .................................................... Documentation Support ....................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 15 15 15 15 15 12 Mechanical, Packaging, and Orderable Information ........................................................... 15 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision F (May 2013) to Revision G Page * Added Device Information and ESD Rating tables, Feature Description, Device Functional Modes, Application and Implementation, Power Supply Recommendations, Layout, Device and Documentation Support, and Mechanical, Packaging, and Orderable Information sections; updated pin names; added new thermal information; moved some curves to Application Curves section...................................................................................................................................... 1 * Changed wording of footnote 2 ............................................................................................................................................. 5 * Changed values of RJA and "454 mW" to "511 mW" for SOT-23-5 package ................................................................... 10 Changes from Revision E (April 2013) to Revision F * 2 Page Changed layout of National Data Sheet to TI format ........................................................................................................... 12 Submit Documentation Feedback Copyright (c) 2006-2014, Texas Instruments Incorporated Product Folder Links: LP5951 LP5951 www.ti.com SNVS345G - JUNE 2006 - REVISED DECEMBER 2014 5 Pin Configuration and Functions SOT-23 (DBV) 5 Pins Top View OUT 5 1 IN NC 4 2 GND 3 EN SC70 (DCK) 5 Pins Top View OUT 5 1 IN NC 4 2 GND 3 EN Pin Functions PIN NUMBER NAME TYPE DESCRIPTION 1 IN I 2 GND -- Input voltage 1.8 V to 5.5 V 3 EN I 4 NC -- No internal connection 5 OUT O Regulated output voltage Ground Enable pin logic input: Low = shutdown, High = normal operation. This pin should not be left floating. Submit Documentation Feedback Copyright (c) 2006-2014, Texas Instruments Incorporated Product Folder Links: LP5951 3 LP5951 SNVS345G - JUNE 2006 - REVISED DECEMBER 2014 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature (unless otherwise noted) (1) MIN MAX IN pin: Voltage to GND -0.3 6.5 EN pin: Voltage to GND -0.3 to (VIN + 0.3 V) (2) 6.5 Continuous power dissipation (3) 150 Package peak reflow temperature (10-20 s) 240 Package peak reflow temperature (Pb-free, 10-20 s) 260 Storage temperature, Tstg (2) (3) V Internally limited Junction temperature (TJ-MAX ) (1) UNIT -65 C 150 C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The lower of VIN + 0.3 or 6.5 V. Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ = 160C (typ.) and disengages at TJ = 140C (typ.). 6.2 ESD Ratings V(ESD) (1) Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) Electrostatic discharge VALUE UNIT 2000 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) (1) (2) MIN VIN Input voltage VEN Enable input voltage TJ Junction temperature TA Ambient temperature (1) (2) NOM MAX UNIT 1.8 5.5 V 0 (VIN + 0.3) V -40 125 C See Power Dissipation And Device Operation Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to the potential at the GND pin. 6.4 Thermal Information LP5951 THERMAL METRIC (1) SOT-23 (DBV) SC70 (DCK) 5 PINS 5 PINS RJA Junction-to-ambient thermal resistance 195.6 276.7 RJC(top) Junction-to-case (top) thermal resistance 108.3 86.3 RJB Junction-to-board thermal resistance 52.1 56.9 JT Junction-to-top characterization parameter 11.0 1.3 JB Junction-to-board characterization parameter 51.6 56.1 (1) 4 UNIT C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright (c) 2006-2014, Texas Instruments Incorporated Product Folder Links: LP5951 LP5951 www.ti.com SNVS345G - JUNE 2006 - REVISED DECEMBER 2014 6.5 Electrical Characteristics All typical (TYP) values and limits are for TA = TJ = 25C, and minimum (MIN) and maximum (MAX) limits apply over the operating junction temperature range (TJ ) of -40C to 125C unless otherwise specified in the Test Conditions. Unless otherwise noted, VIN = VOUT(NOM) + 1 V, CIN = 1 F, COUT = 1 F, VEN = 0.9 V. (1) (2) PARAMETER VIN TEST CONDITIONS VIN VOUT(NOM) + VDO Input voltage IOUT = 1mA TJ = 25C Output voltage tolerance IOUT = 1mA -30C TJ +125C VOUT Line regulation error MIN TYP MAX 1.8 5.5 -2% 2% -3.5% 3.5% VIN = VOUT(NOM) + 1 V to 5.5 V 0.1 UNIT V %/V IOUT = 1 mA VDO Load regulation error IOUT = 1 mA to 150 mA Output voltage dropout (3) IOUT = 150 mA , VOUT 2.5 V -0.01 IOUT = 150 mA , VOUT < 2.5 V IQ Quiescent current 200 350 VEN = 0.9 V, ILOAD = 0 29 55 VEN = 0.9 V, ILOAD = 150 mA 33 70 0.005 1 VEN = 0 V, TJ = 25C ISC Output current (short circuit) PSRR VIN = VOUT(NOM) + 1 V Power supply rejection ratio EN Output noise TSD Thermal shutdown 150 (3) 400 Sine modulated VIN, = 100 Hz 60 Sine modulated VIN, = 1 kHz 60 Sine modulated VIN, = 10 kHz 50 BW = 10 Hz - 100 kHz Temperature hysteresis (1) (2) %/mA 250 mV A mA dB 125 VRMS 160 C 20 All voltages are with respect to the potential at the GND pin. Minimum and Maximum limits are ensured through test, design, or statistical correlation over the operating junction temperature range (TJ ) of -40C to 125C, unless otherwise stated. Typical values represent the most likely parametric norm at TJ = 25C, and are provided for reference purposes only. Dropout voltage is defined as the input to output voltage differential at which the output voltage falls to 100 mV below the nominal output voltage. This specification does not apply for output voltages below 1.8 V. 6.6 Enable Control Characteristics PARAMETER TEST CONDITIONS IEN Maximum input current at EN input 0 V VEN VIN, VIN = 5.5 V -40C TJ 125C VIL Low input threshold (shutdown) VIN = 1.8 V to 5.5 V -40C TJ 125C VIH High input threshold (enable) VIN = 1.8 V to 5.5 V -40C TJ 125C MIN TYP MAX -1 1 UNIT A 0.4 V 0.9 6.7 Transient Characteristics PARAMETER VOUT Dynamic line transient TEST CONDITIONS VIN = VOUT(NOM) + 1 V to VOUT(NOM) + 1 V + 0.6 V in 30 s, no load MIN TYP MAX UNIT 2 mV -30 20 -50 40 mV mV mV mV VOUT Dynamic load transient IOUT = 0 mA to 150 mA in 10 s IOUT = 150 mA to 0 mA in 10 s IOUT = 1 mA to 150 mA in 1 s IOUT = 150 mA to 1 mA in 1 s VOUT Overshoot on start-up Nominal conditions 10 mV TON Turnon time IOUT = 1 mA 30 s Submit Documentation Feedback Copyright (c) 2006-2014, Texas Instruments Incorporated Product Folder Links: LP5951 5 LP5951 SNVS345G - JUNE 2006 - REVISED DECEMBER 2014 www.ti.com 6.8 Output Capacitor, Recommended Specification PARAMETER TEST CONDITIONS MIN (1) TYP MAX (1) 0.7 1 47 F 0.300 UNIT (2) COUT Output capacitance Capacitance IOUT = 150 mA, VIN = 5 V ESR (1) (2) 0.003 Min and Max limits are ensured by design. The capacitor tolerance should be 30% or better over temperature. The full operating conditions for the application should be considered when selecting a suitable capacitor to ensure that the minimum value of capacitance is always met. Recommended capacitor type is X7R. However, dependent on application, X5R, Y5V, and Z5U can also be used. The shown minimum limit represents real minimum capacitance, including all tolerances and must be maintained over temperature and dc bias voltage (see External Capacitors in Application and Implementation section). 6.9 Typical Characteristics 150 0 AVOUT LOAD CURRENT (mA) CIN, COUT = 1.0 F LP5951-3.3 150 0 TIME (50 s/DIV) TIME (50 s/DIV) Figure 1. Load Transient Response LP5951-3.3 VIN (1V/DIV) IL = 150 mA CIN = 1.0 F COUT = 1.5 F 4.3 IL = 150 mA AVOUT 2.3 TIME (100 s/DIV) TIME (100 s/DIV) Figure 3. Line Transient Response 6 4.9 (2 mV/DIV) VIN AVOUT 2.9 Figure 2. Load Transient Response CIN, COUT = 1.0 F (2 mV/DIV) (500 mV/DIV) LP5951-1.3 CIN = 1.0 F COUT = 1.5 F (20 mV/DIV) LP5951-1.3 (20 mV/DIV) AVOUT LOAD CURRENT (mA) Unless otherwise specified, CIN = 1 F ceramic, COUT = 1 F ceramic, VIN = VOUT(NOM) + 1 V, TA = 25C; EN pin is tied to VIN. Submit Documentation Feedback Figure 4. Line Transient Response Copyright (c) 2006-2014, Texas Instruments Incorporated Product Folder Links: LP5951 LP5951 www.ti.com SNVS345G - JUNE 2006 - REVISED DECEMBER 2014 Typical Characteristics (continued) Unless otherwise specified, CIN = 1 F ceramic, COUT = 1 F ceramic, VIN = VOUT(NOM) + 1 V, TA = 25C; EN pin is tied to VIN. IL = 150 mA IL = 150 mA VEN (500 mV/DIV) VOUT LP5951-3.3 (1V/DIV) VEN (500 mV/DIV) VOUT (500 mV/DIV) LP5951-1.3 TIME (10 s/DIV) TIME (10 s/DIV) Figure 5. Enable Start-Up Time Figure 6. Enable Start-Up Time 1.0 40.0 LP5951-1.3 IL = 1 mA IL = 1 mA LP5951-1.3 38.0 0.8 TA = 125oC 34.0 32.0 IGND (PA) VOUT CHANGE (%) 36.0 0.6 0.4 0.2 30.0 TA = 25oC 28.0 26.0 0.0 24.0 22.0 -0.2 -0.4 -40 -20 TA = -40oC 20.0 18.0 1.5 0 20 40 60 80 100 120 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VIN (V) TEMPERATURE (oC) Figure 7. Output Voltage Change vs Temperature Figure 8. Ground Current vs VIN 0 LP5951-3.3 RIPPLE REJECTION (dB) VIN = 3.8V, IL = 1 mA -20 -40 VIN = 5.5V, IL = 1 mA -60 -80 10 VIN = 5.5V, VIN = 3.8V, IL = 0 mA IL = 0 mA 100 1k 10k 100k 1M FREQUENCY (Hz) Figure 9. Power Supply Rejection Ratio Submit Documentation Feedback Copyright (c) 2006-2014, Texas Instruments Incorporated Product Folder Links: LP5951 7 LP5951 SNVS345G - JUNE 2006 - REVISED DECEMBER 2014 www.ti.com 7 Detailed Description 7.1 Overview The LP5951 regulator is designed to meet the requirements of portable battery-powered systems providing a regulated output voltage and low quiescent current. When switched to shutdown mode via a logic signal at the EN pin, the power consumption is reduced to virtually zero. 7.2 Functional Block Diagram IN Bias Generator EN LDO Core and Reference OUT Enable Controller Over Current and Thermal Protection GND 7.3 Feature Description 7.3.1 No-Load Stability The LP5951 will remain stable and in regulation with no external load. This is an important consideration in some circuits, for example CMOS RAM keep-alive applications. 7.3.2 Enable Operation The LP5951 may be switched ON or OFF by a logic input at the Enable pin, EN. A logic high at this pin will turn the device on. When the EN pin is low, the regulator output is off and the device typically consumes 5 nA. If the application does not require the enable switching feature, the EN pin should be tied to VIN to keep the regulator output permanently on. To ensure proper operation, the signal source used to drive the VEN input must be able to swing above and below the specified turn-on/off voltage thresholds listed in the Enable Control Characteristics table, VIL and VIH. 7.3.3 Fast Turn Off And On The controlled switch-off feature of the device provides a fast turn off by discharging the output capacitor via an internal FET device. This discharge is current limited by the RDSon of this switch. Fast turnon is ensured by an optimized architecture allowing a very fast ramp of the output voltage to reach the target voltage. 7.3.4 Short-Circuit Protection The LP5951 is short circuit protected and in the event of a peak over-current condition, the output current through the PMOS will be limited. If the over-current condition exists for a longer time, the average power dissipation will increase depending on the input to output voltage difference until the thermal shutdown circuitry will turn off the PMOS. Please refer to the Thermal Information section for power dissipation calculations. 8 Submit Documentation Feedback Copyright (c) 2006-2014, Texas Instruments Incorporated Product Folder Links: LP5951 LP5951 www.ti.com SNVS345G - JUNE 2006 - REVISED DECEMBER 2014 Feature Description (continued) 7.3.5 Thermal-Overload Protection Thermal-Overload Protection limits the total power dissipation in the LP5951. When the junction temperature exceeds TJ = 160C typ., the shutdown logic is triggered and the PMOS is turned off, allowing the device to cool down. After the junction temperature dropped by 20C (temperature hysteresis), the PMOS is activated again. This results in a pulsed output voltage during continuous thermal-overload conditions. The Thermal-Overload Protection is designed to protect the LP5951 in the event of a fault condition. For normal, continuous operation, do not exceed the absolute maximum junction temperature rating of TJ = 150C (see Absolute Maximum Ratings). 7.3.6 Reverse Current Path The internal PFET pass device in LP5951 has an inherent parasitic body diode. During normal operation, the input voltage is higher than the output voltage and the parasitic diode is reverse biased. However, if the output is pulled above the input in an application, then current flows from the output to the input as the parasitic diode gets forward biased. The output can be pulled above the input as long as the current in the parasitic diode is limited to 50 mA. For currents above this limit an external Schottky diode must be connected from VOUT to VIN (cathode on VIN, anode on VOUT). 7.4 Device Functional Modes 7.4.1 Enable (EN) The EN pin voltage must be higher than the VIH threshold to ensure that the device is fully enabled under all operating conditions. The EN pin voltage must be lower than the VIL threshold to ensure that the device is fully disabled. However if the application does not require the shutdown feature, the VEN pin can be tied to VIN to keep the regulator output permanently on. 7.4.2 Minimum Operating Input Voltage (VIN) The LP5951 internal circuitry is not fully functional until VIN is at least 1.8 V. The output voltage is not regulated until VIN (VOUT + VDO), or 1.8 V, whichever is higher. Submit Documentation Feedback Copyright (c) 2006-2014, Texas Instruments Incorporated Product Folder Links: LP5951 9 LP5951 SNVS345G - JUNE 2006 - REVISED DECEMBER 2014 www.ti.com 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The LP5951 is a linear voltage regulator for digital applications designed to be stable with space-saving ceramic capacitors as small as 1 F. Performance is specified for a -40C to 125C temperature range for bot the SOT23 and SC70 packages. 8.2 Typical Application LP5951 1 VIN IN OUT 1 PF 5 1 PF Enable Control, active high 3 NC Load 4 EN GND 2 Figure 10. LP5951 Typical Application 8.2.1 Design Requirements Table 1. Design Parameters DESIGN PARAMETER DESIGN REQUIREMENT Input voltage range 1.8 V to 5.5 V Output voltage 1.3 V Output current 150 mA Output capacitor range 1 F Input/output capacitor ESR range 3 m to 300 m 8.2.2 Detailed Design Procedure 8.2.2.1 Power Dissipation And Device Operation The permissible power dissipation for any package is a measure of the capability of the device to pass heat from the power source, the junctions of the IC, to the ultimate heat sink, the ambient environment. Thus, the power dissipation is dependent on the ambient temperature and the thermal resistance across the various interfaces between the die and ambient air. In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = 125C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the part/package in the application (RJA), as given by the following equation: TA-MAX = TJ-MAX-OP - (RJA x PD-MAX). The allowable power dissipation for the device in a given package can be calculated using the equation: PD = (TJ(MAX) - TA) /RJA (1) With an RJA = 195.6C/W, the device in the SOT-23-5 package returns a value of 511 mW with a maximum junction temperature of 125C at TA of 25C. 10 Submit Documentation Feedback Copyright (c) 2006-2014, Texas Instruments Incorporated Product Folder Links: LP5951 LP5951 www.ti.com SNVS345G - JUNE 2006 - REVISED DECEMBER 2014 The actual power dissipation across the device can be estimated by the following equation: PD (VIN - VOUT) x IOUT (2) This establishes the relationship between the power dissipation allowed due to thermal consideration, the voltage drop across the device, and the continuous current capability of the device. These two equations should be used to determine the optimum operating conditions for the device in the application. 8.2.2.2 External Capacitors As is common with most regulators, the LP5951 requires external capacitors to ensure stable operation. The LP5951 is specifically designed for portable applications requiring minimum board space and the smallest size components. These capacitors must be correctly selected for good performance. 8.2.2.3 Input Capacitor An input capacitor is required for stability. It is recommended that a 1-F capacitor be connected between the LP5951 IN pin and ground (this capacitance value may be increased without limit). This capacitor must be located a distance of not more than 1 cm from the input pin and returned to a clean analogue ground. Any good quality ceramic, tantalum, or film capacitor may be used at the input. Important: Tantalum capacitors can suffer catastrophic failures due to surge current when connected to a lowimpedance source of power (like a battery or a very large capacitor). If a tantalum capacitor is used at the input, it must be ensured by the manufacturer to have a surge current rating sufficient for the application. There are no requirements for the ESR (Equivalent Series Resistance) on the input capacitor, but tolerance and temperature coefficient must be considered when selecting the capacitor to ensure the capacitance will remain 0.7 F over the entire operating temperature range. 8.2.2.4 Output Capacitor The LP5951 is designed specifically to work with very small ceramic output capacitors. A ceramic capacitor (dielectric types X7R, Z5U, or Y5V) in the 1-F range (up to 47 F) and with ESR between 3 m to 500 m is suitable in the LP5951 application circuit. This capacitor must be located a distance of not more than 1 cm from the OUT pin and returned to a clean analogue ground. It is also possible to use tantalum or film capacitors at the device output, VOUT, but these are not as attractive for reasons of size and cost (see Capacitor Characteristics). 8.2.2.5 Capacitor Characteristics The LP5951 is designed to work with ceramic capacitors on the output to take advantage of the benefits they offer. For capacitance values in the range of 1 F to 4.7 F, ceramic capacitors are the smallest, least expensive and have the lowest ESR values, thus making them best for eliminating high frequency noise. The ESR of a typical 1-F ceramic capacitor is in the range of 3 m to 40 m, which easily meets the ESR requirement for stability for the LP5951. For both input and output capacitors, careful interpretation of the capacitor specification is required to ensure correct device operation. The capacitor value can change greatly, depending on the operating conditions and capacitor type. In particular, the output capacitor selection should take account of all the capacitor parameters, to ensure that the specification is met within the application. The capacitance can vary with DC bias conditions as well as temperature and frequency of operation. Capacitor values will also show some decrease over time due to aging. The capacitor parameters are also dependant on the particular case size, with smaller sizes giving poorer performance figures in general. As an example, Figure 11 shows a typical graph comparing different capacitor case sizes in a Capacitance vs. DC Bias plot. As shown in the graph, increasing the DC Bias condition can result in the capacitance value falling below the minimum value given in the recommended capacitor specifications table (0.7 F in this case). Note that the graph shows the capacitance out of spec for the 0402 case size capacitor at higher bias voltages. It is therefore recommended that the capacitor manufacturers' specifications for the nominal value capacitor are consulted for all conditions, as some capacitor sizes (such as 0402) may not be suitable in the actual application. Submit Documentation Feedback Copyright (c) 2006-2014, Texas Instruments Incorporated Product Folder Links: LP5951 11 LP5951 CAP VALUE (% of Nom. 1 PF) SNVS345G - JUNE 2006 - REVISED DECEMBER 2014 www.ti.com 0603, 10V, X5R 100% 80% 60% 0402, 6.3V, X5R 40% 20% 0 1.0 2.0 3.0 4.0 5.0 DC BIAS (V) Figure 11. Typical Variation in Capacitance vs DC Bias The ceramic capacitor's capacitance can vary with temperature. The capacitor type X7R, which operates over a temperature range of -55C to 125C, will only vary the capacitance to within 15%. The capacitor type X5R has a similar tolerance over a reduced temperature range of -55C to 85C. Many large value ceramic capacitors, larger than 1 F are manufactured with Z5U or Y5V temperature characteristics. Their capacitance can drop by more than 50% as the temperature varies from 25C to 85C. Therefore X7R is recommended over Z5U and Y5V in applications where the ambient temperature will change significantly above or below 25C. Tantalum capacitors are less desirable than ceramic for use as output capacitors because they are more expensive when comparing equivalent capacitance and voltage ratings in the 1-F to 4.7-F range. Another important consideration is that tantalum capacitors have higher ESR values than equivalent size ceramics. This means that while it may be possible to find a tantalum capacitor with an ESR value within the stable range, it would have to be larger in capacitance (which means bigger and more costly) than a ceramic capacitor with the same ESR value. It should also be noted that the ESR of a typical tantalum will increase about 2:1 as the temperature goes from 25C down to -40C, so some guard band must be allowed. Table 2. Suggested Capacitors and Their Suppliers 12 CAPACITANCE / F MODEL VENDOR TYPE CASE SIZE / INCH (mm) 1 C1608X5R1A105K TDK Ceramic, X5R 0603 (1608) 1 C1005X5R1A105K TDK Ceramic, X5R 0402 (1005) Submit Documentation Feedback Copyright (c) 2006-2014, Texas Instruments Incorporated Product Folder Links: LP5951 LP5951 www.ti.com SNVS345G - JUNE 2006 - REVISED DECEMBER 2014 LP5951-1.3 VEN (500 mV/DIV) 150 VOUT CIN, COUT = 1.0 F (500 mV/DIV) LP5951-1.3 0 (20 mV/DIV) AVOUT LOAD CURRENT (mA) 8.2.3 Application Curves IL = 150 mA TIME (10 s/DIV) TIME (50 s/DIV) Figure 13. Enable Start-Up Time Figure 12. Load Transient Response 9 Power Supply Recommendations This device is designed to operate from an input supply voltage range of 1.8 V to 5.5 V. The input supply should be well regulated and free of spurious noise. To ensure that the LP5951 output voltage is well regulated, the input supply should be at least VOUT + 0.5 V, or 1.8 V, whichever is higher. A minimum capacitor value of 1-F is required to be within 1 cm of the IN pin. 9.1 Output Current Derating 0.15 ILOADMAX / A SOT23-5 SC70-5 0.1 0.05 0 0 1 2 VIN - VOUT / V 3 4 D001 Figure 14. Maximum Load Current vs VIN - VOUT, TA = 85C, VOUT = 1.5 V Submit Documentation Feedback Copyright (c) 2006-2014, Texas Instruments Incorporated Product Folder Links: LP5951 13 LP5951 SNVS345G - JUNE 2006 - REVISED DECEMBER 2014 www.ti.com 10 Layout 10.1 Layout Guidelines The dynamic performance of the LP5951 is dependent on the layout of the PCB. PCB layout practices that are adequate for typical LDOs may degrade the load regulation, PSRR, noise, or transient performance of the LP5951. Best performance is achieved by placing CIN and COUT on the same side of the PCB as the LP5951, and as close as is practical to the package. The ground connections for CIN and COUT should be back to the LP5951 ground pin using as wide, and as short, of a copper trace as is practical. Connections using long trace lengths, narrow trace widths, and/or connections through vias should be avoided. These will add parasitic inductances and resistance that results in inferior performance especially during transient conditions. A Ground Plane, either on the opposite side of a two-layer PCB, or embedded in a multi-layer PCB, is strongly recommended. This Ground Plane serves as a circuit reference plane to assure accuracy. 10.2 Layout Example VIN GND CIN 1 IN 2 GND OUT 5 COUT VOUT GND Enable 3 EN N/C 4 Figure 15. LP5951 Layout 14 Submit Documentation Feedback Copyright (c) 2006-2014, Texas Instruments Incorporated Product Folder Links: LP5951 LP5951 www.ti.com SNVS345G - JUNE 2006 - REVISED DECEMBER 2014 11 Device and Documentation Support 11.1 Device Support 11.1.1 Third-Party Products Disclaimer TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE. 11.2 Documentation Support 11.2.1 Related Documentation For the availability of evaluation boards, see the LP5951 product folder. For information regarding evaluation boards, see the TI AN-1486 Application Report LP5951 Evaluation Board (SNVA169). 11.3 Trademarks All trademarks are the property of their respective owners. 11.4 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.5 Glossary SLYZ022 -- TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright (c) 2006-2014, Texas Instruments Incorporated Product Folder Links: LP5951 15 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2017 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) LP5951MF-1.3/NOPB ACTIVE SOT-23 DBV 5 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LKRB LP5951MF-1.5/NOPB ACTIVE SOT-23 DBV 5 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LKAB LP5951MF-1.8/NOPB ACTIVE SOT-23 DBV 5 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LKBB LP5951MF-2.0/NOPB ACTIVE SOT-23 DBV 5 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LKCB LP5951MF-2.5/NOPB ACTIVE SOT-23 DBV 5 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LKEB LP5951MF-2.8/NOPB ACTIVE SOT-23 DBV 5 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LKFB LP5951MF-3.0/NOPB ACTIVE SOT-23 DBV 5 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LKGB LP5951MF-3.3 NRND SOT-23 DBV 5 1000 TBD Call TI Call TI -40 to 125 LKHB LP5951MF-3.3/NOPB ACTIVE SOT-23 DBV 5 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LKHB LP5951MFX-1.3/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LKRB LP5951MFX-1.5/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LKAB LP5951MFX-1.8/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LKBB LP5951MFX-2.0/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LKCB LP5951MFX-2.5/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LKEB LP5951MFX-3.0/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LKGB LP5951MFX-3.3/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LKHB LP5951MG-1.3/NOPB ACTIVE SC70 DCK 5 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L23 Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 14-Oct-2017 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) LP5951MG-1.5/NOPB ACTIVE SC70 DCK 5 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM LP5951MG-1.8/NOPB ACTIVE SC70 DCK 5 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM L3B LP5951MG-2.0/NOPB ACTIVE SC70 DCK 5 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM L4B LP5951MG-2.5/NOPB ACTIVE SC70 DCK 5 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM L5B LP5951MG-2.8/NOPB ACTIVE SC70 DCK 5 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM L6B LP5951MG-3.0/NOPB ACTIVE SC70 DCK 5 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM L7B LP5951MG-3.3/NOPB ACTIVE SC70 DCK 5 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM LAB LP5951MGX-1.3/NOPB ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L23 LP5951MGX-1.5/NOPB ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L2B LP5951MGX-1.8/NOPB ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM L3B LP5951MGX-2.5/NOPB ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM L5B LP5951MGX-2.8/NOPB ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM L6B LP5951MGX-3.0/NOPB ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM L7B LP5951MGX-3.3/NOPB ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM LAB (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. Addendum-Page 2 -40 to 125 L2B Samples PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2017 (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 24-Aug-2017 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) LP5951MF-1.3/NOPB SOT-23 DBV 5 1000 178.0 8.4 LP5951MF-1.5/NOPB SOT-23 DBV 5 1000 178.0 LP5951MF-1.8/NOPB SOT-23 DBV 5 1000 178.0 LP5951MF-2.0/NOPB SOT-23 DBV 5 1000 LP5951MF-2.5/NOPB SOT-23 DBV 5 LP5951MF-2.8/NOPB SOT-23 DBV LP5951MF-3.0/NOPB SOT-23 DBV LP5951MF-3.3 SOT-23 W Pin1 (mm) Quadrant 3.2 3.2 1.4 4.0 8.0 Q3 8.4 3.2 3.2 1.4 4.0 8.0 Q3 8.4 3.2 3.2 1.4 4.0 8.0 Q3 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LP5951MF-3.3/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LP5951MFX-1.3/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LP5951MFX-1.5/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LP5951MFX-1.8/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LP5951MFX-2.0/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LP5951MFX-2.5/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LP5951MFX-3.0/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LP5951MFX-3.3/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LP5951MG-1.3/NOPB SC70 DCK 5 1000 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3 LP5951MG-1.5/NOPB SC70 DCK 5 1000 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 24-Aug-2017 Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LP5951MG-1.8/NOPB SC70 DCK 5 1000 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3 LP5951MG-2.0/NOPB SC70 DCK 5 1000 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3 LP5951MG-2.5/NOPB SC70 DCK 5 1000 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3 LP5951MG-2.8/NOPB SC70 DCK 5 1000 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3 LP5951MG-3.0/NOPB SC70 DCK 5 1000 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3 LP5951MG-3.3/NOPB SC70 DCK 5 1000 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3 LP5951MGX-1.3/NOPB SC70 DCK 5 3000 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3 LP5951MGX-1.5/NOPB SC70 DCK 5 3000 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3 LP5951MGX-1.8/NOPB SC70 DCK 5 3000 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3 LP5951MGX-2.5/NOPB SC70 DCK 5 3000 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3 LP5951MGX-2.8/NOPB SC70 DCK 5 3000 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3 LP5951MGX-3.0/NOPB SC70 DCK 5 3000 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3 LP5951MGX-3.3/NOPB SC70 DCK 5 3000 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LP5951MF-1.3/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0 LP5951MF-1.5/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0 LP5951MF-1.8/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0 LP5951MF-2.0/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0 Pack Materials-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 24-Aug-2017 Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LP5951MF-2.5/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0 LP5951MF-2.8/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0 LP5951MF-3.0/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0 LP5951MF-3.3 SOT-23 DBV 5 1000 210.0 185.0 35.0 LP5951MF-3.3/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0 LP5951MFX-1.3/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0 LP5951MFX-1.5/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0 LP5951MFX-1.8/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0 LP5951MFX-2.0/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0 LP5951MFX-2.5/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0 LP5951MFX-3.0/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0 LP5951MFX-3.3/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0 LP5951MG-1.3/NOPB SC70 DCK 5 1000 210.0 185.0 35.0 LP5951MG-1.5/NOPB SC70 DCK 5 1000 210.0 185.0 35.0 LP5951MG-1.8/NOPB SC70 DCK 5 1000 210.0 185.0 35.0 LP5951MG-2.0/NOPB SC70 DCK 5 1000 210.0 185.0 35.0 LP5951MG-2.5/NOPB SC70 DCK 5 1000 210.0 185.0 35.0 LP5951MG-2.8/NOPB SC70 DCK 5 1000 210.0 185.0 35.0 LP5951MG-3.0/NOPB SC70 DCK 5 1000 210.0 185.0 35.0 LP5951MG-3.3/NOPB SC70 DCK 5 1000 210.0 185.0 35.0 LP5951MGX-1.3/NOPB SC70 DCK 5 3000 210.0 185.0 35.0 LP5951MGX-1.5/NOPB SC70 DCK 5 3000 210.0 185.0 35.0 LP5951MGX-1.8/NOPB SC70 DCK 5 3000 210.0 185.0 35.0 LP5951MGX-2.5/NOPB SC70 DCK 5 3000 210.0 185.0 35.0 LP5951MGX-2.8/NOPB SC70 DCK 5 3000 210.0 185.0 35.0 LP5951MGX-3.0/NOPB SC70 DCK 5 3000 210.0 185.0 35.0 LP5951MGX-3.3/NOPB SC70 DCK 5 3000 210.0 185.0 35.0 Pack Materials-Page 3 PACKAGE OUTLINE DBV0005A SOT-23 - 1.45 mm max height SCALE 4.000 SMALL OUTLINE TRANSISTOR C 3.0 2.6 1.75 1.45 PIN 1 INDEX AREA 1 0.1 C B A 5 2X 0.95 1.9 1.45 MAX 3.05 2.75 1.9 2 4 0.5 5X 0.3 0.2 3 (1.1) C A B 0.15 TYP 0.00 0.25 GAGE PLANE 8 TYP 0 0.22 TYP 0.08 0.6 TYP 0.3 SEATING PLANE 4214839/C 04/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-178. www.ti.com EXAMPLE BOARD LAYOUT DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X (0.95) 3 4 (R0.05) TYP (2.6) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X SOLDER MASK OPENING METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL 0.07 MIN ARROUND 0.07 MAX ARROUND NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS 4214839/C 04/2017 NOTES: (continued) 4. Publication IPC-7351 may have alternate designs. 5. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X(0.95) 4 3 (R0.05) TYP (2.6) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X 4214839/C 04/2017 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 7. Board assembly site may have different recommendations for stencil design. www.ti.com PACKAGE OUTLINE DBV0005A SOT-23 - 1.45 mm max height SCALE 4.000 SMALL OUTLINE TRANSISTOR C 3.0 2.6 1.75 1.45 PIN 1 INDEX AREA 1 0.1 C B A 5 2X 0.95 1.9 1.45 MAX 3.05 2.75 1.9 2 4 0.5 5X 0.3 0.2 3 (1.1) C A B 0.15 TYP 0.00 0.25 GAGE PLANE 8 TYP 0 0.22 TYP 0.08 0.6 TYP 0.3 SEATING PLANE 4214839/C 04/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-178. www.ti.com EXAMPLE BOARD LAYOUT DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X (0.95) 3 4 (R0.05) TYP (2.6) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X SOLDER MASK OPENING METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL 0.07 MIN ARROUND 0.07 MAX ARROUND NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS 4214839/C 04/2017 NOTES: (continued) 4. Publication IPC-7351 may have alternate designs. 5. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X(0.95) 4 3 (R0.05) TYP (2.6) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X 4214839/C 04/2017 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 7. Board assembly site may have different recommendations for stencil design. www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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