W25Q64JV 3V 64M-BIT SERIAL FLASH MEMORY WITH DUAL, QUAD SPI Publication Release Date: November 22, 2017 Revision I W25Q64JV Table of Contents 1. 2. 3. 4. 5. 6. GENERAL DESCRIPTIONS .................................................................................................................. 4 FEATURES ............................................................................................................................................ 4 PACKAGE TYPES AND PIN CONFIGURATIONS ............................................................................... 5 3.1 Pin Configuration SOIC 208-mil ................................................................................................ 5 3.2 Pad Configuration WSON 6x5-mm/ 8x6-mm, XSON 4x4-mm .................................................. 5 3.3 Pin Description SOIC 208-mil, WSON 6x5-mm/ 8x6-mm, XSON 4x4-mm ............................... 5 3.4 Pin Configuration SOIC 300-mil ................................................................................................ 6 3.5 Pin Description SOIC 300-mil .................................................................................................... 6 3.6 Ball Configuration TFBGA 8x6-mm (5x5 or 6x4 Ball Array) ...................................................... 7 3.7 Ball Description TFBGA 5x5 or 8x6-mm ................................................................................... 7 3.8 Ball Configuration WLCSP ........................................................................................................ 8 3.9 Ball Description WLCSP12 ........................................................................................................ 8 PIN DESCRIPTIONS ............................................................................................................................. 9 4.1 Chip Select (/CS) ....................................................................................................................... 9 4.2 Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3) ......................................... 9 4.3 Write Protect (/WP).................................................................................................................... 9 4.4 HOLD (/HOLD) .......................................................................................................................... 9 4.5 Serial Clock (CLK) ..................................................................................................................... 9 4.6 Reset (/RESET)(1) ...................................................................................................................... 9 BLOCK DIAGRAM ...............................................................................................................................10 FUNCTIONAL DESCRIPTIONS ..........................................................................................................11 6.1 Standard SPI Instructions ........................................................................................................11 6.2 Dual SPI Instructions ...............................................................................................................11 6.3 Quad SPI Instructions..............................................................................................................11 6.4 Software Reset & Hardware /RESET pin ................................................................................11 6.5 Write Protection .......................................................................................................................12 Write Protect Features ............................................................................................................... 12 7. STATUS AND CONFIGURATION REGISTERS .................................................................................13 7.1 Status Registers ......................................................................................................................13 Erase/Write In Progress (BUSY) - Status Only ...................................................................... 13 Write Enable Latch (WEL) - Status Only ................................................................................ 13 Block Protect Bits (BP2, BP1, BP0) - Volatile/Non-Volatile Writable ...................................... 13 Top/Bottom Block Protect (TB) - Volatile/Non-Volatile Writable ............................................. 14 Sector/Block Protect Bit (SEC) - Volatile/Non-Volatile Writable ............................................. 14 Complement Protect (CMP) - Volatile/Non-Volatile Writable ................................................. 14 Status Register Protect (SRP, SRL) - Volatile/Non-Volatile Writable ..................................... 15 Erase/Program Suspend Status (SUS) - Status Only ............................................................ 16 Security Register Lock Bits (LB3, LB2, LB1) - Volatile/Non-Volatile OTP Writable ................ 16 Quad Enable (QE) - Volatile/Non-Volatile Writable ................................................................ 16 Write Protect Selection (WPS) - Volatile/Non-Volatile Writable ............................................. 17 Output Driver Strength (DRV1, DRV0) - Volatile/Non-Volatile Writable ................................. 17 -1- Publication Release Date: November 22, 2017 Revision I W25Q64JV Reserved Bits - Non Functional ............................................................................................. 17 Status Register Memory Protection (WPS = 0, CMP = 0) .......................................................... 18 Status Register Memory Protection (WPS = 0, CMP = 1) .......................................................... 19 Individual Block Memory Protection (WPS=1) ......................................................................... 20 8. INSTRUCTIONS ..................................................................................................................................21 8.1 Device ID and Instruction Set Tables ......................................................................................21 Manufacturer and Device Identification ...................................................................................... 21 Instruction Set Table 1 (Standard SPI Instructions)(1) ................................................................ 22 Instruction Set Table 2 (Dual/Quad SPI Instructions)(1).............................................................. 23 8.2 Instruction Descriptions ...........................................................................................................24 Write Enable (06h) ..................................................................................................................... 24 Write Enable for Volatile Status Register (50h).......................................................................... 24 Write Disable (04h) .................................................................................................................... 25 Read Status Register-1 (05h), Status Register-2 (35h) & Status Register-3 (15h) .................... 25 Write Status Register-1 (01h), Status Register-2 (31h) & Status Register-3 (11h) .................... 26 Read Data (03h) ........................................................................................................................ 28 Fast Read (0Bh) ........................................................................................................................ 29 Fast Read Dual Output (3Bh) .................................................................................................... 30 Fast Read Quad Output (6Bh) ................................................................................................... 31 Fast Read Dual I/O (BBh) ........................................................................................................ 32 Fast Read Quad I/O (EBh)....................................................................................................... 33 Set Burst with Wrap (77h) ........................................................................................................ 34 Page Program (02h) ................................................................................................................ 35 Quad Input Page Program (32h).............................................................................................. 36 8.3 Sector Erase (20h) ..................................................................................................................37 32KB Block Erase (52h)............................................................................................................. 38 64KB Block Erase (D8h) ............................................................................................................ 39 Chip Erase (C7h / 60h) .............................................................................................................. 40 Erase / Program Suspend (75h) ................................................................................................ 41 Erase / Program Resume (7Ah) ................................................................................................. 42 Power-down (B9h) ..................................................................................................................... 43 Release Power-down / Device ID (ABh) .................................................................................... 44 Read Manufacturer / Device ID (90h) ........................................................................................ 45 Read Manufacturer / Device ID Dual I/O (92h) .......................................................................... 46 Read Manufacturer / Device ID Quad I/O (94h) ....................................................................... 47 Read Unique ID Number (4Bh) ................................................................................................ 48 Read JEDEC ID (9Fh) ............................................................................................................. 49 Read SFDP Register (5Ah)...................................................................................................... 50 Erase Security Registers (44h) ................................................................................................ 51 Program Security Registers (42h) ............................................................................................ 52 Read Security Registers (48h) ................................................................................................. 53 Individual Block/Sector Lock (36h) ........................................................................................... 54 Individual Block/Sector Unlock (39h) ....................................................................................... 55 Read Block/Sector Lock (3Dh)................................................................................................. 56 Global Block/Sector Lock (7Eh) ............................................................................................... 57 -2- Publication Release Date: November 22, 2017 Revision I W25Q64JV Global Block/Sector Unlock (98h) ............................................................................................ 57 Enable Reset (66h) and Reset Device (99h) ........................................................................... 58 9. 10. 11. 12. ELECTRICAL CHARACTERISTICS....................................................................................................59 9.1 Absolute Maximum Ratings (1) ...............................................................................................59 9.2 Operating Ranges ...................................................................................................................59 9.3 Power-Up Power-Down Timing and Requirements ................................................................60 9.4 DC Electrical Characteristics- ..................................................................................................61 9.5 AC Measurement Conditions ..................................................................................................62 9.6 AC Electrical Characteristics(6) ................................................................................................63 9.7 Serial Output Timing ................................................................................................................65 9.8 Serial Input Timing...................................................................................................................65 9.9 /WP Timing ..............................................................................................................................65 PACKAGE SPECIFICATIONS ............................................................................................................66 10.1 8-Pin SOIC 208-mil (Package Code SS) .................................................................................66 10.2 8-Pad WSON 6x5-mm (Package Code ZP) ............................................................................67 10.3 8-Pad WSON 8x6mm (Package Code ZE) .............................................................................68 10.4 8-Pad XSON 4x4x0.45-mm (Package Code XG) ...................................................................69 10.5 16-Pin SOIC 300-mil (Package Code SF) ...............................................................................70 10.7 24-Ball TFBGA 8x6-mm (Package Code TB, 5x5 Ball Array) .................................................71 10.8 24-Ball TFBGA 8x6-mm (Package Code TC, 6x4 ball array)..................................................72 10.9 12-Ball WLCSP (Package Code BY) .......................................................................................73 ORDERING INFORMATION ...............................................................................................................74 11.1 Valid Part Numbers and Top Side Marking .............................................................................75 REVISION IISTORY ............................................................................................................................76 -3- Publication Release Date: November 22, 2017 Revision I W25Q64JV 1. GENERAL DESCRIPTIONS The W25Q64JV (64M-bit) Serial Flash memory provides a storage solution for systems with limited space, pins and power. The 25Q series offers flexibility and performance well beyond ordinary Serial Flash devices. They are ideal for code shadowing to RAM, executing code directly from Dual/Quad SPI (XIP) and storing voice, text and data. The device operates on 2.7V to 3.6V power supply with current consumption as low as 1A for power-down. All devices are offered in space-saving packages. The W25Q64JV array is organized into 32,768 programmable pages of 256-bytes each. Up to 256 bytes can be programmed at a time. Pages can be erased in groups of 16 (4KB sector erase), groups of 128 (32KB block erase), groups of 256 (64KB block erase) or the entire chip (chip erase). The W25Q64JV has 2,048 erasable sectors and 128 erasable blocks respectively. The small 4KB sectors allow for greater flexibility in applications that require data and parameter storage. (See Figure 2.) The W25Q64JV supports the standard Serial Peripheral Interface (SPI), Dual/Quad I/O SPI: Serial Clock, Chip Select, Serial Data I/O0 (DI), I/O1 (DO), I/O2 and I/O3. SPI clock frequencies of W25Q64JV of up to 133MHz are supported allowing equivalent clock rates of 266MHz (133MHz x 2) for Dual I/O and 532MHz (133MHz x 4) for Quad I/O when using the Fast Read Dual/Quad I/O. These transfer rates can outperform standard Asynchronous 8 and 16-bit Parallel Flash memories. Additionally, the device supports JEDEC standard manufacturer and device ID, and a 64-bit Unique Serial Number and three 256-bytes Security Registers. 2. FEATURES New Family of SpiFlash Memories - W25Q64JV: 64M-bit / 8M-byte - Standard SPI: CLK, /CS, DI, DO - Dual SPI: CLK, /CS, IO0, IO1 - Quad SPI: CLK, /CS, IO0, IO1, IO2, IO3 - Software & Hardware Reset(1) Highest Performance Serial Flash - 133MHz Single, Dual/Quad SPI clocks 266/532MHz equivalent Dual/Quad SPI - Min. 100K Program-Erase cycles per sector - More than 20-year data retention Efficient "Continuous Read" - Continuous Read with 8/16/32/64-Byte Wrap - As few as 8 clocks to address memory - Allows true XIP (execute in place) operation - Outperforms X16 Parallel Flash Low Power, Wide Temperature Range - Single 2.7 to 3.6V supply - <1A Power-down (typ.) - -40C to +85C operating range Flexible Architecture with 4KB sectors - Uniform Sector/Block Erase (4K/32K/64K-Byte) - Program 1 to 256 byte per programmable page - Erase/Program Suspend & Resume Advanced Security Features - Software and Hardware Write-Protect - Special OTP protection - Top/Bottom, Complement array protection - Individual Block/Sector array protection - 64-Bit Unique ID for each device - Discoverable Parameters (SFDP) Register - 3X256-Bytes Security Registers - Volatile & Non-volatile Status Register Bits Space Efficient Packaging - 8-pin SOIC 208-mil - 8-pad WSON 6x5-mm/8x6-mm - 16-pin SOIC 300-mil - 8-pad XSON 4x4-mm - 24-ball TFBGA 8x6-mm (6x4 ball array) - 24-ball TFBGA 8x6-mm (6x4/5x5 ball array) - 12-ball WLCSP - Contact Winbond for KGD and other options Note: 1. Hardware /RESET pin is only available on TFBGA or SOIC16 packages -4- Publication Release Date: November 22, 2017 Revision I W25Q64JV 3. PACKAGE TYPES AND PIN CONFIGURATIONS 3.1 Pin Configuration SOIC 208-mil Top View /CS 1 8 VCC DO (IO1) 2 7 /HOLD or /RESET (IO3) /WP (IO2) 3 6 CLK GND 4 5 DI (IO0) Figure 1a. W25Q64JV Pin Assignments, 8-pin SOIC 208-mil (Package Code SS) 3.2 Pad Configuration WSON 6x5-mm/ 8x6-mm, XSON 4x4-mm Top View /CS 1 8 VCC DO (IO1) 2 7 /HOLD or /RESET (IO3) /WP (IO2) 3 6 CLK GND 4 5 DI (IO0) Figure 1b. W25Q64JV Pad Assignments, 8-pad WSON 6x5-mm/8x6 (Package Code ZP, ZE) 3.3 Pin Description SOIC 208-mil, WSON 6x5-mm/ 8x6-mm, XSON 4x4-mm PAD NO. PAD NAME I/O FUNCTION 1 /CS I 2 DO (IO1) I/O Chip Select Input Data Output (Data Input Output 1)(1) 3 /WP (IO2) I/O Write Protect Input ( Data Input Output 2)(2) 4 GND 5 DI (IO0) I/O 6 CLK I 7 /HOLD or /RESET (IO3) I/O 8 VCC Ground Data Input (Data Input Output 0)(1) Serial Clock Input Hold or Reset Input (Data Input Output 3)(2) Power Supply Notes: 1. 2. IO0 and IO1 are used for Standard and Dual SPI instructions IO0 - IO3 are used for Quad SPI instructions, /HOLD (or /RESET) function is only available for Standard/Dual SPI. -5- Publication Release Date: November 22, 2017 Revision I W25Q64JV 3.4 Pin Configuration SOIC 300-mil Top View IO3 1 16 CLK VCC 2 15 DI (IO0) /RESET 3 14 NC NC 4 13 NC NC 5 12 NC NC 6 11 NC /CS 7 10 GND DO (IO1) 8 9 IO2 Figure 1c. W25Q64JV Pin Assignments, 16-pin SOIC 300-mil (Package Code SF) 3.5 Pin Description SOIC 300-mil PIN NO. PIN NAME I/O FUNCTION 1 /HOLD or /RESET (IO3) I/O 2 VCC 3 /RESET 4 N/C No Connect 5 N/C No Connect 6 N/C No Connect 7 /CS I 8 DO (IO1) I/O Data Output (Data Input Output 1)(1) 9 /WP (IO2) I/O Write Protect Input (Data Input Output 2)(2) 10 GND Ground 11 N/C No Connect 12 N/C No Connect 13 N/C No Connect 14 N/C No Connect 15 DI (IO0) I/O 16 CLK I Hold or Reset Input (Data Input Output 3)(2) Power Supply I Reset Input(3) Chip Select Input Data Input (Data Input Output 0)(1) Serial Clock Input Notes: 1. IO0 and IO1 are used for Standard and Dual SPI instructions. 2. IO0 - IO3 are used for Quad SPI instructions, /HOLD (or /RESET) function is only available for Standard/Dual SPI. 3. The /RESET pin is a dedicated hardware reset pin regardless of device settings or operation states. If the hardware reset function is not used, this pin can be left floating or connected to VCC in the system. -6- Publication Release Date: November 22, 2017 Revision I W25Q64JV 3.6 Ball Configuration TFBGA 8x6-mm (5x5 or 6x4 Ball Array) Top View Top View A1 A2 A3 A4 NC NC NC /RESET A2 A3 A4 A5 NC NC /RESET NC B1 B2 B3 B4 B1 B2 B3 B4 B5 NC CLK GND VCC NC CLK GND VCC NC C1 C2 C3 C4 C1 C2 C3 C4 C5 NC /CS NC /WP (IO2) NC /CS NC /WP (IO2) NC D1 D2 D3 D4 D1 D2 D3 D4 D5 NC DO(IO1) NC DO(IO1) E1 E2 E3 NC NC NC DI(IO0) /HOLD(IO3) DI(IO0) /HOLD(IO3) NC E1 E2 E3 E4 E4 E5 NC NC NC NC NC NC F1 F2 F3 F4 NC NC NC NC Package Code B Package Code C Figure 1d. W25Q64JV Ball Assignments, 24-ball TFBGA 8x6-mm (Package Code TB/TC) 3.7 Ball Description TFBGA 5x5 or 8x6-mm BALL NO. PIN NAME I/O FUNCTION A4 /RESET I Reset Input(3) B2 CLK I Serial Clock Input B3 GND Ground B4 VCC Power Supply C2 /CS I C4 /WP (IO2) I/O Write Protect Input (Data Input Output 2)(2) D2 DO (IO1) I/O Data Output (Data Input Output 1)(1) D3 DI (IO0) I/O Data Input (Data Input Output 0)(1) D4 /HOLD (IO3) I/O Hold or Reset Input (Data Input Output 3)(2) Multiple NC Chip Select Input No Connect Notes: 1. IO0 and IO1 are used for Standard and Dual SPI instructions 2. IO0 - IO3 are used for Quad SPI instructions, /HOLD (or /RESET) function is only available for Standard/Dual SPI. 3. The /RESET pin is a dedicated hardware reset pin regardless of device settings or operation states. If the hardware reset function is not used, this pin can be left floating or connected to VCC in the system -7- Publication Release Date: November 22, 2017 Revision I W25Q64JV 3.8 Ball Configuration WLCSP Figure 1e. W25Q64JV Ball Assignments, 12-ball WLCSP (Package Code BY) 3.9 Ball Description WLCSP12 BALL NO. PIN NAME I/O FUNCTION B2 VCC B3 /CS I C2 /HOLD or /RESET (IO3) I/O Hold Input or /RESET (Data Input Output 3)(2) C3 DO (IO1) I/O Data Output (Data Input Output 1)(1) Power Supply Chip Select Input D2 CLK I D3 /WP (IO2) I/O Serial Clock Input Write Protect Input (Data Input Output 2)(2) E2 DI (IO0) I/O Data Input (Data Input Output 0)(1) E3 GND Ground Notes: 1. 2. IO0 and IO1 are used for Standard and Dual SPI instructions IO0 - IO3 are used for Quad SPI instructions, /HOLD (or /RESET) function is only available for Standard/Dual SPI. -8- Publication Release Date: November 22, 2017 Revision I W25Q64JV 4. PIN DESCRIPTIONS 4.1 Chip Select (/CS) The SPI Chip Select (/CS) pin enables and disables device operation. When /CS is high the device is deselected and the Serial Data Output (DO, or IO0, IO1, IO2, IO3) pins are at high impedance. When deselected, the devices power consumption will be at standby levels unless an internal erase, program or write status register cycle is in progress. When /CS is brought low the device will be selected, power consumption will increase to active levels and instructions can be written to and data read from the device. After power-up, /CS must transition from high to low before a new instruction will be accepted. The /CS input must track the VCC supply level at power-up and power-down (see "Write Protection" and Figure 58). If needed a pull-up resister on the /CS pin can be used to accomplish this. 4.2 Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3) The W25Q64JV supports standard SPI, Dual SPI and Quad SPI operation. Standard SPI instructions use the unidirectional DI (input) pin to serially write instructions, addresses or data to the device on the rising edge of the Serial Clock (CLK) input pin. Standard SPI also uses the unidirectional DO (output) to read data or status from the device on the falling edge of CLK. Dual and Quad SPI instructions use the bidirectional IO pins to serially write instructions, addresses or data to the device on the rising edge of CLK and read data or status from the device on the falling edge of CLK. Quad SPI instructions require the non-volatile Quad Enable bit (QE) in Status Register-2 to be set. When QE=1, the /WP pin becomes IO2 and the /HOLD pin becomes IO3. 4.3 Write Protect (/WP) The Write Protect (/WP) pin can be used to prevent the Status Register from being written. Used in conjunction with the Status Register's Block Protect (CMP, SEC, TB, BP2, BP1 and BP0) bits and Status Register Protect (SRP) bits, a portion as small as a 4KB sector or the entire memory array can be hardware protected. The /WP pin is active low. 4.4 HOLD (/HOLD) The /HOLD pin allows the device to be paused while it is actively selected. When /HOLD is brought low, while /CS is low, the DO pin will be at high impedance and signals on the DI and CLK pins will be ignored (don't care). When /HOLD is brought high, device operation can resume. The /HOLD function can be useful when multiple devices are sharing the same SPI signals. The /HOLD pin is active low. When the QE bit of Status Register-2 is set for Quad I/O, the /HOLD pin function is not available since this pin is used for IO3. See Figure 1a-c for the pin configuration of Quad I/O operation. 4.5 Serial Clock (CLK) The SPI Serial Clock Input (CLK) pin provides the timing for serial input and output operations. ("See SPI Operations") Reset (/RESET)(1) 4.6 A dedicated hardware /RESET pin is available on SOIC-16 and TFBGA packages. When it's driven low for a minimum period of ~1S, this device will terminate any external or internal operations and return to its power-on state. Note: 1. Hardware /RESET pin is available on SOIC-16 or TFBGA; please contact Winbond for this package. -9- Publication Release Date: November 22, 2017 Revision I W25Q64JV 5. BLOCK DIAGRAM SFDP Register 000000h Security Register 1 - 3 0000FFh 003000h 002000h 001000h 0030FFh 0020FFh 0010FFh Block Segmentation xxFF00h * xxF000h Sector 15 (4KB) xxFFFFh * xxF0FFh xxEF00h * xxE000h Sector 14 (4KB) xxEFFFh * xxE0FFh xxDF00h * xxD000h Sector 13 (4KB) xxDFFFh * xxD0FFh 7FFF00h * Block 127 (64KB) 7F0000h Sector 2 (4KB) xx2FFFh * xx20FFh xx1F00h * xx1000h Sector 1 (4KB) xx1FFFh * xx10FFh xx0F00h * xx0000h Sector 0 (4KB) xx0FFFh * xx00FFh Write Protect Logic and Row Decode xx2F00h * xx2000h 40FF00h * 400000h Block 64 (64KB) 40FFFFh * 4000FFh 3FFF00h * 3F0000h Block 63 (64KB) 3FFFFFh * 3F00FFh * * * Write Control Logic Status Register 20FF00h * 200000h Block 32 (64KB) 20FFFFh * 2000FFh 1FFF00h * 1F0000h Block 31 (64KB) 1FFFFFh * 1F00FFh * * * High Voltage Generators 00FF00h * 000000h /HOLD (IO3) CLK /CS SPI Command & Control Logic Page Address Latch / Counter W25Q64FV W25Q64JV * * * * * * /WP (IO2) 7FFFFFh * 7F00FFh Block 0 (64KB) Beginning Page Address 00FFFFh * 0000FFh Ending Page Address Column Decode And 256-Byte Page Buffer Data DI (IO0) DO (IO1) Byte Address Latch / Counter Figure 2. W25Q64JV Serial Flash Memory Block Diagram - 10 - Publication Release Date: November 22, 2017 Revision I W25Q64JV 6. FUNCTIONAL DESCRIPTIONS 6.1 Standard SPI Instructions The W25Q64JV is accessed through an SPI compatible bus consisting of four signals: Serial Clock (CLK), Chip Select (/CS), Serial Data Input (DI) and Serial Data Output (DO). Standard SPI instructions use the DI input pin to serially write instructions, addresses or data to the device on the rising edge of CLK. The DO output pin is used to read data or status from the device on the falling edge of CLK. SPI bus operation Mode 0 (0,0) and 3 (1,1) are supported. The primary difference between Mode 0 and Mode 3 concerns the normal state of the CLK signal when the SPI bus master is in standby and data is not being transferred to the Serial Flash. For Mode 0, the CLK signal is normally low on the falling and rising edges of /CS. For Mode 3, the CLK signal is normally high on the falling and rising edges of /CS. 6.2 Dual SPI Instructions The W25Q64JV supports Dual SPI operation when using instructions such as "Fast Read Dual Output (3Bh)" and "Fast Read Dual I/O (BBh)". These instructions allow data to be transferred to or from the device at two to three times the rate of ordinary Serial Flash devices. The Dual SPI Read instructions are ideal for quickly downloading code to RAM upon power-up (code-shadowing) or for executing non-speed-critical code directly from the SPI bus (XIP). When using Dual SPI instructions, the DI and DO pins become bidirectional I/O pins: IO0 and IO1. 6.3 Quad SPI Instructions The W25Q64JV supports Quad SPI operation when using instructions such as "Fast Read Quad Output (6Bh)", and "Fast Read Quad I/O (EBh). These instructions allow data to be transferred to or from the device four to six times the rate of ordinary Serial Flash. The Quad Read instructions offer a significant improvement in continuous and random access transfer rates allowing fast code-shadowing to RAM or execution directly from the SPI bus (XIP). When using Quad SPI instructions the DI and DO pins become bidirectional IO0 and IO1, with the additional I/O pins: IO2, IO3. Quad SPI instructions require the non-volatile Quad Enable bit (QE) in Status Register-2 to be set. 6.4 Software Reset & Hardware /RESET pin The W25Q64JV can be reset to the initial power-on state by a software Reset sequence. This sequence must include two consecutive instructions: Enable Reset (66h) & Reset (99h). If the instruction sequence is successfully accepted, the device will take approximately 30S (tRST) to reset. No instruction will be accepted during the reset period. For the SOIC-16 and TFBGA packages, W25Q64JV provides a dedicated hardware /RESET pin. Drive the /RESET pin low for a minimum period of ~1S (tRESET*) will interrupt any on-going external/internal operations and reset the device to its initial power-on state. Hardware /RESET pin has higher priority than other SPI input signals (/CS, CLK, IOs). Note: 1. Hardware /RESET pin is available on SOIC-16 or TFBGA; please contact Winbond for his package. 2. While a faster /RESET pulse (as short as a few hundred nanoseconds) will often reset the device, a 1us minimum is recommended to ensure reliable operation. 3. There is an internal pull-up resistor for the dedicated /RESET pin on the SOIC-16 and TFBGA-24 package. If the reset function is not needed, this pin can be left floating in the system. - 11 - Publication Release Date: November 22, 2017 Revision I W25Q64JV 6.5 Write Protection Applications that use non-volatile memory must take into consideration the possibility of noise and other adverse system conditions that may compromise data integrity. To address this concern, the W 25Q64JV provides several means to protect the data from inadvertent writes. Write Protect Features Device resets when VCC is below threshold Time delay write disable after Power-up Write enable/disable instructions and automatic write disable after erase or program Software and Hardware (/WP pin) write protection using Status Registers Additional Individual Block/Sector Locks for array protection Write Protection using Power-down instruction Lock Down write protection for Status Register until the next power-up One Time Program (OTP) write protection for array and Security Registers using Status Register * * Note: This feature is available upon special order. Please contact Winbond for details. Upon power-up or at power-down, the W25Q64JV will maintain a reset condition while VCC is below the threshold value of VWI, (See Power-up Timing and Voltage Levels and Figure 43). While reset, all operations are disabled and no instructions are recognized. During power-up and after the VCC voltage exceeds VWI, all program and erase related instructions are further disabled for a time delay of t PUW. This includes the Write Enable, Page Program, Sector Erase, Block Erase, Chip Erase and the Write Status Register instructions. Note that the chip select pin (/CS) must track the VCC supply level at power-up until the VCCmin level and tVSL time delay is reached, and it must also track the VCC supply level at power-down to prevent adverse command sequence. If needed a pull-up resister on /CS can be used to accomplish this. After power-up the device is automatically placed in a write-disabled state with the Status Register Write Enable Latch (WEL) set to a 0. A Write Enable instruction must be issued before a Page Program, Sector Erase, Block Erase, Chip Erase or Write Status Register instruction will be accepted. After completing a program, erase or write instruction the Write Enable Latch (WEL) is automatically cleared to a write-disabled state of 0. Software controlled write protection is facilitated using the Write Status Register instruction and setting the Status Register Protect (SRP, SRL) and Block Protect (CMP, TB, BP[3:0]) bits. These settings allow a portion or the entire memory array to be configured as read only. Used in conjunction with the Write Protect (/WP) pin, changes to the Status Register can be enabled or disabled under hardware control. See Status Register section for further information. Additionally, the Power-down instruction offers an extra level of write protection as all instructions are ignored except for the Release Power-down instruction. The W25Q64JV also provides another Write Protect method using the Individual Block Locks. Each 64KB block (except the top and bottom blocks, total of 126 blocks) and each 4KB sector within the top/bottom blocks (total of 32 sectors) are equipped with an Individual Block Lock bit. When the lock bit is 0, the corresponding sector or block can be erased or programmed; when the lock bit is set to 1, Erase or Program commands issued to the corresponding sector or block will be ignored. When the device is powered on, all Individual Block Lock bits will be 1, so the entire memory array is protected from Erase/Program. An "Individual Block Unlock (39h)" instruction must be issued to unlock any specific sector or block. The WPS bit in Status Register-3 is used to decide which Write Protect scheme should be used. When WPS=0 (factory default), the device will only utilize CMP, SEC, TB, BP[2:0] bits to protect specific areas of the array; when WPS=1, the device will utilize the Individual Block Locks for write protection. - 12 - Publication Release Date: November 22, 2017 Revision I W25Q64JV 7. STATUS AND CONFIGURATION REGISTERS Three Status and Configuration Registers are provided for W25Q64JV. The Read Status Register-1/2/3 instructions can be used to provide status on the availability of the flash memory array, whether the device is write enabled or disabled, the state of write protection, Quad SPI setting, Security Register lock status, Erase/Program Suspend status, output driver strength, power-up. The Write Status Register instruction can be used to configure the device write protection features, Quad SPI setting, Security Register OTP locks, and output driver strength. Write access to the Status Register is controlled by the state of the nonvolatile Status Register Protect bits (SRL), the Write Enable instruction, and during Standard/Dual SPI operations 7.1 Status Registers S7 S6 S5 S4 S3 S2 S1 S0 SRP SEC TB BP2 BP1 BP0 WEL BUSY STATUS R EGISTER PROTECT (non-volatile) SECTOR PROTECT (non-volatile) TOP/BOTT OM PROTECT (non-volatile) BLOCK PROTECT BIT S (non-volatile) WRITE ENABLE LATCH ERASE/WRITE IN PROGRESS (volatile) Figure 4a. Status Register-1 Erase/Write In Progress (BUSY) - Status Only BUSY is a read only bit in the status register (S0) that is set to a 1 state when the device is executing a Page Program, Quad Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register or Erase/Program Security Register instruction. During this time the device will ignore further instructions except for the Read Status Register and Erase/Program Suspend instruction (see t W, tPP, tSE, tBE, and tCE in AC Characteristics). When the program, erase or write status/security register instruction has completed, the BUSY bit will be cleared to a 0 state indicating the device is ready for further instructions. Write Enable Latch (WEL) - Status Only Write Enable Latch (WEL) is a read only bit in the status register (S1) that is set to 1 after executing a Write Enable Instruction. The WEL status bit is cleared to 0 when the device is write disabled. A write disable state occurs upon power-up or after any of the following instructions: Write Disable, Page Program, Quad Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, Erase Security Register and Program Security Register. Block Protect Bits (BP2, BP1, BP0) - Volatile/Non-Volatile Writable The Block Protect Bits (BP2, BP1, BP0) are non-volatile read/write bits in the status register (S4, S3, and S2) that provide Write Protection control and status. Block Protect bits can be set using the Write Status Register Instruction (see tW in AC characteristics). All, none or a portion of the memory array can be protected from Program and Erase instructions (see Status Register Memory Protection table). The factory default setting for the Block Protection Bits is 0, none of the array protected. - 13 - Publication Release Date: November 22, 2017 Revision I W25Q64JV Top/Bottom Block Protect (TB) - Volatile/Non-Volatile Writable The non-volatile Top/Bottom bit (TB) controls if the Block Protect Bits (BP2, BP1, BP0) protect from the Top (TB=0) or the Bottom (TB=1) of the array as shown in the Status Register Memory Protection table. The factory default setting is TB=0. The TB bit can be set with the Write Status Register Instruction depending on the state of the SRP/SRL and WEL bits. Sector/Block Protect Bit (SEC) - Volatile/Non-Volatile Writable The non-volatile Sector/Block Protect bit (SEC) controls if the Block Protect Bits (BP2, BP1, BP0) protect either 4KB Sectors (SEC=1) or 64KB Blocks (SEC=0) in the Top (TB=0) or the Bottom (TB=1) of the array as shown in the Status Register Memory Protection table. The default setting is SEC=0. Complement Protect (CMP) - Volatile/Non-Volatile Writable The Complement Protect bit (CMP) is a non-volatile read/write bit in the status register (S14). It is used in conjunction with SEC, TB, BP2, BP1 and BP0 bits to provide more flexibility for the array protection. Once CMP is set to 1, previous array protection set by SEC, TB, BP2, BP1 and BP0 will be reversed. For instance, when CMP=0, a top 64KB block can be protected while the rest of the array is not; when CMP=1, the top 64KB block will become unprotected while the rest of the array become read-only. Please refer to the Status Register Memory Protection table for details. The default setting is CMP=0. - 14 - Publication Release Date: November 22, 2017 Revision I W25Q64JV Status Register Protect (SRP, SRL) - Volatile/Non-Volatile Writable Three Status and Configuration Registers are provided for W25Q64JV. The Read Status Register-1/2/3 instructions can be used to provide status on the availability of the flash memory array, whether the device is write enabled or disabled, the state of write protection, Quad SPI setting, Security Register lock status, Erase/Program Suspend status, and output driver strength, The Write Status Register instruction can be used to configure the device write protection features, Quad SPI setting, Security Register OTP locks, output driver. Write access to the Status Register is controlled by the state of the non-volatile Status Register Protect bits (SRP, SRL), the Write Enable instruction, and during Standard/Dual SPI operations, the /WP pin. Status Register Description X Software Protection /WP pin has no control. The Status register can be written to after a Write Enable instruction, WEL=1. [Factory Default] 1 0 Hardware Protected When /WP pin is low the Status Register locked and cannot be written to. 0 1 1 Hardware Unprotected When /WP pin is high the Status register is unlocked and can be written to after a Write Enable instruction, WEL=1. 1 X X Power Supply Lock-Down Status Register is protected and cannot be written to again until the next power-down, power-up cycle.(1) 1 X X One Time Program(2) Status Register is permanently protected and cannot be written to. (enabled by adding prefix command AAh, 55h) SRL SRP /WP 0 0 0 1. When SRL =1, a power-down, power-up cycle will change SRL =0 state. 2. Please contact Winbond for details regarding the special instruction sequence. - 15 - Publication Release Date: November 22, 2017 Revision I W25Q64JV S1 5 S1 4 S1 3 S1 2 S1 1 S1 0 S9 S8 SUS CMP LB3 LB2 LB1 (R) QE SRL SUSPEND STATUS (Status-Onl y) COMPLEMENT PROTECT (Volatile/Non-Volatile Writable) SECUR ITY REGISTER LOCK BITS (Volatile/Non-Volatile Writable) Re served QUAD ENABLE (Volatile/Non-Volatile Writable) STATUS REGISTER Lock (Volatile/Non-Volatile Writable) Figure 4b. Status Register-2 Erase/Program Suspend Status (SUS) - Status Only The Suspend Status bit is a read only bit in the status register (S15) that is set to 1 after executing a Erase/Program Suspend (75h) instruction. The SUS status bit is cleared to 0 by Erase/Program Resume (7Ah) instruction as well as a power-down, power-up cycle. Security Register Lock Bits (LB3, LB2, LB1) - Volatile/Non-Volatile OTP Writable The Security Register Lock Bits (LB3, LB2, LB1) are non-volatile One Time Program (OTP) bits in Status Register (S13, S12, S11) that provide the write protect control and status to the Security Registers. The default state of LB3-1 is 0, Security Registers are unlocked. LB3-1 can be set to 1 individually using the Write Status Register instruction. LB3-1 are One Time Programmable (OTP), once it's set to 1, the corresponding 256-Byte Security Register will become read-only permanently. Quad Enable (QE) - Volatile/Non-Volatile Writable The Quad Enable (QE) bit is a non-volatile read/write bit in the status register (S9) that enables Quad SPI operation. When the QE bit is set to a 0 state (factory default for part numbers with ordering options "IM"), the /HOLD are enabled, the device operates in Standard/Dual SPI modes. When the QE bit is set to a 1 (factory fixed default for part numbers with ordering options "IQ"), the Quad IO2 and IO3 pins are enabled, and /HOLD function is disabled, the device operates in Standard/Dual/Quad SPI modes. - 16 - Publication Release Date: November 22, 2017 Revision I W25Q64JV Figure 4c. Status Register-3 Write Protect Selection (WPS) - Volatile/Non-Volatile Writable The WPS bit is used to select which Write Protect scheme should be used. When WPS=0, the device will use the combination of CMP, SEC, TB, BP[2:0] bits to protect a specific area of the memory array. When WPS=1, the device will utilize the Individual Block Locks to protect any individual sector or blocks. The default value for all Individual Block Lock bits is 1 upon device power on or after reset. Output Driver Strength (DRV1, DRV0) - Volatile/Non-Volatile Writable The DRV1 & DRV0 bits are used to determine the output driver strength for the Read operations. DRV1, DRV0 Driver Strength 0, 0 100% 0, 1 75% 1, 0 50% 1, 1 25% (default) Reserved Bits - Non Functional There are a few reserved Status Register bits that may be read out as a "0" or "1". It is recommended to ignore the values of those bits. During a "Write Status Register" instruction, the Reserved Bits can be written as "0", but there will not be any effects. - 17 - Publication Release Date: November 22, 2017 Revision I W25Q64JV Status Register Memory Protection (WPS = 0, CMP = 0) STATUS REGISTER(1) W25Q64JV (64M-BIT) MEMORY PROTECTION(3) SEC TB BP2 BP1 BP0 PROTECTED BLOCK(S) PROTECTED ADDRESSES PROTECTED DENSITY PROTECTED PORTION(2) X X 0 0 0 NONE NONE NONE NONE 0 0 0 0 1 126 and 127 7E0000h - 7FFFFFh 128KB Upper 1/64 0 0 0 1 0 124 thru 127 7C0000h - 7FFFFFh 256KB Upper 1/32 0 0 0 1 1 120 thru 127 780000h - 7FFFFFh 512KB Upper 1/16 0 0 1 0 0 112 thru 127 700000h - 7FFFFFh 1MB Upper 1/8 0 0 1 0 1 96 thru 127 600000h - 7FFFFFh 2MB Upper 1/4 0 0 1 1 0 64 thru 127 400000h - 7FFFFFh 4MB Upper 1/2 0 1 0 0 1 0 and 1 000000h - 01FFFFh 128KB Lower 1/64 0 1 0 1 0 0 thru 3 000000h - 03FFFFh 256KB Lower 1/32 0 1 0 1 1 0 thru 7 000000h - 07FFFFh 512KB Lower 1/16 0 1 1 0 0 0 thru 15 000000h - 0FFFFFh 1MB Lower 1/8 0 1 1 0 1 0 thru 31 000000h - 1FFFFFh 2MB Lower 1/4 0 1 1 1 0 0 thru 63 000000h - 3FFFFFh 4MB Lower 1/2 X X 1 1 1 0 thru 127 000000h - 7FFFFFh 8MB ALL 1 0 0 0 1 127 7FF000h - 7FFFFFh 4KB U - 1/2048 1 0 0 1 0 127 7FE000h - 7FFFFFh 8KB U - 1/1024 1 0 0 1 1 127 7FC000h - 7FFFFFh 16KB U - 1/512 1 0 1 0 X 127 7F8000h - 7FFFFFh 32KB U - 1/256 1 1 0 0 1 0 000000h - 000FFFh 4KB L - 1/2048 1 1 0 1 0 0 000000h - 001FFFh 8KB L - 1/1024 1 1 0 1 1 0 000000h - 003FFFh 16KB L - 1/512 1 1 1 0 X 0 000000h - 007FFFh 32KB L - 1/256 Notes: 1. X = don't care 2. L = Lower; U = Upper 3. If any Erase or Program command specifies a memory region that contains protected data portion, this command will be ignored. - 18 - Publication Release Date: November 22, 2017 Revision I W25Q64JV Status Register Memory Protection (WPS = 0, CMP = 1) STATUS REGISTER(1) W25Q64JV (64M-BIT) MEMORY PROTECTION(3) SEC TB BP2 BP1 BP0 PROTECTED BLOCK(S) PROTECTED ADDRESSES PROTECTED DENSITY PROTECTED PORTION(2) X X 0 0 0 0 thru 127 000000h - 7FFFFFh 8MB ALL 0 0 0 0 1 0 thru 125 000000h - 7DFFFFh 8,064KB Lower 63/64 0 0 0 1 0 0 thru 123 000000h - 7BFFFFh 7,936KB Lower 31/32 0 0 0 1 1 0 thru 119 000000h - 77FFFFh 7,680KB Lower 15/16 0 0 1 0 0 0 thru 111 000000h - 6FFFFFh 7MB Lower 7/8 0 0 1 0 1 0 thru 95 000000h - 5FFFFFh 5MB Lower 3/4 0 0 1 1 0 0 thru 63 000000h - 3FFFFFh 4MB Lower 1/2 0 1 0 0 1 2 thru 127 020000h - 7FFFFFh 8,064KB Upper 63/64 0 1 0 1 0 4 thru 127 040000h - 7FFFFFh 7,936KB Upper 31/32 0 1 0 1 1 8 thru 127 080000h - 7FFFFFh 7,680KB Upper 15/16 0 1 1 0 0 16 thru 127 100000h - 7FFFFFh 7MB Upper 7/8 0 1 1 0 1 32 thru 127 200000h - 7FFFFFh 5MB Upper 3/4 0 1 1 1 0 64 thru 127 400000h - 7FFFFFh 4MB Upper 1/2 X X 1 1 1 NONE NONE NONE NONE 1 0 0 0 1 0 thru 127 000000h - 7FEFFFh 8,188KB L - 2047/2048 1 0 0 1 0 0 thru 127 000000h - 7FDFFFh 8,184KB L - 1023/1024 1 0 0 1 1 0 thru 127 000000h - 7FBFFFh 8,176KB L - 511/512 1 0 1 0 X 0 thru 127 000000h - 7F7FFFh 8,160KB L - 255/256 1 1 0 0 1 0 thru 127 001000h - 7FFFFFh 8,188KB L - 2047/2048 1 1 0 1 0 0 thru 127 002000h - 7FFFFFh 8,184KB L - 1023/1024 1 1 0 1 1 0 thru 127 004000h - 7FFFFFh 8,176KB L - 511/512 1 1 1 0 X 0 thru 127 008000h - 7FFFFFh 8,160KB L - 255/256 Notes: 1. X = don't care 2. L = Lower; U = Upper 3. If any Erase or Program command specifies a memory region that contains protected data portion, this command will be ignored. - 19 - Publication Release Date: November 22, 2017 Revision I W25Q64JV Block 127 (64KB) Individual Block Memory Protection (WPS=1) Sector 15 (4KB) Sector 14 (4KB) Sector 1 (4KB) Sector 0 (4KB) Individual Block Locks: 32 Sectors (Top/Bottom) 126 Blocks Block 126 (64KB) Individual Block Lock: 36h + Address Individual Block Unlock: 39h + Address Read Block Lock: 3Dh + Address Global Block Lock: 7Eh Block 0 (64KB) Block 1 (64KB) Global Block Unlock: 98h Sector 15 (4KB) Sector 14 (4KB) Sector 1 (4KB) Sector 0 (4KB) Figure 4d. Individual Block/Sector Locks Notes: 1. 2. Individual Block/Sector protection is only valid when WPS=1. All individual block/sector lock bits are set to 1 by default after power up, all memory array is protected. - 20 - Publication Release Date: November 22, 2017 Revision I W25Q64JV 8. INSTRUCTIONS The Standard/Dual/Quad SPI instruction set of the W25Q64JV consists of 48 basic instructions that are fully controlled through the SPI bus (see Instruction Set Table1-2). Instructions are initiated with the falling edge of Chip Select (/CS). The first byte of data clocked into the DI input provides the instruction code. Data on the DI input is sampled on the rising edge of clock with most significant bit (MSB) first. Instructions vary in length from a single byte to several bytes and may be followed by address bytes, data bytes, dummy bytes (don't care), and in some cases, a combination. Instructions are completed with the rising edge of edge /CS. Clock relative timing diagrams for each instruction are included in Figures 5 through 57. All read instructions can be completed after any clocked bit. However, all instructions that Write, Program or Erase must complete on a byte boundary (/CS driven high after a full 8-bits have been clocked) otherwise the instruction will be ignored. This feature further protects the device from inadvertent writes. Additionally, while the memory is being programmed or erased, or when the Status Register is being written, all instructions except for Read Status Register will be ignored until the program or erase cycle has completed. 8.1 Device ID and Instruction Set Tables Manufacturer and Device Identification MANUFACTURER ID (MF7 - MF0) Winbond Serial Flash EFh Device ID (ID7 - ID0) (ID15 - ID0) Instruction ABh, 90h, 92h, 94h 9Fh W25Q64JV-IQ 16h 4017h W25Q64JV-IM* 16h 7017h Note: For DTR, QPI supporting, please refer to W25Q64JV DTR datasheet. - 21 - Publication Release Date: November 22, 2017 Revision I W25Q64JV Instruction Set Table 1 (Standard SPI Instructions)(1) Data Input Output Number of Clock(1-1-1) Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 Byte 7 8 8 8 8 8 8 8 Dummy Dummy Dummy (ID7-ID0)(2) (MF7-MF0) (ID7-ID0) (UID63-0) Write Enable 06h Volatile SR Write Enable 50h Write Disable 04h Release Power-down / ID ABh Manufacturer/Device ID 90h Dummy Dummy 00h JEDEC ID 9Fh (MF7-MF0) (ID15-ID8) (ID7-ID0) Read Unique ID 4Bh Dummy Dummy Dummy Dummy Read Data 03h A23-A16 A15-A8 A7-A0 (D7-D0) Fast Read 0Bh A23-A16 A15-A8 A7-A0 Dummy (D7-D0) Page Program 02h A23-A16 A15-A8 A7-A0 D7-D0 D7-D0(3) Sector Erase (4KB) 20h A23-A16 A15-A8 A7-A0 Block Erase (32KB) 52h A23-A16 A15-A8 A7-A0 Block Erase (64KB) D8h A23-A16 A15-A8 A7-A0 dummy (D7-0) Chip Erase C7h/60h 05h (S7-S0)(2) Write Status Register-1 01h (S7-S0)(4) Read Status Register-2 35h (S15-S8)(2) Write Status Register-2 31h (S15-S8) Read Status Register-3 15h (S23-S16)(2) Write Status Register-3 11h (S23-S16) Read SFDP Register 5Ah 00h 00h A7-A0 44h A23-A16 A15-A8 A7-A0 42h A23-A16 A15-A8 A7-A0 D7-D0 D7-D0(3) 48h A23-A16 A15-A8 A7-A0 Dummy (D7-D0) (L7-L0) Read Status Register-1 (4) Erase Security Register (5) Program Security Register(5) Read Security Register (5) Global Block Lock 7Eh Global Block Unlock 98h Read Block Lock 3Dh A23-A16 A15-A8 A7-A0 Individual Block Lock 36h A23-A16 A15-A8 A7-A0 Individual Block Unlock 39h A23-A16 A15-A8 A7-A0 Erase / Program Suspend 75h Erase / Program Resume 7Ah Power-down B9h Enable Reset 66h Reset Device 99h - 22 - Publication Release Date: November 22, 2017 Revision I W25Q64JV Instruction Set Table 2 (Dual/Quad SPI Instructions)(1) Data Input Output Number of Clock(1-1-2) Byte 1 8 Byte 2 8 Byte 3 8 Byte 4 8 Byte 5 4 Byte 6 4 Byte 7 4 Fast Read Dual Output 3Bh A23-A16 A15-A8 A7-A0 Dummy Dummy (D7-D0)(7) Number of Clock(1-2-2) 8 4 4 4 4 4 4 BBh A23-A16(6) A15-A8(6) A7-A0(6) Dummy(11) Mftr./Device ID Dual I/O 92h (6) (6) Number of Clock(1-1-4) 8 Fast Read Dual I/O A23-A16 8 A15-A8 8 (6) 00 8 Quad Input Page Program 32h A23-A16 A15-A8 A7-A0 Fast Read Quad Output 6Bh A23-A16 A15-A8 A7-A0 Number of Clock(1-4-4) 8 (8) 2 (8) 2 (8) 2 (11) Dummy 2 (9) (D7-D0) Byte 8 4 Byte 9 4 4 4 (D7-D0)(7) (MF7-MF0) (ID7-ID0)(7) 2 2 2 2 (3) (D7-D0) ... Dummy Dummy Dummy Dummy (D7-D0)(10) 2 2 2 2 2 (ID7-ID0) Mftr./Device ID Quad I/O 94h A23-A16 A15-A8 00 Dummy(11) Dummy Dummy (MF7-MF0) Fast Read Quad I/O EBh A23-A16 A15-A8 A7-A0 Dummy(11) Dummy Dummy (D7-D0) Set Burst with Wrap 77h Dummy Dummy Dummy W8-W0 Data bytes are shifted with Most Significant Bit first. Byte fields with data in parenthesis "( )" indicate data output from the device on either 1, 2 or 4 IO pins. 2. The Status Register contents and Device ID will repeat continuously until /CS terminates the instruction. 3. At least one byte of data input is required for Page Program, Quad Page Program and Program Security Registers, up to 256 bytes of data input. If more than 256 bytes of data are sent to the device, the addressing will wrap to the beginning of the page and overwrite previously sent data. 4. Write Status Register-1 (01h) can also be used to program Status Register-1&2, see section 8.2.5. 5. Security Register Address: Security Register 1: A23-16 = 00h; A15-8 = 10h; A7-0 = byte address Security Register 2: A23-16 = 00h; A15-8 = 20h; A7-0 = byte address Security Register 3: A23-16 = 00h; A15-8 = 30h; A7-0 = byte address 6. Dual SPI address input format: IO0 = A22, A20, A18, A16, A14, A12, A10, A8 A6, A4, A2, A0, M6, M4, M2, M0 IO1 = A23, A21, A19, A17, A15, A13, A11, A9 A7, A5, A3, A1, M7, M5, M3, M1 7. Dual SPI data output format: IO0 = (D6, D4, D2, D0) IO1 = (D7, D5, D3, D1) 8. Quad SPI address input format: Set Burst with Wrap input format: IO0 = A20, A16, A12, A8, A4, A0, M4, M0 IO0 = x, x, x, x, x, x, W4, x IO1 = A21, A17, A13, A9, A5, A1, M5, M1 IO1 = x, x, x, x, x, x, W5, x IO2 = A22, A18, A14, A10, A6, A2, M6, M2 IO2 = x, x, x, x, x, x, W6, x IO3 = A23, A19, A15, A11, A7, A3, M7, M3 IO3 = x, x, x, x, x, x, x, x 9. Quad SPI data input/output format: IO0 = (D4, D0, .....) IO1 = (D5, D1, .....) IO2 = (D6, D2, .....) IO3 = (D7, D3, .....) 10. Fast Read Quad I/O data output format: IO0 = (x, x, x, x, D4, D0, D4, D0) IO1 = (x, x, x, x, D5, D1, D5, D1) IO2 = (x, x, x, x, D6, D2, D6, D2) IO3 = (x, x, x, x, D7, D3, D7, D3) 11. The first dummy is M7-M0 should be set to Fxh 1. - 23 - Publication Release Date: November 22, 2017 Revision I W25Q64JV 8.2 Instruction Descriptions Write Enable (06h) The Write Enable instruction (Figure 5) sets the Write Enable Latch (WEL) bit in the Status Register to a 1. The WEL bit must be set prior to every Page Program, Quad Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register and Erase/Program Security Registers instruction. The Write Enable instruction is entered by driving /CS low, shifting the instruction code "06h" into the Data Input (DI) pin on the rising edge of CLK, and then driving /CS high. /CS Mode 3 CLK 0 1 2 3 4 5 6 7 Mode 0 Mode 3 Mode 0 Instruction (06h) DI (IO0) High Impedance DO (IO1) Figure 5. Write Enable Instruction for SPI Mode Write Enable for Volatile Status Register (50h) The non-volatile Status Register bits described in section 7.1 can also be written to as volatile bits. This gives more flexibility to change the system configuration and memory protection schemes quickly without waiting for the typical non-volatile bit write cycles or affecting the endurance of the Status Register nonvolatile bits. To write the volatile values into the Status Register bits, the Write Enable for Volatile Status Register (50h) instruction must be issued prior to a Write Status Register (01h) instruction. Write Enable for Volatile Status Register instruction (Figure 6) will not set the Write Enable Latch (WEL) bit, it is only valid for the Write Status Register instruction to change the volatile Status Register bit values. /CS Mode 3 CLK 0 1 2 3 4 Mode 0 5 6 7 Mode 3 Mode 0 Instruction (50h) DI (IO0) DO (IO1) High Impedance Figure 6. Write Enable for Volatile Status Register Instruction for SPI Mode) - 24 - Publication Release Date: November 22, 2017 Revision I W25Q64JV Write Disable (04h) The Write Disable instruction (Figure 7) resets the Write Enable Latch (WEL) bit in the Status Register to a 0. The Write Disable instruction is entered by driving /CS low, shifting the instruction code "04h" into the DI pin and then driving /CS high. Note that the WEL bit is automatically reset after Power-up and upon completion of the Write Status Register, Erase/Program Security Registers, Page Program, Quad Page Program, Sector Erase, Block Erase, Chip Erase and Reset instructions. /CS Mode 3 CLK 0 1 2 3 4 5 6 7 Mode 3 Mode 0 Mode 0 Instruction (04h) DI (IO0) High Impedance DO (IO1) Figure 7. Write Disable Instruction for SPI Mode Read Status Register-1 (05h), Status Register-2 (35h) & Status Register-3 (15h) The Read Status Register instructions allow the 8-bit Status Registers to be read. The instruction is entered by driving /CS low and shifting the instruction code "05h" for Status Register-1, "35h" for Status Register-2 or "15h" for Status Register-3 into the DI pin on the rising edge of CLK. The status register bits are then shifted out on the DO pin at the falling edge of CLK with most significant bit (MSB) first as shown in Figure 8. Refer to section 7.1 for Status Register descriptions. The Read Status Register instruction may be used at any time, even while a Program, Erase or Write Status Register cycle is in progress. This allows the BUSY status bit to be checked to determine when the cycle is complete and if the device can accept another instruction. The Status Register can be read continuously, as shown in Figure 8. The instruction is completed by driving /CS high. /CS Mode 3 CLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Mode 0 Instruction (05h/35h/15h) DI (IO0) High Impedance DO (IO1) * = MSB Status Register-1/2/3 out 7 6 5 4 3 2 1 Status Register-1/2/3 out 0 * 7 6 5 4 3 2 1 0 7 * Figure 8. Read Status Register Instruction - 25 - Publication Release Date: November 22, 2017 Revision I W25Q64JV Write Status Register-1 (01h), Status Register-2 (31h) & Status Register-3 (11h) The Write Status Register instruction allows the Status Registers to be written. The writable Status Register bits include:SEC, TB, BP[2:0] in Status Register-1; CMP, LB[3:1], QE, SRL in Status Register-2; DRV1, DRV0, WPS in Status Register-3. All other Status Register bit locations are read-only and will not be affected by the Write Status Register instruction. LB[3:1] are non-volatile OTP bits, once it is set to 1, it cannot be cleared to 0. To write non-volatile Status Register bits, a standard Write Enable (06h) instruction must previously have been executed for the device to accept the Write Status Register instruction (Status Register bit WEL must equal 1). Once write enabled, the instruction is entered by driving /CS low, sending the instruction code "01h/31h/11h", and then writing the status register data byte as illustrated in Figure 9a. To write volatile Status Register bits, a Write Enable for Volatile Status Register (50h) instruction must have been executed prior to the Write Status Register instruction (Status Register bit WEL remains 0). However, SRL and LB[3:1] cannot be changed from "1" to "0" because of the OTP protection for these bits. Upon power off or the execution of a Software/Hardware Reset, the volatile Status Register bit values will be lost, and the non-volatile Status Register bit values will be restored. During non-volatile Status Register write operation (06h combined with 01h/31h/11h), after /CS is driven high, the self-timed Write Status Register cycle will commence for a time duration of tW (See AC Characteristics). While the Write Status Register cycle is in progress, the Read Status Register instruction may still be accessed to check the status of the BUSY bit. The BUSY bit is a 1 during the Write Status Register cycle and a 0 when the cycle is finished and ready to accept other instructions again. After the Write Status Register cycle has finished, the Write Enable Latch (WEL) bit in the Status Register will be cleared to 0. During volatile Status Register write operation (50h combined with 01h/31h/11h), after /CS is driven high, the Status Register bits will be refreshed to the new values within the time period of t SHSL2 (See AC Characteristics). BUSY bit will remain 0 during the Status Register bit refresh period. Refer to section 7.1 for Status Register descriptions. /CS Mode 3 CLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Mode 0 Mode 3 Mode 0 Instruction (01h/31h/11h) Register-1/2/3 in DI (IO0) 7 6 5 4 3 2 1 0 * High Impedance DO (IO1) * = MSB Figure 9a. Write Status Register-1/2/3 Instruction - 26 - Publication Release Date: November 22, 2017 Revision I W25Q64JV The W25Q64JV is also backward compatible to Winbond's previous generations of serial flash memories, in which the Status Register-1&2 can be written using a single "Write Status Register-1 (01h)" command. To complete the Write Status Register-1&2 instruction, the /CS pin must be driven high after the sixteenth bit of data that is clocked in as shown in Figure 9c. If /CS is driven high after the eighth clock, the Write Status Register-1 (01h) instruction will only program the Status Register-1, the Status Register-2 will not be affected (Previous generations will clear CMP and QE bits). /CS Mode 3 CLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Mode 0 Mode 0 Instruction (01h) DI (IO0) Mode 3 Status Register 1 in 7 6 5 4 3 * 2 Status Register 2 in 1 0 15 14 13 12 11 10 9 8 * High Impedance DO (IO1) * = MSB Figure 9c. Write Status Register-1/2 Instruction - 27 - Publication Release Date: November 22, 2017 Revision I W25Q64JV Read Data (03h) The Read Data instruction allows one or more data bytes to be sequentially read from the memory. The instruction is initiated by driving the /CS pin low and then shifting the instruction code "03h" followed by a 24-bit address (A23-A0) into the DI pin. The code and address bits are latched on the rising edge of the CLK pin. After the address is received, the data byte of the addressed memory location will be shifted out on the DO pin at the falling edge of CLK with most significant bit (MSB) first. The address is automatically incremented to the next higher address after each byte of data is shifted out allowing for a continuous stream of data. This means that the entire memory can be accessed with a single instruction as long as the clock continues. The instruction is completed by driving /CS high. The Read Data instruction sequence is shown in Figure 14. If a Read Data instruction is issued while an Erase, Program or Write cycle is in process (BUSY=1) the instruction is ignored and will not have any effects on the current cycle. The Read Data instruction allows clock rates from D.C. to a maximum of f R (see AC Electrical Characteristics). The Read Data (03h) instruction is only supported in Standard SPI mode. /CS Mode 3 CLK 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 Mode 0 Instruction (03h) 24-Bit Address DI (IO0) 23 22 21 3 2 1 0 * Data Out 1 High Impedance DO (IO1) 7 6 5 4 3 2 1 0 7 * * = MSB Figure 14. Read Data Instruction - 28 - Publication Release Date: November 22, 2017 Revision I W25Q64JV Fast Read (0Bh) The Fast Read instruction is similar to the Read Data instruction except that it can operate at the highest possible frequency of FR (see AC Electrical Characteristics). This is accomplished by adding eight "dummy" clocks after the 24-bit address as shown in Figure 16. The dummy clocks allow the devices internal circuits additional time for setting up the initial address. During the dummy clocks the data value on the DO pin is a "don't care". /CS Mode 3 CLK 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 Mode 0 Instruction (0Bh) 24-Bit Address DI (IO0) 23 22 21 42 43 3 2 1 0 45 46 47 48 * High Impedance DO (IO1) * = MSB /CS 31 32 33 34 35 36 37 38 39 40 41 44 49 50 51 52 53 54 55 CLK Dummy Clocks DI (IO0) DO (IO1) 0 High Impedance Data Out 1 7 6 5 4 3 Data Out 2 2 1 * 0 7 6 5 4 3 2 1 0 7 * Figure 16. Fast Read Instruction - 29 - Publication Release Date: November 22, 2017 Revision I W25Q64JV Fast Read Dual Output (3Bh) The Fast Read Dual Output (3Bh) instruction is similar to the standard Fast Read (0Bh) instruction except that data is output on two pins; IO0 and IO1. This allows data to be transferred at twice the rate of standard SPI devices. The Fast Read Dual Output instruction is ideal for quickly downloading code from Flash to RAM upon power-up or for applications that cache code-segments to RAM for execution. Similar to the Fast Read instruction, the Fast Read Dual Output instruction can operate at the highest possible frequency of FR (see AC Electrical Characteristics). This is accomplished by adding eight "dummy" clocks after the 24-bit address as shown in Figure 18. The dummy clocks allow the device's internal circuits additional time for setting up the initial address. The input data during the dummy clocks is "don't care". However, the IO0 pin should be high-impedance prior to the falling edge of the first data out clock. /CS Mode 3 CLK 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 Mode 0 Instruction (3Bh) 24-Bit Address DI (IO0) 23 22 21 42 43 3 2 1 0 45 46 47 48 * High Impedance DO (IO1) * = MSB /CS 31 32 33 34 35 36 37 38 39 40 41 44 49 50 51 52 53 54 55 CLK IO0 switches from Input to Output Dummy Clocks DI (IO0) DO (IO1) 0 High Impedance 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7 * Data Out 1 * Data Out 2 * Data Out 3 * Data Out 4 Figure 18. Fast Read Dual Output Instruction - 30 - Publication Release Date: November 22, 2017 Revision I W25Q64JV Fast Read Quad Output (6Bh) The Fast Read Quad Output (6Bh) instruction is similar to the Fast Read Dual Output (3Bh) instruction except that data is output on four pins, IO0, IO1, IO2, and IO3. The Quad Enable (QE) bit in Status Register2 must be set to 1 before the device will accept the Fast Read Quad Output Instruction. The Fast Read Quad Output Instruction allows data to be transferred at four times the rate of standard SPI devices. The Fast Read Quad Output instruction can operate at the highest possible frequency of FR (see AC Electrical Characteristics). This is accomplished by adding eight "dummy" clocks after the 24-bit address as shown in Figure 20. The dummy clocks allow the device's internal circuits additional time for setting up the initial address. The input data during the dummy clocks is "don't care". However, the IO pins should be highimpedance prior to the falling edge of the first data out clock. /CS Mode 3 CLK 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 Mode 0 Instruction (6Bh) 24-Bit Address IO0 23 High Impedance IO1 22 21 42 43 3 2 1 45 46 47 0 * High Impedance IO2 High Impedance IO3 * = MSB /CS 31 32 33 34 35 36 37 38 39 40 41 44 CLK IO0 switches from Input to Output Dummy Clocks IO0 IO1 IO2 IO3 0 High Impedance High Impedance High Impedance 4 0 4 0 4 0 4 0 4 5 1 5 1 5 1 5 1 5 6 2 6 2 6 2 6 2 6 7 3 7 3 7 3 7 3 7 Byte 1 Byte 2 Byte 3 Byte 4 Figure 20. Fast Read Quad Output Instruction - 31 - Publication Release Date: November 22, 2017 Revision I W25Q64JV Fast Read Dual I/O (BBh) The Fast Read Dual I/O (BBh) instruction allows for improved random access while maintaining two IO pins, IO0 and IO1. It is similar to the Fast Read Dual Output (3Bh) instruction but with the capability to input the Address bits (A23-0) two bits per clock. This reduced instruction overhead may allow for code execution (XIP) directly from the Dual SPI in some applications. /CS Mode 3 CLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Mode 0 Instruction (BBh) A23-16 A15-8 A7-0 M7-0 DI (IO0) 22 20 18 16 14 12 10 8 6 4 2 0 6 4 2 0 DO (IO1) 23 21 19 17 15 13 11 9 7 5 3 1 7 5 3 1 * * = MSB * /CS 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 CLK IOs switch from Input to Output DI (IO0) 0 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6 DO (IO1) 1 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7 * Byte 1 * Byte 2 * Byte 3 * Byte 4 Figure 22. Fast Read Dual I/O Instruction (M5-4=Fxh) - 32 - Publication Release Date: November 22, 2017 Revision I W25Q64JV Fast Read Quad I/O (EBh) The Fast Read Quad I/O (EBh) instruction is similar to the Fast Read Dual I/O (BBh) instruction except that address and data bits are input and output through four pins IO 0, IO1, IO2 and IO3 and four Dummy clocks are required in SPI mode prior to the data output. The Quad I/O dramatically reduces instruction overhead allowing faster random access for code execution (XIP) directly from the Quad SPI. The Quad Enable bit (QE) of Status Register-2 must be set to enable the Fast Read Quad I/O Instruction. /CS Mode 3 CLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Mode 0 Instruction (EBh) A23-16 A15-8 A7-0 M7-0 Dummy IOs switch from Input to Output Dummy IO0 20 16 12 8 4 0 4 0 4 0 4 0 4 IO1 21 17 13 9 5 1 5 1 5 1 5 1 5 IO2 22 18 14 10 6 2 6 2 6 2 6 2 6 IO3 23 19 15 11 7 3 7 3 7 3 7 3 7 Byte 1 Byte 2 Byte 3 Figure 24a. Fast Read Quad I/O Instruction (M7-M0 should be set to Fxh) Fast Read Quad I/O with "8/16/32/64-Byte Wrap Around" in Standard SPI mode The Fast Read Quad I/O instruction can also be used to access a specific portion within a page by issuing a "Set Burst with Wrap" (77h) command prior to EBh. The "Set Burst with Wrap" (77h) command can either enable or disable the "Wrap Around" feature for the following EBh commands. When "Wrap Around" is enabled, the data being accessed can be limited to either an 8, 16, 32 or 64-byte section of a 256-byte page. The output data starts at the initial address specified in the instruction, once it reaches the ending boundary of the 8/16/32/64-byte section, the output will wrap around to the beginning boundary automatically until /CS is pulled high to terminate the command. The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then fill the cache afterwards within a fixed length (8/16/32/64-byte) of data without issuing multiple read commands. The "Set Burst with Wrap" instruction allows three "Wrap Bits", W6-4 to be set. The W4 bit is used to enable or disable the "Wrap Around" operation while W6-5 are used to specify the length of the wrap around section within a page. Refer to section 8.2.37 for detail descriptions. - 33 - Publication Release Date: November 22, 2017 Revision I W25Q64JV Set Burst with Wrap (77h) In Standard SPI mode, the Set Burst with Wrap (77h) instruction is used in conjunction with "Fast Read Quad I/O" instructions to access a fixed length of 8/16/32/64-byte section within a 256-byte page. Certain applications can benefit from this feature and improve the overall system code execution performance. Similar to a Quad I/O instruction, the Set Burst with Wrap instruction is initiated by driving the /CS pin low and then shifting the instruction code "77h" followed by 24 dummy bits and 8 "Wrap Bits", W7-0. The instruction sequence is shown in Figure 28. Wrap bit W7 and the lower nibble W3-0 are not used. W4 = 0 W6, W5 0 0 1 1 W4 =1 (DEFAULT) Wrap Around Wrap Length Wrap Around Wrap Length Yes Yes Yes Yes 8-byte 16-byte 32-byte 64-byte No No No No N/A N/A N/A N/A 0 1 0 1 Once W6-4 is set by a Set Burst with Wrap instruction, the following "Fast Read Quad I/O" instructions will use the W6-4 setting to access the 8/16/32/64-byte section within any page. To exit the "Wrap Around" function and return to normal read operation, another Set Burst with Wrap instruction should be issued to set W4 = 1. The default value of W4 upon power on or after a software/hardware reset is 1. /CS Mode 3 CLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Mode 0 Mode 3 Mode 0 don't care Instruction (77h) don't care don't care Wrap Bit IO0 X X X X X X w4 X IO1 X X X X X X w5 X IO2 X X X X X X w6 X IO3 X X X X X X X X Figure 28. Set Burst with Wrap Instruction - 34 - Publication Release Date: November 22, 2017 Revision I W25Q64JV Page Program (02h) The Page Program instruction allows from one byte to 256 bytes (a page) of data to be programmed at previously erased (FFh) memory locations. A Write Enable instruction must be executed before the device will accept the Page Program Instruction (Status Register bit WEL= 1). The instruction is initiated by driving the /CS pin low then shifting the instruction code "02h" followed by a 24-bit address (A23-A0) and at least one data byte, into the DI pin. The /CS pin must be held low for the entire length of the instruction while data is being sent to the device. The Page Program instruction sequence is shown in Figure 29. If an entire 256 byte page is to be programmed, the last address byte (the 8 least significant address bits) should be set to 0. If the last address byte is not zero, and the number of clocks exceeds the remaining page length, the addressing will wrap to the beginning of the page. In some cases, less than 256 bytes (a partial page) can be programmed without having any effect on other bytes within the same page. One condition to perform a partial page program is that the number of clocks cannot exceed the remaining page length. If more than 256 bytes are sent to the device the addressing will wrap to the beginning of the page and overwrite previously sent data. As with the write and erase instructions, the /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not done the Page Program instruction will not be executed. After /CS is driven high, the self-timed Page Program instruction will commence for a time duration of tpp (See AC Characteristics). While the Page Program cycle is in progress, the Read Status Register instruction may still be accessed for checking the status of the BUSY bit. The BUSY bit is a 1 during the Page Program cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions again. After the Page Program cycle has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Page Program instruction will not be executed if the addressed page is protected by the Block Protect (CMP, SEC, TB, BP2, BP1, and BP0) bits or the Individual Block/Sector Locks. /CS Mode 3 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 Mode 0 2 1 0 * 6 5 4 3 2 1 0 2079 3 2078 21 2077 22 2076 23 Data Byte 1 2075 24-Bit Address 2074 Instruction (02h) DI (IO0) 2073 CLK 7 * * = MSB 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 2072 /CS CLK Mode 0 Data Byte 2 DI (IO0) Mode 3 0 7 * 6 5 4 3 Data Byte 3 2 1 0 7 6 5 4 3 Data Byte 256 2 1 0 * 7 6 5 4 3 2 1 0 * Figure 29. Page Program Instruction - 35 - Publication Release Date: November 22, 2017 Revision I W25Q64JV Quad Input Page Program (32h) The Quad Page Program instruction allows up to 256 bytes of data to be programmed at previously erased (FFh) memory locations using four pins: IO 0, IO1, IO2, and IO3. The Quad Page Program can improve performance for PROM Programmer and applications that have slow clock speeds <5MHz. Systems with faster clock speed will not realize much benefit for the Quad Page Program instruction since the inherent page program time is much greater than the time it take to clock-in the data. To use Quad Page Program the Quad Enable (QE) bit in Status Register-2 must be set to 1. A Write Enable instruction must be executed before the device will accept the Quad Page Program instruction (Status Register-1, WEL=1). The instruction is initiated by driving the /CS pin low then shifting the instruction code "32h" followed by a 24-bit address (A23-A0) and at least one data byte, into the IO pins. The /CS pin must be held low for the entire length of the instruction while data is being sent to the device. All other functions of Quad Page Program are identical to standard Page Program. The Quad Page Program instruction sequence is shown in Figure 30. /CS Mode 3 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 Mode 0 22 21 3 2 1 543 23 542 IO0 539 24-Bit Address 538 Instruction (32h) 541 CLK 0 * IO1 IO2 IO3 * = MSB 33 34 35 36 37 540 32 537 31 536 /CS CLK Mode 0 Byte 253 Byte 254 Byte 255 Byte 256 Byte 1 Byte 2 Byte 3 4 0 4 0 4 0 4 0 4 0 4 0 4 0 IO1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 IO2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 IO3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 IO0 Mode 3 0 * * * * * * * Figure 30. Quad Input Page Program Instruction - 36 - Publication Release Date: November 22, 2017 Revision I W25Q64JV 8.3 Sector Erase (20h) The Sector Erase instruction sets all memory within a specified sector (4K-bytes) to the erased state of all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Sector Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the instruction code "20h" followed a 24-bit sector address (A23-A0). The Sector Erase instruction sequence is shown in Figure 31. The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not done the Sector Erase instruction will not be executed. After /CS is driven high, the self-timed Sector Erase instruction will commence for a time duration of tSE (See AC Characteristics). While the Sector Erase cycle is in progress, the Read Status Register instruction may still be accessed for checking the status of the BUSY bit. The BUSY bit is a 1 during the Sector Erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions again. After the Sector Erase cycle has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Sector Erase instruction will not be executed if the addressed page is protected by the Block Protect (CMP, SEC, TB, BP2, BP1, and BP0) bits or the Individual Block/Sector Locks. /CS Mode 3 CLK 0 1 2 3 4 5 6 7 8 29 30 31 Mode 3 Mode 0 Instruction (20h) DI (IO0) DO (IO1) 9 Mode 0 24-Bit Address 23 22 2 1 0 * High Impedance * = MSB Figure 31. Sector Erase Instruction - 37 - Publication Release Date: November 22, 2017 Revision I W25Q64JV 32KB Block Erase (52h) The Block Erase instruction sets all memory within a specified block (32K-bytes) to the erased state of all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Block Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the instruction code "52h" followed a 24-bit block address (A23-A0). The Block Erase instruction sequence is shown in Figure 32. The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not done the Block Erase instruction will not be executed. After /CS is driven high, the self-timed Block Erase instruction will commence for a time duration of tBE1 (See AC Characteristics). While the Block Erase cycle is in progress, the Read Status Register instruction may still be accessed for checking the status of the BUSY bit. The BUSY bit is a 1 during the Block Erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions again. After the Block Erase cycle has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Block Erase instruction will not be executed if the addressed page is protected by the Block Protect (CMP, SEC, TB, BP2, BP1, and BP0) bits or the Individual Block/Sector Locks. /CS Mode 3 CLK 0 1 2 3 4 5 6 7 8 29 30 31 Mode 3 Mode 0 Instruction (52h) DI (IO0) DO (IO1) 9 Mode 0 24-Bit Address 23 22 2 1 0 * High Impedance * = MSB Figure 32. 32KB Block Erase Instruction - 38 - Publication Release Date: November 22, 2017 Revision I W25Q64JV 64KB Block Erase (D8h) The Block Erase instruction sets all memory within a specified block (64K-bytes) to the erased state of all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Block Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the instruction code "D8h" followed a 24-bit block address (A23-A0). The Block Erase instruction sequence is shown in Figure 33. The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not done the Block Erase instruction will not be executed. After /CS is driven high, the self-timed Block Erase instruction will commence for a time duration of tBE (See AC Characteristics). While the Block Erase cycle is in progress, the Read Status Register instruction may still be accessed for checking the status of the BUSY bit. The BUSY bit is a 1 during the Block Erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions again. After the Block Erase cycle has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Block Erase instruction will not be executed if the addressed page is protected by the Block Protect (CMP, SEC, TB, BP2, BP1, and BP0) bits or the Individual Block/Sector Locks. /CS Mode 3 CLK 0 1 2 3 4 5 6 7 8 29 30 31 Mode 3 Mode 0 Instruction (D8h) DI (IO0) DO (IO1) 9 Mode 0 24-Bit Address 23 22 2 1 0 * High Impedance * = MSB Figure 33. 64KB Block Erase Instruction - 39 - Publication Release Date: November 22, 2017 Revision I W25Q64JV Chip Erase (C7h / 60h) The Chip Erase instruction sets all memory within the device to the erased state of all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Chip Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the instruction code "C7h" or "60h". The Chip Erase instruction sequence is shown in Figure 34. The /CS pin must be driven high after the eighth bit has been latched. If this is not done the Chip Erase instruction will not be executed. After /CS is driven high, the self-timed Chip Erase instruction will commence for a time duration of tCE (See AC Characteristics). While the Chip Erase cycle is in progress, the Read Status Register instruction may still be accessed to check the status of the BUSY bit. The BUSY bit is a 1 during the Chip Erase cycle and becomes a 0 when finished and the device is ready to accept other instructions again. After the Chip Erase cycle has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Chip Erase instruction will not be executed if any memory region is protected by the Block Protect (CMP, SEC, TB, BP2, BP1, and BP0) bits or the Individual Block/Sector Locks. /CS Mode 3 CLK 0 1 2 3 4 5 Mode 0 6 7 Mode 3 Mode 0 Instruction (C7h/60h) DI (IO0) DO (IO1) High Impedance Figure 34. Chip Erase Instruction - 40 - Publication Release Date: November 22, 2017 Revision I W25Q64JV Erase / Program Suspend (75h) The Erase/Program Suspend instruction "75h", allows the system to interrupt a Sector or Block Erase operation or a Page Program operation and then read from or program/erase data to, any other sectors or blocks. The Erase/Program Suspend instruction sequence is shown in Figure 35. The Write Status Register instruction (01h) and Erase instructions (20h, 52h, D8h, C7h, 60h, 44h) are not allowed during Erase Suspend. Erase Suspend is valid only during the Sector or Block erase operation. If written during the Chip Erase operation, the Erase Suspend instruction is ignored. The Write Status Register instruction (01h) and Program instructions (02h, 32h, 42h) are not allowed during Program Suspend. Program Suspend is valid only during the Page Program or Quad Page Program operation. The Erase/Program Suspend instruction "75h" will be accepted by the device only if the SUS bit in the Status Register equals to 0 and the BUSY bit equals to 1 while a Sector or Block Erase or a Page Program operation is on-going. If the SUS bit equals to 1 or the BUSY bit equals to 0, the Suspend instruction will be ignored by the device. A maximum of time of "t SUS" (See AC Characteristics) is required to suspend the erase or program operation. The BUSY bit in the Status Register will be cleared from 1 to 0 within "tSUS" and the SUS bit in the Status Register will be set from 0 to 1 immediately after Erase/Program Suspend. For a previously resumed Erase/Program operation, it is also required that the Suspend instruction "75h" is not issued earlier than a minimum of time of "tSUS" following the preceding Resume instruction "7Ah". Unexpected power off during the Erase/Program suspend state will reset the device and release the suspend state. SUS bit in the Status Register will also reset to 0. The data within the page, sector or block that was being suspended may become corrupted. It is recommended for the user to implement system design techniques against the accidental power interruption and preserve data integrity during erase/program suspend state. /CS tSUS Mode 3 CLK 0 1 2 3 4 5 6 7 Mode 3 Mode 0 Mode 0 Instruction (75h) DI (IO0) DO (IO1) High Impedance Accept instructions Figure 35. Erase/Program Suspend Instruction - 41 - Publication Release Date: November 22, 2017 Revision I W25Q64JV Erase / Program Resume (7Ah) The Erase/Program Resume instruction "7Ah" must be written to resume the Sector or Block Erase operation or the Page Program operation after an Erase/Program Suspend. The Resume instruction "7Ah" will be accepted by the device only if the SUS bit in the Status Register equals to 1 and the BUSY bit equals to 0. After issued the SUS bit will be cleared from 1 to 0 immediately, the BUSY bit will be set from 0 to 1 within 200ns and the Sector or Block will complete the erase operation or the page will complete the program operation. If the SUS bit equals to 0 or the BUSY bit equals to 1, the Resume instruction "7Ah" will be ignored by the device. The Erase/Program Resume instruction sequence is shown in Figure 36. Resume instruction is ignored if the previous Erase/Program Suspend operation was interrupted by unexpected power off. It is also required that a subsequent Erase/Program Suspend instruction not to be issued within a minimum of time of "tSUS" following a previous Resume instruction. /CS Mode 3 CLK 0 1 2 3 4 5 6 7 Mode 3 Mode 0 Mode 0 Instruction (7Ah) DI (IO0) Resume previously suspended Program or Erase Figure 36. Erase/Program Resume Instruction - 42 - Publication Release Date: November 22, 2017 Revision I W25Q64JV Power-down (B9h) Although the standby current during normal operation is relatively low, standby current can be further reduced with the Power-down instruction. The lower power consumption makes the Power-down instruction especially useful for battery powered applications (See ICC1 and ICC2 in AC Characteristics). The instruction is initiated by driving the /CS pin low and shifting the instruction code "B9h" as shown in Figure 37. The /CS pin must be driven high after the eighth bit has been latched. If this is not done the Power-down instruction will not be executed. After /CS is driven high, the power-down state will entered within the time duration of tDP (See AC Characteristics). While in the power-down state only the Release Power-down / Device ID (ABh) instruction, which restores the device to normal operation, will be recognized. All other instructions are ignored. This includes the Read Status Register instruction, which is always available during normal operation. Ignoring all but one instruction makes the Power Down state a useful condition for securing maximum write protection. The device always powers-up in the normal operation with the standby current of ICC1. /CS tDP Mode 3 CLK 0 1 2 3 4 5 6 7 Mode 3 Mode 0 Mode 0 Instruction (B9h) DI (IO0) Stand-by current Power-down current Figure 37. Deep Power-down Instruction - 43 - Publication Release Date: November 22, 2017 Revision I W25Q64JV Release Power-down / Device ID (ABh) The Release from Power-down / Device ID instruction is a multi-purpose instruction. It can be used to release the device from the power-down state, or obtain the devices electronic identification (ID) number. To release the device from the power-down state, the instruction is issued by driving the /CS pin low, shifting the instruction code "ABh" and driving /CS high as shown in Figure 38a. Release from power-down will take the time duration of tRES1 (See AC Characteristics) before the device will resume normal operation and other instructions are accepted. The /CS pin must remain high during the tRES1 time duration. When used only to obtain the Device ID while not in the power-down state, the instruction is initiated by driving the /CS pin low and shifting the instruction code "ABh" followed by 3-dummy bytes. The Device ID bits are then shifted out on the falling edge of CLK with most significant bit (MSB) first. The Device ID value for the W25Q64JV is listed in Manufacturer and Device Identification table. The Device ID can be read continuously. The instruction is completed by driving /CS high. When used to release the device from the power-down state and obtain the Device ID, the instruction is the same as previously described, and shown in Figure 38b, except that after /CS is driven high it must remain high for a time duration of tRES2 (See AC Characteristics). After this time duration the device will resume normal operation and other instructions will be accepted. If the Release from Power-down / Device ID instruction is issued while an Erase, Program or Write cycle is in process (when BUSY equals 1) the instruction is ignored and will not have any effects on the current cycle. /CS tRES1 Mode 3 CLK 0 1 2 3 4 5 6 7 Mode 3 Mode 0 Mode 0 Instruction (ABh) DI (IO0) Power-down current Stand-by current Figure 38a. Release Power-down Instruction /CS Mode 3 CLK 0 1 2 3 4 5 6 7 8 9 29 30 31 32 33 34 35 36 37 38 Mode 3 Mode 0 Mode 0 Instruction (ABh) DI (IO0) tRES2 3 Dummy Bytes 23 22 2 1 0 * Device ID High Impedance DO (IO1) 7 6 5 4 3 2 1 0 * * = MSB Power-down current Stand-by current Figure 38c. Release Power-down / Device ID Instruction - 44 - Publication Release Date: November 22, 2017 Revision I W25Q64JV Read Manufacturer / Device ID (90h) The Read Manufacturer/Device ID instruction is an alternative to the Release from Power-down / Device ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device ID. The Read Manufacturer/Device ID instruction is very similar to the Release from Power-down / Device ID instruction. The instruction is initiated by driving the /CS pin low and shifting the instruction code "90h" followed by a 24-bit address (A23-A0) of 000000h. After which, the Manufacturer ID for Winbond (EFh) and the Device ID are shifted out on the falling edge of CLK with most significant bit (MSB) first as shown in Figure 39. The Device ID values for the W25Q64JV are listed in Manufacturer and Device Identification table. The instruction is completed by driving /CS high. /CS Mode 3 CLK 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 Mode 0 Instruction (90h) Address (000000h) DI (IO0) 23 22 21 42 43 3 2 45 46 1 0 * High Impedance DO (IO1) * = MSB /CS 31 32 33 34 35 36 37 38 39 40 41 44 Mode 3 CLK DI (IO0) Mode 0 0 DO (IO1) 7 * Manufacturer ID (EFh) 6 5 4 3 2 1 0 Device ID Figure 39. Read Manufacturer / Device ID Instruction - 45 - Publication Release Date: November 22, 2017 Revision I W25Q64JV Read Manufacturer / Device ID Dual I/O (92h) The Read Manufacturer / Device ID Dual I/O instruction is an alternative to the Read Manufacturer / Device ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device ID at 2x speed. The Read Manufacturer / Device ID Dual I/O instruction is similar to the Fast Read Dual I/O instruction. The instruction is initiated by driving the /CS pin low and shifting the instruction code "92h" followed by a 24-bit address (A23-A0) of 000000h, but with the capability to input the Address bits two bits per clock. After which, the Manufacturer ID for Winbond (EFh) and the Device ID are shifted out 2 bits per clock on the falling edge of CLK with most significant bits (MSB) first as shown in Figure 40. The Device ID values for the W25Q64JV are listed in Manufacturer and Device Identification table. The Manufacturer and Device IDs can be read continuously, alternating from one to the other. The instruction is completed by driving /CS high. /CS Mode 3 CLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Mode 0 Instruction (92h) A23-16 DI (IO0) High Impedance DO (IO1) * = MSB A15-8 A7-0 (00h) M7-0 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 * * * * /CS 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 Mode 3 CLK Mode 0 IOs switch from Input to Output DI (IO0) 0 6 4 2 0 6 4 2 0 6 DO (IO1) 1 7 5 3 1 7 5 3 1 * MFR ID * Device ID 4 2 0 6 7 5 3 1 7 * MFR ID (repeat) * 4 2 0 5 3 1 Device ID (repeat) Figure 40. Read Manufacturer / Device ID Dual I/O Instruction Note: The "Continuous Read Mode" bits M(7-0) must be set to Fxh to be compatible with Fast Read Dual I/O instruction. - 46 - Publication Release Date: November 22, 2017 Revision I W25Q64JV Read Manufacturer / Device ID Quad I/O (94h) The Read Manufacturer / Device ID Quad I/O instruction is an alternative to the Read Manufacturer / Device ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device ID at 4x speed. The Read Manufacturer / Device ID Quad I/O instruction is similar to the Fast Read Quad I/O instruction. The instruction is initiated by driving the /CS pin low and shifting the instruction code "94h" followed by a four clock dummy cycles and then a 24-bit address (A23-A0) of 000000h, but with the capability to input the Address bits four bits per clock. After which, the Manufacturer ID for Winbond (EFh) and the Device ID are shifted out four bits per clock on the falling edge of CLK with most significant bit (MSB) first as shown in Figure 41. The Manufacturer and Device IDs can be read continuously, alternating from one to the other. The instruction is completed by driving /CS high. /CS Mode 3 CLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Mode 0 Instruction (94h) IO0 High Impedance IO1 High Impedance IO2 High Impedance IO3 A7-0 (00h) M7-0 Dummy IOs switch from Input to Output A23-16 A15-8 Dummy 4 0 4 0 4 0 4 0 4 0 4 0 5 1 5 1 5 1 5 1 5 1 5 1 6 2 6 2 6 2 6 2 6 2 6 2 7 3 7 3 7 3 7 3 7 3 7 3 MFR ID Device ID /CS 23 24 25 26 27 28 29 30 Mode 3 CLK Mode 0 IO0 0 4 0 4 0 4 0 4 0 IO1 1 5 1 5 1 5 1 5 1 IO2 2 6 2 6 2 6 2 6 2 IO3 3 7 3 7 3 7 3 7 3 MFR ID (repeat) Device ID (repeat) MFR ID (repeat) Device ID (repeat) Figure 41. Read Manufacturer / Device ID Quad I/O Instruction Note: The "Continuous Read Mode" bits M(7-0) must be set to Fxh to be compatible with Fast Read Quad I/O instruction. - 47 - Publication Release Date: November 22, 2017 Revision I W25Q64JV Read Unique ID Number (4Bh) The Read Unique ID Number instruction accesses a factory-set read-only 64-bit number that is unique to each W25Q64JV device. The ID number can be used in conjunction with user software methods to help prevent copying or cloning of a system. The Read Unique ID instruction is initiated by driving the /CS pin low and shifting the instruction code "4Bh" followed by a four bytes of dummy clocks. After which, the 64-bit ID is shifted out on the falling edge of CLK as shown in Figure 42. /CS Mode 3 CLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Mode 0 Instruction (4Bh) Dummy Byte 1 Dummy Byte 2 DI (IO0) High Impedance DO (IO1) 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 102 24 101 23 100 /CS Mode 3 CLK Mode 0 Dummy Byte 3 Dummy Byte 4 DI (IO0) DO (IO1) High Impedance * = MSB 63 62 61 2 1 * 64-bit Unique Serial Number 0 Figure 42. Read Unique ID Number Instruction - 48 - Publication Release Date: November 22, 2017 Revision I W25Q64JV Read JEDEC ID (9Fh) For compatibility reasons, the W25Q64JV provides several instructions to electronically determine the identity of the device. The Read JEDEC ID instruction is compatible with the JEDEC standard for SPI compatible serial memories that was adopted in 2003. The instruction is initiated by driving the /CS pin low and shifting the instruction code "9Fh". The JEDEC assigned Manufacturer ID byte for Winbond (EFh) and two Device ID bytes, Memory Type (ID15-ID8) and Capacity (ID7-ID0) are then shifted out on the falling edge of CLK with most significant bit (MSB) first as shown in Figure 43. For memory type and capacity values refer to Manufacturer and Device Identification table. /CS Mode 3 CLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Mode 0 Instruction (9Fh) DI (IO0) Manufacturer ID (EFh) High Impedance DO (IO1) * = MSB /CS 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Mode 3 CLK Mode 0 DI (IO0) Memory Type ID15-8 DO (IO1) 7 6 5 4 3 2 Capacity ID7-0 1 0 * 7 6 5 4 3 2 1 0 * Figure 43. Read JEDEC ID Instruction - 49 - Publication Release Date: November 22, 2017 Revision I W25Q64JV Read SFDP Register (5Ah) The W25Q64JV features a 256-Byte Serial Flash Discoverable Parameter (SFDP) register that contains information about device configurations, available instructions and other features. The SFDP parameters are stored in one or more Parameter Identification (PID) tables. Currently only one PID table is specified, but more may be added in the future. The Read SFDP Register instruction is compatible with the SFDP standard initially established in 2010 for PC and other applications, as well as the JEDEC standard JESD216-serials that is published in 2011. Most Winbond SpiFlash Memories shipped after June 2011 (date code 1124 and beyond) support the SFDP feature as specified in the applicable datasheet. The Read SFDP instruction is initiated by driving the /CS pin low and shifting the instruction code "5Ah" followed by a 24-bit address (A23-A0)(1) into the DI pin. Eight "dummy" clocks are also required before the SFDP register contents are shifted out on the falling edge of the 40 th CLK with most significant bit (MSB) first as shown in Figure 44. For SFDP register values and descriptions, please refer to the Winbond Application Note for SFDP Definition Table. Note 1: A23-A8 = 0; A7-A0 are used to define the starting byte address for the 256-Byte SFDP Register. /CS Mode 3 CLK 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 Mode 0 Instruction (5Ah) 24-Bit Address DI (IO0) 23 22 21 42 43 3 2 1 0 45 46 47 48 * High Impedance DO (IO1) /CS 31 32 33 34 35 36 37 38 39 40 41 44 49 50 51 52 53 54 55 CLK Dummy Byte DI (IO0) 0 7 6 5 4 3 2 1 0 Data Out 1 DO (IO1) High Impedance * = MSB 7 6 5 4 * 3 Data Out 2 2 1 0 7 6 5 4 3 2 1 0 7 * Figure 44. Read SFDP Register Instruction Sequence Diagram - 50 - Publication Release Date: November 22, 2017 Revision I W25Q64JV Erase Security Registers (44h) The W25Q64JV offers three 256-byte Security Registers which can be erased and programmed individually. These registers may be used by the system manufacturers to store security and other important information separately from the main memory array. The Erase Security Register instruction is similar to the Sector Erase instruction. A Write Enable instruction must be executed before the device will accept the Erase Security Register Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the instruction code "44h" followed by a 24-bit address (A23-A0) to erase one of the three security registers. ADDRESS A23-16 A15-12 A11-8 A7-0 Security Register #1 00h 0001 0000 Don't Care Security Register #2 00h 0010 0000 Don't Care Security Register #3 00h 0011 0000 Don't Care The Erase Security Register instruction sequence is shown in Figure 45. The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not done the instruction will not be executed. After /CS is driven high, the self-timed Erase Security Register operation will commence for a time duration of tSE (See AC Characteristics). While the Erase Security Register cycle is in progress, the Read Status Register instruction may still be accessed for checking the status of the BUSY bit. The BUSY bit is a 1 during the erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions again. After the Erase Security Register cycle has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Security Register Lock Bits (LB3-1) in the Status Register-2 can be used to OTP protect the security registers. Once a lock bit is set to 1, the corresponding security register will be permanently locked, Erase Security Register instruction to that register will be ignored (Refer to section 7.1.8 for detail descriptions). /CS Mode 3 CLK 0 1 2 3 4 5 6 7 8 29 30 31 Mode 3 Mode 0 Instruction (44h) DI (IO0) DO (IO1) 9 Mode 0 24-Bit Address 23 22 2 1 0 * High Impedance * = MSB Figure 45. Erase Security Registers Instruction - 51 - Publication Release Date: November 22, 2017 Revision I W25Q64JV Program Security Registers (42h) The Program Security Register instruction is similar to the Page Program instruction. It allows from one byte to 256 bytes of security register data to be programmed at previously erased (FFh) memory locations. A Write Enable instruction must be executed before the device will accept the Program Security Register Instruction (Status Register bit WEL= 1). The instruction is initiated by driving the /CS pin low then shifting the instruction code "42h" followed by a 24-bit address (A23-A0) and at least one data byte, into the DI pin. The /CS pin must be held low for the entire length of the instruction while data is being sent to the device. ADDRESS A23-16 A15-12 A11-8 A7-0 Security Register #1 00h 0001 0000 Byte Address Security Register #2 00h 0010 0000 Byte Address Security Register #3 00h 0011 0000 Byte Address The Program Security Register instruction sequence is shown in Figure 46. The Security Register Lock Bits (LB3-1) in the Status Register-2 can be used to OTP protect the security registers. Once a lock bit is set to 1, the corresponding security register will be permanently locked, Program Security Register instruction to that register will be ignored (See 7.1.8, 8.2.25 for detail descriptions). /CS Mode 3 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 Mode 0 1 * 0 6 5 4 3 2 1 0 2079 Data Byte 1 2 2078 3 2077 21 2076 22 2075 24-Bit Address 23 2074 Instruction (42h) DI (IO0) 2073 CLK 7 * * = MSB 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 2072 /CS CLK Mode 0 Data Byte 2 DI (IO0) Mode 3 0 7 * 6 5 4 3 Data Byte 3 2 1 0 7 6 5 4 3 * Data Byte 256 2 1 0 7 6 5 4 3 2 1 0 * Figure 46. Program Security Registers Instruction - 52 - Publication Release Date: November 22, 2017 Revision I W25Q64JV Read Security Registers (48h) The Read Security Register instruction is similar to the Fast Read instruction and allows one or more data bytes to be sequentially read from one of the four security registers. The instruction is initiated by driving the /CS pin low and then shifting the instruction code "48h" followed by a 24-bit address (A23-A0) and eight "dummy" clocks into the DI pin. The code and address bits are latched on the rising edge of the CLK pin. After the address is received, the data byte of the addressed memory location will be shifted out on the DO pin at the falling edge of CLK with most significant bit (MSB) first. The byte address is automatically incremented to the next byte address after each byte of data is shifted out. Once the byte address reaches the last byte of the register (byte address FFh), it will reset to address 00h, the first byte of the register, and continue to increment. The instruction is completed by driving /CS high. The Read Security Register instruction sequence is shown in Figure 47. If a Read Security Register instruction is issued while an Erase, Program or Write cycle is in process (BUSY=1) the instruction is ignored and will not have any effects on the current cycle. The Read Security Register instruction allows clock rates from D.C. to a maximum of F R (see AC Electrical Characteristics). ADDRESS A23-16 A15-12 A11-8 A7-0 Security Register #1 00h 0001 0000 Byte Address Security Register #2 00h 0010 0000 Byte Address Security Register #3 00h 0011 0000 Byte Address /CS Mode 3 CLK 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 Mode 0 Instruction (48h) 24-Bit Address DI (IO0) 23 22 21 42 43 3 2 1 0 45 46 47 48 * High Impedance DO (IO1) * = MSB /CS 31 32 33 34 35 36 37 38 39 40 41 44 49 50 51 52 53 54 55 CLK Dummy Byte DI (IO0) 0 7 6 5 4 3 2 1 0 Data Out 1 DO (IO1) High Impedance 7 6 5 4 * 3 Data Out 2 2 1 0 7 6 5 4 3 2 1 0 7 * Figure 47. Read Security Registers Instruction - 53 - Publication Release Date: November 22, 2017 Revision I W25Q64JV Individual Block/Sector Lock (36h) The Individual Block/Sector Lock provides an alternative way to protect the memory array from adverse Erase/Program. In order to use the Individual Block/Sector Locks, the WPS bit in Status Register-3 must be set to 1. If WPS=0, the write protection will be determined by the combination of CMP, SEC, TB, BP[2:0] bits in the Status Registers. The Individual Block/Sector Lock bits are volatile bits. The default values after device power up or after a Reset are 1, so the entire memory array is being protected. To lock a specific block or sector as illustrated in Figure 4d, an Individual Block/Sector Lock command must be issued by driving /CS low, shifting the instruction code "36h" into the Data Input (DI) pin on the rising edge of CLK, followed by a 24-bit address and then driving /CS high. A Write Enable instruction must be executed before the device will accept the Individual Block/Sector Lock Instruction (Status Register bit WEL= 1). /CS Mode 3 CLK 0 1 2 3 4 5 6 7 8 9 29 30 31 Mode 0 Mode 3 Mode 0 Instruction (36h) DI (IO0) 24-Bit Address 23 22 2 1 0 * DO (IO1) High Impedance * = MSB Figure 53. Individual Block/Sector Lock Instruction - 54 - Publication Release Date: November 22, 2017 Revision I W25Q64JV Individual Block/Sector Unlock (39h) The Individual Block/Sector Lock provides an alternative way to protect the memory array from adverse Erase/Program. In order to use the Individual Block/Sector Locks, the WPS bit in Status Register-3 must be set to 1. If WPS=0, the write protection will be determined by the combination of CMP, SEC, TB, BP[2:0] bits in the Status Registers. The Individual Block/Sector Lock bits are volatile bits. The default values after device power up or after a Reset are 1, so the entire memory array is being protected. To unlock a specific block or sector as illustrated in Figure 4d, an Individual Block/Sector Unlock command must be issued by driving /CS low, shifting the instruction code "39h" into the Data Input (DI) pin on the rising edge of CLK, followed by a 24-bit address and then driving /CS high. A Write Enable instruction must be executed before the device will accept the Individual Block/Sector Unlock Instruction (Status Register bit WEL= 1). /CS Mode 3 CLK 0 1 2 3 4 5 6 7 8 9 29 30 31 Mode 0 Mode 3 Mode 0 Instruction (39h) DI (IO0) 24-Bit Address 23 22 2 1 0 * DO (IO1) High Impedance * = MSB Figure 54. Individual Block Unlock Instruction - 55 - Publication Release Date: November 22, 2017 Revision I W25Q64JV Read Block/Sector Lock (3Dh) The Individual Block/Sector Lock provides an alternative way to protect the memory array from adverse Erase/Program. In order to use the Individual Block/Sector Locks, the WPS bit in Status Register-3 must be set to 1. If WPS=0, the write protection will be determined by the combination of CMP, SEC, TB, BP[2:0] bits in the Status Registers. The Individual Block/Sector Lock bits are volatile bits. The default values after device power up or after a Reset are 1, so the entire memory array is being protected. To read out the lock bit value of a specific block or sector as illustrated in Figure 4d, a Read Block/Sector Lock command must be issued by driving /CS low, shifting the instruction code "3Dh" into the Data Input (DI) pin on the rising edge of CLK, followed by a 24-bit address. The Block/Sector Lock bit value will be shifted out on the DO pin at the falling edge of CLK with most significant bit (MSB) first as shown in Figure 55. If the least significant bit (LSB) is 1, the corresponding block/sector is locked; if LSB=0, the corresponding block/sector is unlocked, Erase/Program operation can be performed. /CS Mode 3 CLK 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 Mode 0 Mode 0 Instruction (3Dh) 24-Bit Address DI (IO0) 23 22 21 3 2 1 0 * Lock Value Out High Impedance DO (IO1) * Mode 3 X X X X X X X 0 * = MSB Figure 55. Read Block Lock Instruction - 56 - Publication Release Date: November 22, 2017 Revision I W25Q64JV Global Block/Sector Lock (7Eh) All Block/Sector Lock bits can be set to 1 by the Global Block/Sector Lock instruction. The command must be issued by driving /CS low, shifting the instruction code "7Eh" into the Data Input (DI) pin on the rising edge of CLK, and then driving /CS high. A Write Enable instruction must be executed before the device will accept the Global Block/Sector Lock Instruction (Status Register bit WEL= 1). /CS Mode 3 CLK 0 1 2 3 4 5 6 7 Mode 3 Mode 0 Mode 0 Instruction (7Eh) DI (IO0) High Impedance DO (IO1) Figure 56. Global Block Lock Instruction for SPI Mode Global Block/Sector Unlock (98h) All Block/Sector Lock bits can be set to 0 by the Global Block/Sector Unlock instruction. The command must be issued by driving /CS low, shifting the instruction code "98h" into the Data Input (DI) pin on the rising edge of CLK, and then driving /CS high. A Write Enable instruction must be executed before the device will accept the Global Block/Sector Unlock Instruction (Status Register bit WEL= 1). /CS Mode 3 CLK 0 1 2 3 4 5 6 7 Mode 0 Mode 3 Mode 0 Instruction (98h) DI (IO0) DO (IO1) High Impedance Figure 57. Global Block Unlock Instruction for SPI Mode - 57 - Publication Release Date: November 22, 2017 Revision I W25Q64JV Enable Reset (66h) and Reset Device (99h) Because of the small package and the limitation on the number of pins, the W25Q64JV provide a software Reset instruction instead of a dedicated RESET pin. Once the Reset instruction is accepted, any on-going internal operations will be terminated and the device will return to its default power-on state and lose all the current volatile settings, such as Volatile Status Register bits, Write Enable Latch (WEL) status, Program/Erase Suspend status, Read parameter setting (P7-P0), and Wrap Bit setting (W6-W4). "Enable Reset (66h)" and "Reset (99h)" instructions can be issued in SPI mode. To avoid accidental reset, both instructions must be issued in sequence. Any other commands other than "Reset (99h)" after the "Enable Reset (66h)" command will disable the "Reset Enable" state. A new sequence of "Enable Reset (66h)" and "Reset (99h)" is needed to reset the device. Once the Reset command is accepted by the device, the device will take approximately tRST=30us to reset. During this period, no command will be accepted. Data corruption may happen if there is an on-going or suspended internal Erase or Program operation when Reset command sequence is accepted by the device. It is recommended to check the BUSY bit and the SUS bit in Status Register before issuing the Reset command sequence. /CS Mode 3 CLK 0 1 2 3 4 Mode 0 5 6 7 Mode 3 0 1 2 3 4 Mode 0 Instruction (66h) 5 6 7 Mode 3 Mode 0 Instruction (99h) DI (IO0) DO (IO1) High Impedance Figure 58. Enable Reset and Reset Instruction Sequence - 58 - Publication Release Date: November 22, 2017 Revision I W25Q64JV 9. ELECTRICAL CHARACTERISTICS 9.1 Absolute Maximum Ratings (1) PARAMETERS SYMBOL Supply Voltage VCC Voltage Applied to Any Pin VIO Transient Voltage on any Pin VIOT Storage Temperature TSTG Lead Temperature CONDITIONS RANGE -0.6 to 4.6 V Relative to Ground -0.6 to VCC+0.4 V <20nS Transient Relative to Ground -2.0V to VCC+2.0V V -65 to +150 C (2) C TLEAD Electrostatic Discharge Voltage VESD UNIT See Note Human Body Model(3) -2000 to +2000 V Notes: 1. This device has been designed and tested for the specified operation ranges. Proper operation outside of these levels is not guaranteed. Exposure to absolute maximum ratings may affect device reliability. Exposure beyond absolute maximum ratings may cause permanent damage. 2. Compliant with JEDEC Standard J-STD-20C for small body Sn-Pb or Pb-free (Green) assembly and the European directive on restrictions on hazardous substances (RoHS) 2002/95/EU. 3. JEDEC Std JESD22-A114A (C1=100pF, R1=1500 ohms, R2=500 ohms). 9.2 Operating Ranges PARAMETER Supply Voltage(1) Ambient Temperature, Operating SYMBOL VCC TA SPEC CONDITIONS MIN MAX UNIT FR = 133MHz, fR = 50MHz 3.0 3.6 V FR = 104MHz, fR = 50MHz 2.7 3.0 V -40 +85 C Industrial Note: 1. VCC voltage during Read can operate across the min and max range but should not exceed 10% of the programming (erase/write) voltage. - 59 - Publication Release Date: November 22, 2017 Revision I W25Q64JV 9.3 Power-Up Power-Down Timing and Requirements SPEC PARAMETER SYMBOL VCC (min) to /CS Low tVSL(1) 20 s Time Delay Before Write Instruction tPUW(1) 5 ms Write Inhibit Threshold Voltage VWI MIN 1.0 (1) MAX 2.0 UNIT V Note: 1. These parameters are characterized only. VCC VCC (max) Program, Erase and Write Instructions are ignored /CS must track VCC VCC (min) Reset State tVSL Read Instructions Allowed Device is fully Accessible VWI tPUW Time Figure 58a. Power-up Timing and Voltage Levels /CS must track VCC during VCC Ramp Up/Down VCC /CS Time Figure 58b. Power-up, Power-Down Requirement - 60 - Publication Release Date: November 22, 2017 Revision I W25Q64JV 9.4 DC Electrical CharacteristicsSPEC PARAMETER SYMBOL CONDITIONS Input Capacitance CIN(1) VIN = 0V(1) 6 pF Output Capacitance Cout(1) VOUT = 0V(1) 8 pF Input Leakage ILI 2 A I/O Leakage ILO 2 A Standby Current ICC1 /CS = VCC, VIN = GND or VCC 10 50 A Power-down Current ICC2 /CS = VCC, VIN = GND or VCC 1 15 A Current Read Data / Dual /Quad 50MHz(2) ICC3 C = 0.1 VCC / 0.9 VCC DO = Open 15 mA Current Read Data / Dual /Quad 80MHz(2) ICC3 C = 0.1 VCC / 0.9 VCC DO = Open 18 mA Current Read Data / Dual Output Read/Quad Output Read 104MHz(2) ICC3 C = 0.1 VCC / 0.9 VCC DO = Open 20 mA Current Write Status Register ICC4 /CS = VCC 20 25 mA Current Page Program ICC5 /CS = VCC 20 25 mA Current Sector/Block Erase ICC6 /CS = VCC 20 25 mA Current Chip Erase ICC7 /CS = VCC 20 25 mA Input Low Voltage VIL -0.5 VCC x 0.3 V Input High Voltage VIH VCC x 0.7 VCC + 0.4 V Output Low Voltage VOL IOL = 100 A 0.2 V Output High Voltage VOH IOH = -100 A MIN TYP MAX VCC - 0.2 UNIT V Notes: 1. Tested on sample basis and specified through design and characterization data. TA = 25 C, VCC = 3.0V. 2. Checker Board Pattern. - 61 - Publication Release Date: November 22, 2017 Revision I W25Q64JV 9.5 AC Measurement Conditions PARAMETER SPEC SYMBOL Load Capacitance Input Rise and Fall Times Input Pulse Voltages Input Timing Reference Voltages Output Timing Reference Voltages MIN MAX UNIT CL 30 pF TR, TF 5 ns VIN 0.1 VCC to 0.9 VCC V IN 0.3 VCC to 0.7 VCC V OUT 0.5 VCC to 0.5 VCC V Note: 1. Output Hi-Z is defined as the point where data out is no longer driven. Input and Output Timing Reference Levels Input Levels 0.9 VCC 0.5 VCC 0.1 VCC Figure 59. AC Measurement I/O Waveform - 62 - Publication Release Date: November 22, 2017 Revision I W25Q64JV 9.6 AC Electrical Characteristics(6) SPEC DESCRIPTION SYMBOL ALT UNIT MIN TYP MAX Clock frequency except for Read Data (03h) instructions (3.0V-3.6V) FR fC1 D.C. 133 MHz Clock frequency except for Read Data (03h) instructions( 2.7V-3.0V) FR fC2 D.C. 104 MHz Clock frequency for Read Data instruction (03h) fR D.C. 50 MHz Clock High, Low Time for all instructions except for Read Data (03h) tCLH, tCLL(1) 45% PC ns Clock High, Low Time for Read Data (03h) instruction tCRLH, tCRLL(1) 45% PC ns Clock Rise Time peak to peak tCLCH(2) 0.1 V/ns Clock Fall Time peak to peak tCHCL(2) 0.1 V/ns 5 ns 5 ns /CS Active Setup Time relative to CLK tSLCH /CS Not Active Hold Time relative to CLK tCHSL Data In Setup Time tDVCH tDSU 2 ns Data In Hold Time tCHDX tDH 3 ns /CS Active Hold Time relative to CLK tCHSH 3 ns /CS Not Active Setup Time relative to CLK tSHCH 3 ns /CS Deselect Time (for Read) tSHSL1 tCSH 10 ns /CS Deselect Time (for Erase or Program or Write) tSHSL2 tCSH 50 ns tSHQZ(2) tDIS 7 ns Clock Low to Output Valid 2.7V-3.6V tCLQV tV 6 ns Output Hold Time tCLQX tHO Output Disable Time tCSS 1.5 ns Continued - next page AC Electrical Characteristics (cont'd) - 63 - Publication Release Date: November 22, 2017 Revision I W25Q64JV SPEC DESCRIPTION SYMBOL ALT UNIT MIN TYP MAX Write Protect Setup Time Before /CS Low tWHSL(3) 20 ns Write Protect Hold Time After /CS High tSHWL(3) 100 ns tDP(2) 3 s /CS High to Standby Mode without ID Read tRES1(2) 3 s /CS High to Standby Mode with ID Read tRES2(2) 1.8 s /CS High to next Instruction after Suspend tSUS(2) 20 s /CS High to next Instruction after Reset tRST(2) 30 s /CS High to Power-down Mode tRESET(2) /RESET pin Low period to reset the device 1(5) s Write Status Register Time tW 10 15 ms Page Program Time tPP 0.8 3 ms Sector Erase Time (4KB) tSE 45 400 ms Block Erase Time (32KB) tBE1 120 1,600 ms Block Erase Time (64KB) tBE2 150 2,000 ms Chip Erase Time tCE 20 100 s Notes: 1. Clock high or Clock low must be more than or equal to 45%Pc. Pc=1/fC(MAX) 2. Value guaranteed by design and/or characterization, not 100% tested in production. 3. Only applicable as a constraint for a Write Status Register instruction when SRP=1. 4. It's possible to reset the device with shorter tRESET (as short as a few hundred ns), a 1us minimum is recommended to ensure reliable operation. 5. Tested on sample basis and specified through design and characterization data. T A = 25 C, VCC = 3.0V, 25% driver strength. 6. 4-bytes address alignment for Quad Read, start address from [A1,A0]=(0,0). - 64 - Publication Release Date: November 22, 2017 Revision I W25Q64JV 9.7 Serial Output Timing /CS tCLH CLK IO output tCLQX tCLQV tCLQX tCLQV tCLL MSB OUT tSHQZ LSB OUT 9.8 Serial Input Timing /CS tSHSL tCHSL tSLCH tCHSH tSHCH CLK tDVCH IO input 9.9 tCHDX tCLCH MSB IN tCHCL LSB IN /WP Timing /CS tWHSL tSHWL /WP CLK IO input Write Status Register is allowed - 65 - Write Status Register is not allowed Publication Release Date: November 22, 2017 Revision I W25Q64JV 10. PACKAGE SPECIFICATIONS 10.1 8-Pin SOIC 208-mil (Package Code SS) Symbol Millimeters Inches Min Nom Max Min Nom Max A A1 A2 b C D D1 E E1 e H L y 1.75 0.05 1.70 0.35 0.19 5.18 5.13 5.18 5.13 2.16 0.25 1.91 0.48 0.25 5.38 5.33 5.38 5.33 0.069 0.002 0.067 0.014 0.007 0.204 0.202 0.204 0.202 8.10 0.80 0.303 0.020 0.077 0.006 0.071 0.017 0.008 0.208 0.206 0.208 0.206 0.050 BSC 0.311 0.026 0.085 0.010 0.075 0.019 0.010 0.212 0.210 0.212 0.210 7.70 0.50 1.95 0.15 1.80 0.42 0.20 5.28 5.23 5.28 5.23 1.27 BSC 7.90 0.65 --- --- 0.10 --- --- 0.004 0 --- 8 0 --- 8 - 66 - 0.319 0.031 Publication Release Date: November 22, 2017 Revision I W25Q64JV 10.2 8-Pad WSON 6x5-mm (Package Code ZP) Symbol Millimeters Inches Min Nom Max Min Nom Max A 0.70 0.75 0.80 0.028 0.030 0.031 A1 0.00 0.02 0.05 0.000 0.001 0.002 b 0.35 0.40 0.48 0.014 0.016 0.019 C --- 0.20 REF --- --- 0.008 REF --- D 5.90 6.00 6.10 0.232 0.236 0.240 D2 3.35 3.40 3.45 0.132 0.134 0.136 E 4.90 5.00 5.10 0.193 0.197 0.201 E2 4.25 4.30 4.35 0.167 0.169 0.171 e 1.27 BSC 0.050 BSC L 0.55 0.60 0.65 0.022 0.024 0.026 y 0.00 --- 0.075 0.000 --- 0.003 Note: The metal pad area on the bottom center of the package is not connected to any internal electrical signals. It can be left floating or connected to the device ground (GND pin). Avoid placement of exposed PCB vias under the pad. - 67 - Publication Release Date: November 22, 2017 Revision I W25Q64JV 10.3 8-Pad WSON 8x6mm (Package Code ZE) MILLIMETERS Min Nom Max A 0.70 0.75 0.80 A1 0.00 0.02 SYMBOL Min INCHES Nom Max 0.028 0.030 0.031 0.05 0.000 0.001 0.002 0.019 b 0.35 0.40 0.48 0.014 0.016 C --- 0.20 Ref. --- --- 0.008 Ref. --- D 7.90 8.00 8.10 0.311 0.315 0.319 D2 3.35 3.40 3.45 0.132 0.134 0.136 E 5.90 6.00 6.10 0.232 0.236 0.240 E2 4.25 4.30 4.35 0.167 0.169 0.171 e 1.27 BSC 0.050 BSC L 0.45 0.50 0.55 0.018 0.020 0.022 y 0.00 --- 0.05 0.000 --- 0.002 Note: The metal pad area on the bottom center of the package is not connected to any internal electrical signals. It can be left floating or connected to the device ground (GND pin). Avoid placement of exposed PCB vias under the pad. - 68 - Publication Release Date: November 22, 2017 Revision I W25Q64JV 10.4 8-Pad XSON 4x4x0.45-mm (Package Code XG) - 69 - Publication Release Date: November 22, 2017 Revision I W25Q64JV 10.5 16-Pin SOIC 300-mil (Package Code SF) Min Millimeters Nom Max Min Inches Nom A 2.36 2.49 2.64 0.093 0.098 0.104 A1 0.10 --- 0.30 0.004 --- 0.012 A2 --- 2.31 --- --- 0.091 --- Symbol Max b 0.33 0.41 0.51 0.013 0.016 0.020 C 0.18 0.23 0.28 0.007 0.009 0.011 D 10.08 10.31 10.49 0.397 0.406 0.413 E 10.01 10.31 10.64 0.394 0.406 0.419 E1 7.39 7.49 7.59 0.291 0.295 0.299 e 1.27 BSC 0.050 BSC L 0.38 0.81 1.27 0.015 0.032 0.050 y --- --- 0.076 --- --- 0.003 0 --- 8 0 --- 8 - 70 - Publication Release Date: November 22, 2017 Revision I W25Q64JV 10.7 24-Ball TFBGA 8x6-mm (Package Code TB, 5x5 Ball Array) Note: Ball land: 0.45mm. Ball Opening: 0.35mm PCB ball land suggested <= 0.35mm Min Millimeters Nom Max Min Inches Nom A --- --- 1.20 --- --- 0.047 A1 0.26 0.31 0.36 0.010 0.012 0.014 A2 --- 0.85 --- --- 0.033 --- b 0.35 0.40 0.45 0.014 0.016 0.018 D 7.90 8.00 8.10 0.311 0.315 0.319 6.10 0.232 Symbol D1 E 4.00 BSC 5.90 6.00 0.157 BSC 0.236 E1 4.00 BSC 0.157 BSC 0.039 TYP SE 1.00 TYP SD 1.00 TYP 0.039 TYP e 1.00 BSC 0.039 BSC ccc --- --- Max 0.10 - 71 - --- --- 0.240 0.0039 Publication Release Date: November 22, 2017 Revision I W25Q64JV 10.8 24-Ball TFBGA 8x6-mm (Package Code TC, 6x4 ball array) Note: Ball land: 0.45mm. Ball Opening: 0.35mm PCB ball land suggested <= 0.35mm Symbol Min Millimeters Nom Max Min Inches Nom Max A --- --- 1.20 --- --- 0.047 A1 0.25 0.30 0.35 0.010 0.012 0.014 b 0.35 0.40 0.45 0.014 0.016 0.018 D 7.95 8.00 8.05 0.313 0.315 0.317 D1 E 5.00 BSC 5.95 E1 6.05 0.234 3.00 BSC e ccc 6.00 0.197 BSC 1.00 BSC --- --- 0.236 0.238 0.118 BSC 0.039 BSC 0.10 - 72 - --- --- 0.039 Publication Release Date: November 22, 2017 Revision I W25Q64JV 10.9 12-Ball WLCSP (Package Code BY) Symbol A A1 c b D1 D2 D3 E1 E2 E3 eD eE aaa bbb ccc ddd Min 0.432 0.152 0.280 0.240 Millimeters Nom 0.472 0.167 0.305 0.300 1.200 0.301 0.301 2.200 0.396 0.396 0.5 BSC 0.5 BSC 0.10 0.10 0.03 0.15 Max Min 0.512 0.182 0.330 0.360 0.017 0.006 0.012 0.009 Inches Nom 0.019 0.007 0.013 0.012 0.0472 0.0119 0.0119 0.0866 0.0156 0.0156 0.020 BSC 0.020 BSC 0.004 0.004 0.001 0.006 Max 0.020 0.007 0.014 0.014 Notes: 1. 2. Dimension b is measured at the maximum solder bump diameter, parallel to primary datum C. Dimension D and E; please contact Winbond for details. - 73 - Publication Release Date: November 22, 2017 Revision I W25Q64JV 11. ORDERING INFORMATION W(1) 25Q 64J V xx(2) I W = Winbond 25Q = SpiFlash Serial Flash Memory with 4KB sectors, Dual/Quad I/O 64J = 64M-bit V = 2.7V to 3.6V SS = 8-pin SOIC 208-mil ZP = WSON8 6x5-mm XG = XSON 4x4x0.45-mm TC = TFBGA 8x6-mm (6x4 ball array) I SF = 16-pin SOIC 300-mil ZE = WSON8 8x6-mm TB = TFBGA 8x6-mm (5x5 ball array) BY = 12-ball WLCSP = Industrial (-40C to +85C) (3,4) Q(5) = Green Package (Lead-free, RoHS Compliant, Halogen-free (TBBA), Antimony-Oxide-free Sb2O3) with QE = 1 (fixed) in Status register-2. Backward compatible to FV family. M(6) = Green Package (Lead-free, RoHS Compliant, Halogen-free (TBBA), Antimony-Oxide-free Sb2O3) with QE = 0 (programmable) in Status register-2. New device ID is used to identify JV family Notes: 1. 2. 3. 4. 5. 6. The "W" prefix is not included on the part marking. Only the 2nd letter is used for the part marking; WSON package type ZP is not used for the part marking. Standard bulk shipments are in Tube (shape E). Please specify alternate packing method, such as Tape and Reel (shape T) or Tray (shape S), when placing orders. For shipments with OTP feature enabled, please specify when placing orders. /HOLD function is disabled to support Standard, Dual and Quad I/O without user setting. For DTR, QPI supporting, please refer to W25Q64JV DTR datasheet. - 74 - Publication Release Date: November 22, 2017 Revision I W25Q64JV 11.1 Valid Part Numbers and Top Side Marking The following table provides the valid part numbers for the W25Q64JV SpiFlash Memory. Please contact Winbond for specific availability by density and package type. Winbond SpiFlash memories use a 12-digit Product Number for ordering. However, due to limited space, the Top Side Marking on all packages uses an abbreviated 10-digit number. W25Q64JV-IQ valid part numbers: PACKAGE TYPE DENSITY PRODUCT NUMBER TOP SIDE MARKING 64M-bit W25Q64JVSSIQ 25Q64JVSIQ 64M-bit W25Q64JVSFIQ 25Q64JVFIQ 64M-bit W25Q64JVZPIQ 25Q64JVIQ ZE(1) WSON-8 8x6-mm 64M-bit W25Q64JVZEIQ 25Q64JVIQ XG XSON-8 4x4x0.45-mm 64M-bit W25Q64JVXGIQ Q64JVXGIQ TB(2) TFBGA-24 8x6-mm (5x5 Ball Array) 64M-bit W25Q64JVTBIQ 25Q64JVBIQ TC(2) TFBGA-24 8x6-mm (6x4 Ball Array) 64M-bit W25Q64JVTCIQ 25Q64JVCIQ BY(2) 12-ball WLCSP 64M-bit W25Q64JVBYIQ 6CJI *Qyw(4) DENSITY PRODUCT NUMBER TOP SIDE MARKING 64M-bit W25Q64JVSSIM 25Q64JVSIM 64M-bit W25Q64JVSFIM 25Q64JVFIM 64M-bit W25Q64JVZPIM 25Q64JVIM ZE(1) WSON-8 8x6-mm 64M-bit W25Q64JVZEIM 25Q64JVIM XG XSON-8 4x4x0.45-mm 64M-bit W25Q64JVXGIM Q64JVXGIM SS SOIC-8 208-mil SF SOIC-16 300-mil ZP(1) WSON-8 6x5-mm W25Q64JV-IM(3) valid part numbers: PACKAGE TYPE SS SOIC-8 208-mil SF SOIC-16 300-mil ZP WSON-8 6x5-mm Note: 1. 2. 3. 4. For WSON packages, the package type ZP and ZE is not used in the top side marking. These package types are special order, please contact Winbond for more information For DTR, QPI supporting, please refer to W25Q64JV DTR datasheet. yw: year/ week. - 75 - Publication Release Date: November 22, 2017 Revision I W25Q64JV 12. REVISION IISTORY VERSION DATE PAGE DESCRIPTION A 2015/01/07 New Create Datasheet B 2016/04/12 Removed "Preliminary" C 2016/06/03 16 73-76 D 2016/08/30 4 8 E 2016/10/24 F 2016/11/15 12 G 2016/12/14 4-5, 67, 71-72 H 2017/05/11 I 2017/11/22 Updated QE description Added TFBGA information Added data retention Added TFBGA 5X5 Removed PDIP 8 information Updated Status Register-1 table Updated XSON package information 20, 73-74 Updated /WP information Updated W25Q64JV-IM order information 8, 72-75 Added WLCSP package type Trademarks Winbond and SpiFlash are trademarks of Winbond Electronics Corporation. All other marks are the property of their respective owner. Important Notice Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Furthermore, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. Information in this document is provided solely in connection with Winbond products. Winbond reserves the right to make changes, corrections, modifications or improvements to this document and the products and services described herein at any time, without notice. - 76 - Publication Release Date: November 22, 2017 Revision I