GMM77316280CTG-5/6 16,777,216 WORDS x 72 BIT CMOS DYNAMIC RAM MODULE Description Features The GMM77316280CTG is an 16M x 72 bits Dynamic RAM MODULE which is assembled 18 pieces of 16M x 4bit DRAMs in 32 pin TSOP package and two 16bit driver ICs in 48pin TSSOP package mounted on a 168 pin printed circuit board with decoupling capacitors. The GMM77316280CTG is optimized for application to the systems which are required high density and large capacity such as main memory of the computers and an image memory systems, and to the others which are requested compact size. The GMM77316280CTG provides common data inputs and Extended Data Outputs. * 168 pins Dual In-Line Package - GMM77316280CTG : Gold plating * Extended Data Ouput (EDO) Mode Capability * Single Power Supply * Fast Access Time & Cycle Time (Unit: ns) tRAC tCAC tRC Speed tHPC GMM77316280CTG-5 50 18 84 20 GMM77316280CTG-6 60 20 104 25 * Low Power Active : 9144/8496mW (MAX) Standby : 105mW (CMOS level : MAX) * RAS Only Refresh, CAS before RAS Refresh, Hidden Refresh Capability * All inputs and outputs TTL Compatible * 4096 Refresh Cycles/64ms GMM77316280CTG (Both Side) Pin Configuration (Top View) Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 VSS DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VCC DQ14 DQ15 DQ16 DQ17 VSS RSVD RSVD VCC /WE0 /CAS0 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 RSVD /RAS0 /OE0 VSS A0 A2 A4 A6 A8 A10 A12* VCC RFU RFU VSS /OE2 /RAS2 /CAS4 RSVD /WE2 VCC RSVD RSVD DQ18 DQ19 VSS DQ20 DQ21 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 DQ22 DQ23 Vcc DQ24 RFU RFU RFU RFU DQ25 DQ26 DQ27 VSS DQ28 DQ29 DQ30 DQ31 VCC DQ32 DQ33 DQ34 DQ35 VSS PD1 PD3 PD5 PD7 ID 0 VCC 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 VSS DQ36 DQ37 DQ38 DQ39 VCC DQ40 DQ41 DQ42 DQ43 DQ44 VSS DQ45 DQ46 DQ47 DQ48 DQ49 VCC DQ50 DQ51 DQ52 DQ53 VSS RSVD RSVD VCC RFU /CAS1* 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 RSVD /RAS1* RFU VSS A1 A3 A5 A7 A9 A11 A13* VCC RFU B0 VSS RFU /RAS3* /CAS5* RSVD /PDE VCC RSVD RSVD DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 VCC DQ60 RFU RFU RFU RFU DQ61 DQ62 DQ63 VSS DQ64 DQ65 DQ66 DQ67 VCC DQ68 DQ69 DQ70 DQ71 VSS PD2 PD4 PD6 PD8 ID 1 VCC Note : Pins Marked * are not used in this module. * This Data Sheet is subject to change without notice. 1 GMM77316280CTG-5/6 Block Diagram RAS0 RAS2 CAS0 CAS4 WE0 WE2 OE0 A1~A11 OE2 DQ 0 DQ 1 DQ 2 DQ 3 DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 DQ 0 DQ 1 DQ 2 DQ 3 DQ 8 DQ 9 DQ 10 DQ 11 DQ 0 DQ 1 DQ 2 DQ 3 DQ 12 DQ 13 DQ 14 DQ 15 DQ 0 DQ 1 DQ 2 DQ 3 DQ 16 DQ 17 DQ 18 DQ 19 DQ 0 DQ 1 DQ 2 DQ 3 DQ 20 DQ 21 DQ 22 DQ 23 DQ 0 DQ 1 DQ 2 DQ 3 DQ 24 DQ 25 DQ 26 DQ 27 DQ 0 DQ 1 DQ 2 DQ 3 DQ 28 DQ 29 DQ 30 DQ 31 DQ 0 DQ 1 DQ 2 DQ 3 DQ 32 DQ 33 DQ 34 DQ 35 DQ 0 DQ 1 DQ 2 DQ 3 A1~A11 D0 D1 D2 D3 D4 D5 D6 D7 D8 DRAMS: D0~D17 DQ 36 DQ 37 DQ 38 DQ 39 DQ 0 DQ 1 DQ 2 DQ 3 DQ 40 DQ 41 DQ 42 DQ 43 DQ 0 DQ 1 DQ 2 DQ 3 DQ 44 DQ 45 DQ 46 DQ 47 DQ 0 DQ 1 DQ 2 DQ 3 DQ 48 DQ 49 DQ 50 DQ 51 DQ 0 DQ 1 DQ 2 DQ 3 DQ 52 DQ 53 DQ 54 DQ 55 DQ 0 DQ 1 DQ 2 DQ 3 DQ 56 DQ 57 DQ 58 DQ 59 DQ 0 DQ 1 DQ 2 DQ 3 DQ 60 DQ 61 DQ 62 DQ 63 DQ 0 DQ 1 DQ 2 DQ 3 DQ 64 DQ 65 DQ 66 DQ 67 DQ 0 DQ 1 DQ 2 DQ 3 DQ 68 DQ 69 DQ 70 DQ 71 DQ 0 DQ 1 DQ 2 DQ 3 D9 D10 D11 D12 D13 D14 D15 D16 D17 VSS (when= 0, 1= NC) PDE A0 DRAMS: D0~D8 B0 DRAMS: D9~D17 VCC VSS VCC + 2.2uF Tantal Capacitor D0~D17, Buffer 0.22uF Capacitor VSS D0~D17, Buffer 2 GMM77316280CTG-5/6 Pin Description Function Pin Pin Function Address Inputs PDE Presence Detect Enable Data Input/Output VCC Power (+3.3V) RAS0, RAS2 Row Address Strobe VSS Ground CAS0, CAS4 Column Address Strobe NC No Connection A0,B0,A1-A11 DQ0-DQ71 WE0, WE2 Read/Write Enable PD 1~8 Presence Detect ID 0~1 ID bit Output Enable OE0, OE2 RSVD Reserved Use RFU Reserved for Future Use Presence Detect Pins (Optional) 50ns Pin 60ns 1 1 1 1 1 1 1 0 0 0 1 1 1 1 1 0 0 0 0 0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 ID0 ID1 Absolute Maximum Ratings* Symbol Rating Unit 0 ~ 70 C Storage Temperature (Plastic) -55 ~ 125 C VIN/VOUT Voltage on any Pin Relative to VSS -0.5 ~ 4.6 V Vcc Voltage on Vcc Pin Relative to VSS -0.5 ~ 4.6 V TA TSTG Parameter Ambient Temperature under Bias IOUT Short Circuit Output Current 50 mA PD Power Dissipation 21 W *Note: 1. Stress greater than above Absolute Maximum Ratings may cause permanent damage to the device. Recommended DC Operating Conditions (TA = 0 ~ 70C) Symbol Parameter Min Typ Max Unit Note VCC Supply Voltage 3.0 3.3 3.6 V 1 VIH Input High Voltage 2.0 - Vcc+0.3 V 1 VIL Input Low Voltage -0.3 - 0.8 V 1 *Note: 1. All voltages referenced to VSS. 3 GMM77316280CTG-5/6 DC Electrical Characteristics: (VCC = 3.3V+/-0.3V, TA = 0 ~ 70C) GMM77316280CTG Symbol Parameter Unit Min Max VOH Output Level Output H Level Voltage (IOUT = -2 I) 2.4 Vcc V VOL Output Level Output L Level Voltage (IOUT = 2 I) 0 0.4 V - 2540 ICC1 Operating Current Average Power Supply Operating Current (RAS, CAS Cycling: tRC = tRC min) ICC2 Standby Current (TTL) Power Supply Standby Current (RAS, CAS = VIH, DOUT = High-Z) ICC3 RAS-Only Refresh Current Average Power Supply Current RAS-Only Refresh Mode (RAS Cycling, CAS = VIH, tRC = tRC min) Extended Data Out Mode Current Average Power Supply Current Extended Data Out Mode (RAS = VIL, CAS, Address Cycling: tPC = tPC min) ICC4 ICC5 Standby Current (CMOS) Power Supply Standby Current (RAS, CAS>=VCC-0.2V, DOUT = High-Z) ICC6 CAS-before-RAS Refresh Current (tRC = tRC min) 50ns I 60ns 56 50ns - 2540 60ns - 2360 50ns - 2000 60ns 50ns - 1820 - 29 - 2540 I I 2 I 1,3 I I - 2360 - 110 I ICC7 Standby Current II(L) Input Leakage Current, Any Input (0V VIN Vcc) -5 5 uA IO(L) Output Leakage Current (DOUT is Disabled, 0V VOUT -5 5 uA Vcc) 1,2 2360 - 60ns RAS = VIH CAS = VIL DOUT = Enable - Note 1 Note: 1. ICC depends on output load condition when the device is selected. ICC(max) is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Address can be changed once or less while CAS = VIH. 4 GMM77316280CTG-5/6 Capacitance (VCC = 3.3V+/-0.3V, TA = 25C, f = 1MHz) Symbol Min Max Unit CI1 Input Capacitance (A0~A11,B0) Parameter - 20 pF Note 1 CI2 Input Capacitance (WE0, WE2, OE0, OE2) - 20 pF 1, 2 C13 Input Capacitance (RAS0,RAS2) - 65 pF 1, 2 C14 Input Capacitance (CAS0,CAS4) - 20 pF 1, 2 CI/O I/O Capacitance (DQ0~DQ71) - 20 pF 1, 2 Note: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. CAS = VIH to disable DOUT. AC Characteristics (VCC = 3.3V+/-0.3V, TA = 0 ~ 70C, Notes 1, 2,19) Test Conditions Input rise and fall times : 2ns Input level : VIL/VIH = 0.0/3.0V Input timing reference levels : VIL/VIH = 0.8/2.0V Output timing reference levels : VOL/VOH = 0.8/2.0V Output load : 1 TTL gate+CL (100pF) (Including scope and jig) Read, Write, Read-Modify-Write and Refresh Cycles (Common Parameters) GMM77316280CTG-5 GMM77316280CTG-6 Symbol Parameter Min Max Min Max Unit Notes tRC Random Read or Write Cycle Time 84 - 104 - A tRP RAS Precharge Time 30 - 40 - A tCP CAS Precharge Time 8 - 10 - A tRAS RAS Pulse Width 50 10000 60 10000 A tCAS CAS Pulse Width 8 10000 10 10000 A tASR Row Address Set-up Time 5 - 5 - A tRAH Row Address Hold Time 8 - 10 - A tASC Column Address Set-up Time 0 - 0 - A tCAH Column Address Hold Time 8 - 10 - A tRCD RAS to CAS Delay Time 12 32 14 40 A 3 tRAD RAS to Column Address Delay Time 10 20 12 25 A 4 tRSH RAS Hold Time 18 - 20 - A tCSH CAS Hold Time 35 - 40 - A tCRP CAS to RAS Precharge Time 10 - 10 - A tODD OE to DIN Delay Time 18 - 20 - A 5 tDZO OE Delay Time from DIN 0 - 0 - A 6 tDZC CAS Set-up Time from DIN 0 - 0 - A 6 TransitionTime (Rise and Fall) 2 50 2 50 A 7 Refresh Period ( 4096 Cycles) - 64 - 64 ms tT tREF 5 GMM77316280CTG-5/6 Read Cycles Symbol Parameter GMM77316280CTG-5 GMM77316280CTG-6 Unit Min Max Min Max Notes tRAC Access Time from RAS - 50 - 60 A tCAC Access Time from CAS - 18 - 20 A9,10,17 tAA Access Time from Column Address - 30 - 35 A9,11,17 tOAC Access Time from OE - 18 - 20 A tRCS Read Command Set-up Time 0 - 0 - A tRCH Read Command Hold Time to CAS 0 - 0 - A 12 tRRH Read Command Hold Time to RAS 0 - 0 - A 12 tRAL Column Address to RAS Lead TIme 30 - 35 - A tCAL Column Address to CAS Lead Time 15 - 18 - A tOFF Output Buffer Turn-off Delay Time from CAS - 18 - 20 A 13,21 tOEZ Output Buffer Turn-off Delay Time from OE - 18 - 20 A 13 tCDD CAS to DIN Delay Time 18 - 20 - A 5 tRDD RAS to DIN Delay Time 13 - 15 - A tWDD WE to DIN Delay Time 13 - 15 - A tOFR Output Buffer Turn-off Delay Time from RAS - 13 - 15 A 13,21 tWEZ Output Buffer Turn-off Delay Time from WE - 13 - 15 A 13 tOH Output Data Hold Time 3 - 3 - A 21 tOHR Output Data Hold Time from RAS 3 - 3 - A 21 tRCHR Read Command Hold Time from RAS 50 - 60 - A tOHO Output Data Hold Time from OE 3 - 3 - A tCLZ CAS to Output in Low - Z 2 - 2 - A 8,9 9 6 GMM77316280CTG-5/6 Wrtie Cycles GMM77316280CTG-5 Symbol GMM77316280CTG-6 Parameter Min Max Min Max Unit Notes tWCS Write Command Set-up Time 0 - 0 - A 14 tWCH Write Command Hold Time 8 - 10 - A 21 tWP Write Command Pulse Width 8 - 10 - A tRWL Write Command to RAS Lead Time 18 - 20 - A tCWL Write Command to CAS Lead Time 8 - 10 - A tDS Data-in Set-up Time 0 - 0 - A 15 tDH Data-in Hold Time 13 - 15 - A 15 Read-Modify-Write Cycles GMM77316280CTG-5 GMM77316280CTG-6 Symbol Parameter Min Max Min Max Unit Notes tRWC Read-Modify-Write Cycle Time 116 - 140 - A tRWD RAS to WE Delay Time 72 - 84 - A 14 tCWD CAS to WE Delay Time 30 - 34 - A 14 tAWD Column Address to WE Delay Time 42 - 49 - A 14 tOEH OE Hold Time from WE 13 - 15 - A Cycles Refresh Cycle GMM77316280CTG-5 GMM77316280CTG-6 Symbol Parameter Min Max Min Max Unit Notes tCSR CAS Set-up Time (CAS-before-RAS Refresh Cycle) 5 - 5 - A tCHR CAS Hold Time (CAS-before-RAS Refresh Cycle) 8 - 10 - A tWRP WE setup Time (CAS-before-RAS Refresh Cycle) 5 tWRH WE Hold Time (CAS-before-RAS Refresh Cycle) 8 - 10 - A tRPC RAS Precharge to CAS Hold Time 5 - 5 - A A 5 7 GMM77316280CTG-5/6 Extended Data Out Mode Cycles GMM77316280CTG-5 Symbol GMM77316280CTG-6 Parameter Unit Min Max Min Max Notes tHPC EDO Page Mode Cycle Time 20 - 25 - A 20 tWPE Write pulse width during CAS Precharge 8 - 10 - A tRASP EDO Mode RAS Pulse Width - 100000 - tACP Access Time from CAS Precharge - 28 - 35 tRHCP RAS Hold Time from CAS Precharge 33 - 40 - A tCOL CAS Hold Time Referred OE 8 - 10 - A tCOP CAS to OE set-up Time 5 - 5 - A tRCHP Read Command Hold Time from CAS Precharge 28 - 35 - A tDOH Output Data Hold Time from CAS Low 5 - 5 - A 9,22 tOEP OE Precharge Time 8 - 10 - A 100000 A 16 A 9,17 EDO Page Mode Read-Modify-Write cycle GMM77316280CTG-5 Symbol tHPRWC tCPW GMM77316280CTG-6 Parameter EDO Page Mode Read-Modify-Write Cycle Time WE delay time from CAS precharge Notes Unit Min Max Min Max 57 - 68 - A 45 - 54 - A 14 Present Detect Read cycle GMM77316280CTG-5 GMM77316280CTG-6 Symbol tPD tPDOFF Parameter Unit Min PDE to Valid PD bit PDE to PD bit in active Max Min 10 2 7 2 Notes Max 10 ns 7 A 8 GMM77316280CTG-5/6 Notes: AC measurements assume tT = 2 .A AC initial pause of 200 us is required after power up followed by a minimum of eight initialization cycles ( any combination of cycles containing RAS-only refresh or CAS-beforeRAS refresh) 3. Operation with the t RCD(max) limit insures that tRAC(max) can be met, tRCD(max) is specified as a reference point only: if t RCD is greater than the specified t RCD(max) limit, then access time is controlled exclusively by tCAC. 4. Operation with the t RAD(max) limit insures that tRAC(max) can be met, tRAD(max) is specified as a reference point only: if t RAD is greater than the specified t RAD(max) limit, then access time is controlled exclusively by tAA. 5. Either tOED or tCDD must be satisfied. 6. Either tDZO or tDZC must be satisfied. 7. VIH (min) and V IL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between VIH(min) and VIL (max). 8. Assumes that t RCD<=tRCD(max) and t RAD<=tRAD(max). If t RCD or tRAD is greater than the maximum recommended value shown in this table, tRAC exceeds the value shown. 9. Measured with a load circuit equivalent to 1 TTL loads and 100 pF. 10. Assumes that tRCD>=tRCD(max) and tRCD + tCAC(max) >=tRAD + tAA(max). 11. Assumes that tRAD >=tRAD (max) and tRCD + tCAC(max)<=tRAD + tAA(max). 12. Either tRCH or tRRH must be satisfied for a read cycles. 1. 2. 13. tOFF(max), tOEZ(max), t OFR(max) and t WEZ(max) define the time at which the outputs achieve the open circuit condition and is not referenced to output voltage levels. 14. tWCS, t RWD, t CWD, t AWD, and t CPW are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only: if t WCS >=tWCS(min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle: if tRWD >= tRWD(min), t CWD>=tCWD(min), t AWD>=tAWD(min) and t CPW>=tCPW(min), the cycle is a readmodify-write and the data output will contain data read from the selected cell: if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 15. tDS and t DH are referred to CAS leading edge in early write cycles and to WE leading edge in delayed write or read-modify-write cycles. 16. tRASP defines RAS pulse width in extended data out mode cycles. 17. Access time is determined by the longest among tAA, tCAC and tCPA. 18. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to the device. 19. When output buffers are enabled once, sustain the low impedance state until valid data is obtained. When output buffer is turned on and off within a very short time, generally it causes large VCC/VSS line noise, which causes to degrade VIH min/VIL max level. 9 GMM77316280CTG-5/6 20. tHPC(min) can be achieved during a series of EDO mode early write cycles or EDO mode read cycles. If both write and read operation are mixed in a EDO mode, RAS cycle { EDO mode mix cycle (1),(2) } minimum value of CAS cycle t HPC(tCAS + t CP + 2t T) becomes greater than the specified tHPC(min) value. The value of CAS cycle time of mixed EDO page mode is shown in EDO page mode mix cycle (1) and (2). 21. Data output turns off and becomes high impedance from later rising edge of RAS and CAS. Hold time and turn off time are specified by the timing specifications of later rising edge of RAS and CAS between tOHR and tOH, and between tOFR and tOFF. 22. tDOH defines the time at which the output level go cross. V OL=0.8V, VOH=2.0V of output timing reference level. 23. Before and after self refresh mode, execute CBR refresh to all refresh addresses in or within 64 Aperiod on the condition a and b below. a. Enter self refresh mode within 15.6 us after either burst refresh or distributed refresh at equal interval to all refresh addresses are completed. b. Start burst refresh or distributed refresh at equal interval to all refresh addressed within 15.6us after exiting from self refresh mode. 24. In case of entering from RAS-only-refresh, it is necessary to execute CBR refresh before and after self refresh mode according as note 23. 25. For L_version, it is available to apply each 128 Aand 31.2 us instead of 64 Aand 15.6us at note 23. t 1/4 10us. It is undefined 26. At t RASS 3/4100 us , self refresh mode is activated, and not activated atRASS within the range of 10 us t1/4RASS 11/400 us . for tRASS 13/40 us , it is necessary to satisfy tRPS. 27. XXX: H or L ( H : VIH(min)<=VIN<=VIH(max), L: VIH(min)<=VIN<=VIH(max)) ///////: Invalid Dout When the address, clock and input pins are not described on timing waveforms, their pins must be applied VIH or VIL. 10 GMM77316280CTG-5/6 Unit: mil (mm) * (1 mil = 1/1000 inches) Package Dimension 700(17.78) 1250(31.75) 157.48(4.0) 5250(133.35) 1 84 "C"1450(36.83) 450(11.43) "B" 2150(54.61) "A" 250(6.35) 1700(43.18) 4550(115.57) 5013.78(127.35) 157.48(4.0) max. 157.48(4.0) min. (Front Side) 168 85 (Rear Side) 39.37(1.0) R78.74 (2.0) 125(3.175) 50(1.27) 125(3.175) 39.37(1.0) DETAIL "C" 78.74(2.0) DETAIL "B" 100(2.54) min. R78.74 (2.0) 39.37(1.0) 5.9(0.15) 122.83(3.12) 78.74(2.0) 50(1.27) DETAIL "A" NOTE : 1. Tolerances on all dimensions +/-5 (0.127) unless otherwise specified. 2. Thickness includes Plating and / or Metallization. 11