Kinetis K22F 128KB Flash
100 MHz ARM® Cortex®-M4 Based Microcontroller with FPU
The Kinetis K22 product family members are optimized for cost-
sensitive applications requiring low-power, USB connectivity,
high peripheral integration and processing efficiency with a
floating-point unit. These devices share the comprehensive
enablement and scalability of the Kinetis family.
This product offers:
• Run power consumption down to 120 μA/MHz. Static
power consumption down to 2.6 μA with full state retention
and 6 μs wakeup. Lowest static mode down to 120 nA.
• USB LS/FS OTG 2.0 with embedded 3.3 V, USB FS device
crystal-less functionality.
Performance
• 100 MHz ARM Cortex-M4 core with DSP instructions
delivering 1.25 Dhrystone MIPS per MHz
Memories and memory interfaces
• 128 KB of embedded flash and 24 KB of RAM
• Serial programming interface(EzPort)
• Pre-programmed Kinetis flashloader for one-time, in-
system factory programming
System peripherals
• Flexible low-power modes, multiple wakeup sources
• 4-channel DMA controller
• Independent External and Software Watchdog monitor
Clocks
• Two crystal oscillators: 32 kHz (RTC) and 32-40 kHz or
3-32 MHz
• Three internal oscillators: 32 kHz, 4 MHz, and 48 MHz
• Multi-purpose clock generator with FLL
Security and integrity modules
• Hardware CRC module
• 128-bit unique identification (ID) number per chip
• Flash access control to protect proprietary software
Human-machine interface
• Up to 67 general-purpose I/O (GPIO)
Analog modules
• Two 16-bit SAR ADCs (1.2 MS/s in 12bit mode)
• One 12-bit DAC
• Two analog comparators (CMP) with 6-bit DAC
• Accurate internal voltage reference
Communication interfaces
• USB LS/FS OTG 2.0 with on-chip transceiver
• USB full-speed device crystal-less operation
• Two SPI modules
• Three UART modules and one low-power UART
• Two I2C: Support for up to 1 Mbps operation
• I2S module
Timers
• One 8-channel general-purpose/PWM timer
• Two 2-channel general-purpose timers with
quadrature decoder functionality
• Periodic interrupt timers
• 16-bit low-power timer
• Real-time clock with independent power domain
• Programmable delay block
Operating Characteristics
• Voltage range (including flash writes): 1.71 to 3.6 V
• Temperature range (ambient): -40 to 105°C
MK22FN128VDC10
MK22FN128VLL10
MK22FN128VMP10
MK22FN128VLH10
121 XFBGA (DC)
8 x 8 x 0.5 Pitch 0.65
mm
100 LQFP (LL)
14 x 14 x 1.4 Pitch 0.5
mm
64 MAPBGA (MP)
5 x 5 x 1.2 Pitch 0.5
mm
64 LQFP (LH)
10 x 10 x 1.4 Pitch 0.5
mm
NXP Semiconductors K22P121M100SF9
Data Sheet: Technical Data Rev. 7, 08/2016
NXP reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products.
Ordering Information
Part Number Memory Number of GPIOs
Flash (KB) SRAM (KB)
MK22FN128VDC10 128 24 67
MK22FN128VLL10 128 24 66
MK22FN128VMP10 128 24 40
MK22FN128VLH10 128 24 40
Device Revision Number
Device Mask Set Number SIM_SDID[REVID] JTAG ID Register[PRN]
0N74K 0000 0000
Related Resources
Type Description Resource
Selector
Guide
The NXP Solution Advisor is a web-based tool that features interactive
application wizards and a dynamic product selector
KINETISKMCUSELGD
Product Brief The Product Brief contains concise overview/summary information to
enable quick evaluation of a device for design suitability.
K22FPB
Reference
Manual
The Reference Manual contains a comprehensive description of the
structure and function (operation) of a device.
K22P121M100SF9RM
Data Sheet The Data Sheet is this document. It includes electrical characteristics
and signal connections.
K22P121M100SF9
Chip Errata The chip mask set Errata provides additional or corrective information for
a particular device mask set.
KINETIS_K_xN74K 1
Package
drawing
Package dimensions are provided by part number:
• MK22FN128VDC10
• MK22FN128VLL10
• MK22FN128VMP10
• MK22FN128VLH10
Package drawing:
•98ASA00595D
•98ASS23308W
•98ASA00420D
•98ASS23234W
1. To find the associated resource, go to nxp.com and perform a search using this term with the x replaced by the revision
of the device you are using.
Figure 1 shows the functional modules in the chip.
2Kinetis K22F 128KB Flash, Rev. 7, 08/2016
NXP Semiconductors
Memories and Memory Interfaces
Program
(128 KB)
RAM
CRC
Programmable
Analog Timers Communication InterfacesSecurity
and Integrity
x1
Clocks
Frequency-
Core
Debug
interfaces DSP
Interrupt
controller
Comparator
x2
16-bit
timer
Human-Machine
Interface (HMI)
Up to
System
DMA (4 ch)
Low-leakage
wakeup
locked loop
Serial
programming
interface
(EzPort)
reference
Internal
clocks
delay block
timers
interrupt
Periodic
real-time
Independent
clock
oscillators
Low/high
frequency
UART
x3
®
Cortex™-M4ARM
FPU
voltage ref
USB OTG
LS/FS
USB LS/FS
transceiver
IS
2
x2
IC
2
Timers
x1 (8ch)
SAR ADC x2
SPI
x2
LPUART
High
performance
Flash access
control
low-power
67 GPIOs
(24 KB)
flash
Internal
watchdogs
and external
with 6-bit DAC
12-bit DAC
x1
x2 (2ch)
16-bit
Figure 1. Functional block diagram
Kinetis K22F 128KB Flash, Rev. 7, 08/2016 3
NXP Semiconductors
Table of Contents
1 Ratings....................................................................................5
1.1 Thermal handling ratings................................................. 5
1.2 Moisture handling ratings................................................ 5
1.3 ESD handling ratings.......................................................5
1.4 Voltage and current operating ratings............................. 5
2 General................................................................................... 6
2.1 AC electrical characteristics.............................................6
2.2 Nonswitching electrical specifications..............................6
2.2.1 Voltage and current operating requirements....... 6
2.2.2 LVD and POR operating requirements................7
2.2.3 Voltage and current operating behaviors.............8
2.2.4 Power mode transition operating behaviors........ 9
2.2.5 Power consumption operating behaviors............ 10
2.2.6 EMC radiated emissions operating behaviors.....17
2.2.7 Designing with radiated emissions in mind..........18
2.2.8 Capacitance attributes.........................................18
2.3 Switching specifications...................................................18
2.3.1 Device clock specifications..................................18
2.3.2 General switching specifications......................... 19
2.4 Thermal specifications.....................................................20
2.4.1 Thermal operating requirements......................... 20
2.4.2 Thermal attributes................................................20
3 Peripheral operating requirements and behaviors.................. 21
3.1 Core modules.................................................................. 21
3.1.1 SWD electricals .................................................. 21
3.1.2 JTAG electricals.................................................. 22
3.2 System modules.............................................................. 25
3.3 Clock modules................................................................. 25
3.3.1 MCG specifications..............................................25
3.3.2 IRC48M specifications.........................................27
3.3.3 Oscillator electrical specifications........................28
3.3.4 32 kHz oscillator electrical characteristics...........30
3.4 Memories and memory interfaces................................... 31
3.4.1 Flash electrical specifications..............................31
3.4.2 EzPort switching specifications........................... 32
3.5 Security and integrity modules........................................ 33
3.6 Analog............................................................................. 33
3.6.1 ADC electrical specifications............................... 34
3.6.2 CMP and 6-bit DAC electrical specifications....... 38
3.6.3 12-bit DAC electrical characteristics....................40
3.6.4 Voltage reference electrical specifications.......... 43
3.7 Timers..............................................................................44
3.8 Communication interfaces............................................... 44
3.8.1 USB electrical specifications............................... 45
3.8.2 DSPI switching specifications (limited voltage
range).................................................................. 45
3.8.3 DSPI switching specifications (full voltage
range).................................................................. 47
3.8.4 Inter-Integrated Circuit Interface (I2C) timing...... 48
3.8.5 UART switching specifications............................ 50
3.8.6 I2S/SAI switching specifications..........................50
4 Dimensions............................................................................. 56
4.1 Obtaining package dimensions....................................... 56
5 Pinout......................................................................................57
5.1 K22 Signal Multiplexing and Pin Assignments.................57
5.2 Recommended connection for unused analog and
digital pins........................................................................62
5.3 K22 Pinouts..................................................................... 63
6 Part identification.....................................................................67
6.1 Description.......................................................................67
6.2 Format............................................................................. 67
6.3 Fields............................................................................... 68
6.4 Example...........................................................................68
6.5 121-pin XFBGA part marking.......................................... 69
6.6 64-pin MAPBGA part marking......................................... 69
7 Terminology and guidelines.................................................... 69
7.1 Definitions........................................................................69
7.2 Examples.........................................................................70
7.3 Typical-value conditions.................................................. 70
7.4 Relationship between ratings and operating
requirements....................................................................71
7.5 Guidelines for ratings and operating requirements..........71
8 Revision History...................................................................... 71
4Kinetis K22F 128KB Flash, Rev. 7, 08/2016
NXP Semiconductors
1 Ratings
1.1 Thermal handling ratings
Symbol Description Min. Max. Unit Notes
TSTG Storage temperature –55 150 °C 1
TSDR Solder temperature, lead-free — 260 °C 2
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.2 Moisture handling ratings
Symbol Description Min. Max. Unit Notes
MSL Moisture sensitivity level — 3 — 1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.3 ESD handling ratings
Symbol Description Min. Max. Unit Notes
VHBM Electrostatic discharge voltage, human body model -2000 +2000 V 1
VCDM Electrostatic discharge voltage, charged-device
model
-500 +500 V 2
ILAT Latch-up current at ambient temperature of 105°C -100 +100 mA 3
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human
Body Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.
1.4 Voltage and current operating ratings
Ratings
Kinetis K22F 128KB Flash, Rev. 7, 08/2016 5
NXP Semiconductors
Symbol Description Min. Max. Unit
USBVDD USB Transceiver supply voltage –0.3 3.8 V
VDD Digital supply voltage –0.3 3.8 V
IDD Digital supply current — 145 mA
VDIO Digital input voltage –0.3 VDD + 0.3 V
VAIO Analog1–0.3 VDD + 0.3 V
IDMaximum current single pin limit (applies to all digital pins) –25 25 mA
VDDA Analog supply voltage VDD – 0.3 VDD + 0.3 V
VUSB0_DP USB0_DP input voltage –0.3 3.63 V
VUSB0_DM USB0_DM input voltage –0.3 3.63 V
VBAT RTC battery supply voltage –0.3 3.8 V
1. Analog pins are defined as pins that do not have an associated general purpose I/O port function.
2 General
2.1 AC electrical characteristics
Unless otherwise specified, propagation delays are measured from the 50% to the 50%
point, and rise and fall times are measured at the 20% and 80% points, as shown in the
following figure.
80%
20%
50%
VIL
Input Signal
VIH
Fall Time
High
Low
Rise Time
Midpoint1
The midpoint is VIL + (VIH - VIL) / 2
Figure 2. Input signal measurement reference
2.2 Nonswitching electrical specifications
General
6Kinetis K22F 128KB Flash, Rev. 7, 08/2016
NXP Semiconductors
2.2.1 Voltage and current operating requirements
Table 1. Voltage and current operating requirements
Symbol Description Min. Max. Unit Notes
VDD Supply voltage 1.71 3.6 V
VDDA Analog supply voltage 1.71 3.6 V
VDD – VDDA VDD-to-VDDA differential voltage –0.1 0.1 V
VSS – VSSA VSS-to-VSSA differential voltage –0.1 0.1 V
VBAT RTC battery supply voltage 1.71 3.6 V
USBVDD USB Transceiver supply voltage 3.0 3.6 V 1
VIH Input high voltage
• 2.7 V ≤ VDD ≤ 3.6 V
• 1.7 V ≤ VDD ≤ 2.7 V
0.7 × VDD
0.75 × VDD
—
—
V
V
VIL Input low voltage
• 2.7 V ≤ VDD ≤ 3.6 V
• 1.7 V ≤ VDD ≤ 2.7 V
—
—
0.35 × VDD
0.3 × VDD
V
V
VHYS Input hysteresis 0.06 × VDD — V
IICIO Analog and I/O pin DC injection current — single pin
• VIN < VSS-0.3V (Negative current injection) -3 — mA
2
IICcont Contiguous pin DC injection current —regional limit,
includes sum of negative injection currents or sum of
positive injection currents of 16 contiguous pins
• Negative current injection -25 — mA
VODPU Open drain pullup voltage level VDD VDD V3
VRAM VDD voltage required to retain RAM 1.2 — V
VRFVBAT VBAT voltage required to retain the VBAT register file VPOR_VBAT — V
1. USB nominal operating voltage is 3.3 V.
2. All analog and I/O pins are internally clamped to VSS through ESD protection diodes. If VIN is less than VIO_MIN or
greater than VIO_MAX, a current limiting resistor is required. The negative DC injection current limiting resistor is
calculated as R=(VIO_MIN-VIN)/|IICIO|.
3. Open drain outputs must be pulled to VDD.
2.2.2 LVD and POR operating requirements
Table 2. VDD supply LVD and POR operating requirements
Symbol Description Min. Typ. Max. Unit Notes
VPOR Falling VDD POR detect voltage 0.8 1.1 1.5 V
VLVDH Falling low-voltage detect threshold — high
range (LVDV=01)
2.48 2.56 2.64 V
Table continues on the next page...
General
Kinetis K22F 128KB Flash, Rev. 7, 08/2016 7
NXP Semiconductors
Table 2. VDD supply LVD and POR operating requirements (continued)
Symbol Description Min. Typ. Max. Unit Notes
VLVW1H
VLVW2H
VLVW3H
VLVW4H
Low-voltage warning thresholds — high range
• Level 1 falling (LVWV=00)
• Level 2 falling (LVWV=01)
• Level 3 falling (LVWV=10)
• Level 4 falling (LVWV=11)
2.62
2.72
2.82
2.92
2.70
2.80
2.90
3.00
2.78
2.88
2.98
3.08
V
V
V
V
1
VHYSH Low-voltage inhibit reset/recover hysteresis —
high range
— 80 — mV
VLVDL Falling low-voltage detect threshold — low
range (LVDV=00)
1.54 1.60 1.66 V
VLVW1L
VLVW2L
VLVW3L
VLVW4L
Low-voltage warning thresholds — low range
• Level 1 falling (LVWV=00)
• Level 2 falling (LVWV=01)
• Level 3 falling (LVWV=10)
• Level 4 falling (LVWV=11)
1.74
1.84
1.94
2.04
1.80
1.90
2.00
2.10
1.86
1.96
2.06
2.16
V
V
V
V
1
VHYSL Low-voltage inhibit reset/recover hysteresis —
low range
— 60 — mV
VBG Bandgap voltage reference 0.97 1.00 1.03 V
tLPO Internal low power oscillator period — factory
trimmed
900 1000 1100 μs
1. Rising threshold is the sum of falling threshold and hysteresis voltage
Table 3. VBAT power operating requirements
Symbol Description Min. Typ. Max. Unit Notes
VPOR_VBAT Falling VBAT supply POR detect voltage 0.8 1.1 1.5 V
2.2.3 Voltage and current operating behaviors
Table 4. Voltage and current operating behaviors
Symbol Description Min. Typ. Max. Unit Notes
VOH Output high voltage — Normal drive pad except
RESET_B
2.7 V ≤ VDD ≤ 3.6 V, IOH = -5 mA VDD – 0.5 — — V 1
1.71 V ≤ VDD ≤ 2.7 V, IOH = -2.5 mA VDD – 0.5 — — V
VOH Output high voltage — High drive pad except
RESET_B
2.7 V ≤ VDD ≤ 3.6 V, IOH = -20 mA VDD – 0.5 — — V 1
Table continues on the next page...
General
8Kinetis K22F 128KB Flash, Rev. 7, 08/2016
NXP Semiconductors
Table 4. Voltage and current operating behaviors (continued)
Symbol Description Min. Typ. Max. Unit Notes
1.71 V ≤ VDD ≤ 2.7 V, IOH = -10 mA VDD – 0.5 — — V
IOHT Output high current total for all ports — — 100 mA
VOL Output low voltage — Normal drive pad except
RESET_B
2.7 V ≤ VDD ≤ 3.6 V, IOL = 5 mA — — 0.5 V 1
1.71 V ≤ VDD ≤ 2.7 V, IOL = 2.5 mA — — 0.5 V
VOL Output low voltage — High drive pad except
RESET_B
2.7 V ≤ VDD ≤ 3.6 V, IOL = 20 mA — — 0.5 V 1
1.71 V ≤ VDD ≤ 2.7 V, IOL = 10 mA — — 0.5 V
VOL Output low voltage — RESET_B
2.7 V ≤ VDD ≤ 3.6 V, IOL = 3 mA — — 0.5 V
1.71 V ≤ VDD ≤ 2.7 V, IOL = 1.5 mA — — 0.5 V
IOLT Output low current total for all ports — — 100 mA
IIN Input leakage current (per pin) for full
temperature range
All pins other than high drive port pins — 0.002 0.5 μA 1, 2
High drive port pins — 0.004 0.5 μA
IIN Input leakage current (total all pins) for full
temperature range
— — 1.0 μA 2
RPU Internal pullup resistors 20 — 50 kΩ 3
RPD Internal pulldown resistors 20 — 50 kΩ 4
1. PTB0, PTB1, PTC3, PTC4, PTD4, PTD5, PTD6, and PTD7 I/O have both high drive and normal drive capability
selected by the associated PTx_PCRn[DSE] control bit. All other GPIOs are normal drive only.
2. Measured at VDD=3.6V
3. Measured at VDD supply voltage = VDD min and Vinput = VSS
4. Measured at VDD supply voltage = VDD min and Vinput = VDD
2.2.4 Power mode transition operating behaviors
All specifications except tPOR, and VLLSx→RUN recovery times in the following
table assume this clock configuration:
• CPU and system clocks = 72 MHz
• Bus clock = 36 MHz
• Flash clock = 24 MHz
• MCG mode: FEI
General
Kinetis K22F 128KB Flash, Rev. 7, 08/2016 9
NXP Semiconductors
Table 5. Power mode transition operating behaviors
Symbol Description Min. Typ. Max. Unit Notes
tPOR After a POR event, amount of time from the
point VDD reaches 1.71 V to execution of the
first instruction across the operating temperature
range of the chip.
— — 300 μs 1
• VLLS0 → RUN
—
—
135
μs
• VLLS1 → RUN
—
—
135
μs
• VLLS2 → RUN
—
—
75
μs
• VLLS3 → RUN
—
—
75
μs
• LLS2 → RUN
—
—
6
μs
• LLS3 → RUN
—
—
6
μs
• VLPS → RUN
—
—
5.7
μs
• STOP → RUN
—
—
5.7
μs
1. Normal boot (FTFA_OPT[LPBOOT]=1)
2.2.5 Power consumption operating behaviors
The current parameters in the table below are derived from code executing a while(1)
loop from flash, unless otherwise noted.
The IDD typical values represent the statistical mean at 25°C, and the IDD maximum
values for RUN, WAIT, VLPR, and VLPW represent data collected at 125°C junction
temperature unless otherwise noted. The maximum values represent characterized
results equivalent to the mean plus three times the standard deviation (mean + 3 sigma).
Table 6. Power consumption operating behaviors
Symbol Description Min. Typ. Max. Unit Notes
IDDA Analog supply current — — See note mA 1
IDD_HSRUN High Speed Run mode current - all peripheral
clocks disabled, CoreMark benchmark code
executing from flash
Table continues on the next page...
General
10 Kinetis K22F 128KB Flash, Rev. 7, 08/2016
NXP Semiconductors
Table 6. Power consumption operating behaviors (continued)
Symbol Description Min. Typ. Max. Unit Notes
@ 1.8V — 19.51 20.24 mA 2, 3, 4
@ 3.0V — 19.51 20.24 mA
IDD_HSRUN High Speed Run mode current - all peripheral
clocks disabled, code executing from flash
@ 1.8V — 16.9 17.63 mA 5
@ 3.0V — 17.0 17.73 mA
IDD_HSRUN High Speed Run mode current — all peripheral
clocks enabled, code executing from flash
@ 1.8V — 22.8 23.53 mA 6
@ 3.0V — 22.9 23.63 mA
IDD_RUN Run mode current in Compute operation —
CoreMark benchmark code executing from flash
@ 1.8V — 11.39 12.12 mA 2, 3, 7
@ 3.0V — 11.58 12.31 mA
IDD_RUN Run mode current in Compute operation —
code executing from flash
@ 1.8V — 10.90 11.90 mA 7
@ 3.0V — 10.90 12.23 mA
IDD_RUN Run mode current — all peripheral clocks
disabled, code executing from flash
@ 1.8V — 11.8 12.53 mA 8
@ 3.0V — 11.9 12.63 mA
IDD_RUN Run mode current — all peripheral clocks
enabled, code executing from flash
@ 1.8V — 15.5 16.23 mA 9
@ 3.0V
• @ 25°C — 15.6 16.33 mA
• @ 70°C — 15.6 16.33 mA
• @ 85°C — 15.6 16.33 mA
• @ 105°C — 16.3 17.03 mA
IDD_RUN Run mode current — Compute operation, code
executing from flash
@ 1.8V — 10.9 11.63 mA 10
@ 3.0V
• @ 25°C — 10.9 11.63 mA
• @ 70°C — 10.9 11.63 mA
• @ 85°C — 10.9 11.63 mA
• @ 105°C — 11.5 12.23 mA
Table continues on the next page...
General
Kinetis K22F 128KB Flash, Rev. 7, 08/2016 11
NXP Semiconductors
Table 6. Power consumption operating behaviors (continued)
Symbol Description Min. Typ. Max. Unit Notes
IDD_WAIT Wait mode high frequency current at 3.0 V — all
peripheral clocks disabled
— 6.5 7.23 mA 8
IDD_WAIT Wait mode reduced frequency current at 3.0 V
— all peripheral clocks disabled
— 3.9 4.63 mA 11
IDD_VLPR Very-low-power run mode current in Compute
operation — CoreMark benchmark code
executing from flash
@ 1.8V — 0.60 0.88 mA 2, 3, 12
@ 3.0V — 0.61 0.89 mA
IDD_VLPR Very-low-power run mode current in Compute
operation, code executing from flash
@ 1.8V — 0.48 0.76 mA 12
@ 3.0V — 0.48 0.76 mA
IDD_VLPR Very-low-power run mode current at 3.0 V — all
peripheral clocks disabled
— 0.54 0.82 mA 13
IDD_VLPR Very-low-power run mode current at 3.0 V — all
peripheral clocks enabled
— 0.79 1.07 mA 14
IDD_VLPW Very-low-power wait mode current at 3.0 V —
all peripheral clocks disabled
— 0.30 0.59 mA 15
IDD_STOP Stop mode current at 3.0 V
@ -40°C to 25°C — 0.27 0.33 mA
@ 70°C — 0.31 0.36 mA
@ 85°C — 0.31 0.36 mA
@ 105°C — 0.43 0.66 mA
IDD_VLPS Very-low-power stop mode current at 3.0 V
@ -40°C to 25°C — 4.2 9.00 µA
@ 70°C — 15.8 31.90 µA
@ 85°C — 26.9 50.95 µA
@ 105°C — 43.0 89.00 µA
IDD_LLS3 Low leakage stop mode 3 current at 3.0 V
@ -40°C to 25°C — 2.6 3.30 µA
@ 70°C — 6.2 8.60 µA
@ 85°C — 9.6 12.30 µA
@ 105°C — 15.0 26.00 µA
IDD_LLS2 Low leakage stop mode 2 current at 3.0 V
@ -40°C to 25°C — 2.4 3.00 µA
@ 70°C — 5.2 6.85 µA
@ 85°C — 7.9 9.95 µA
@ 105°C — 12.0 20.00 µA
IDD_VLLS3 Very low-leakage stop mode 3 current at 3.0 V
@ -40°C to 25°C — 1.8 2.10 µA
Table continues on the next page...
General
12 Kinetis K22F 128KB Flash, Rev. 7, 08/2016
NXP Semiconductors
Table 6. Power consumption operating behaviors (continued)
Symbol Description Min. Typ. Max. Unit Notes
@ 70°C — 4.3 5.70 µA
@ 85°C — 6.6 8.10 µA
@ 105°C — 10.0 17.00 µA
IDD_VLLS2 Very low-leakage stop mode 2 current at 3.0 V
@ -40°C to 25°C — 1.6 1.80 µA
@ 70°C — 3.1 3.90 µA
@ 85°C — 4.7 7.00 µA
@ 105°C — 6.8 10.90 µA
IDD_VLLS1 Very low-leakage stop mode 1 current at 3.0 V
@ -40°C to 25°C — 0.70 0.90 µA
@ 70°C — 1.78 2.09 µA
@ 85°C — 2.8 3.25 µA
@ 105°C — 4.0 6.15 µA
IDD_VLLS0 Very low-leakage stop mode 0 current at 3.0 V
with POR detect circuit enabled
@ -40°C to 25°C — 0.40 0.49 µA
@ 70°C — 1.38 1.49 µA
@ 85°C — 2.40 2.70 µA
@ 105°C — 3.6 5.65 µA
IDD_VLLS0 Very low-leakage stop mode 0 current at 3.0 V
with POR detect circuit disabled
@ -40°C to 25°C — 0.12 0.19 µA
@ 70°C — 1.05 1.13 µA
@ 85°C — 2.1 2.45 µA
@ 105°C — 3.3 5.35 µA
IDD_VBAT Average current with RTC and 32kHz disabled
at 3.0 V
@ -40°C to 25°C — 0.18 0.21 µA
@ 70°C — 0.66 0.86 µA
@ 85°C — 1.52 2.24 µA
@ 105°C — 2.92 4.30 µA
IDD_VBAT Average current when CPU is not accessing
RTC registers
@ 1.8V
• @ -40°C to 25°C — 0.57 0.67 µA 16
• @ 70°C — 0.90 1.2 µA
• @ 85°C — 0.90 1.2 µA
• @ 105°C — 2.4 3.5 µA
@ 3.0V
Table continues on the next page...
General
Kinetis K22F 128KB Flash, Rev. 7, 08/2016 13
NXP Semiconductors
Table 6. Power consumption operating behaviors (continued)
Symbol Description Min. Typ. Max. Unit Notes
• @ -40°C to 25°C — 0.67 0.94 µA
• @ 70°C — 1.0 1.4 µA
• @ 85°C — 1.0 1.4 µA
• @ 105°C — 2.7 3.9 µA
1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See
each module's specification for its supply current.
2. Cache on and prefetch on, low compiler optimization.
3. Coremark benchmark compiled using IAR 7.2 withs optimization level low.
4. 100 MHz core and system clock, 50 MHz bus clock, and 25 MHz flash clock. MCG configured for FEE mode. All
peripheral clocks disabled.
5. 100MHz core and system clock, 50MHz bus clock, and 25MHz flash clock. MCG configured for FEI mode. All peripheral
clocks disabled.
6. 100MHz core and system clock, 50MHz bus clock, and 25MHz flash clock. MCG configured for FEI mode. All peripheral
clocks enabled.
7. 72 MHz core and system clock, 36 MHz bus clock, and 24 MHz flash clock. MCG configured for FEE mode. All
peripheral clocks disabled. Compute operation.
8. 72MHz core and system clock, 36MHz bus clock, and 24MHz flash clock. MCG configured for FEI mode. All peripheral
clocks disabled.
9. 72MHz core and system clock, 36MHz bus clock, and 24MHz flash clock. MCG configured for FEI mode. All peripheral
clocks enabled.
10. 72MHz core and system clock, 36MHz bus clock, and 24MHz flash clock. MCG configured for FEI mode. Compute
Operation.
11. 25MHz core and system clock, 25MHz bus clock, and 25MHz flash clock. MCG configured for FEI mode.
12. 4 MHz core, system, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. Compute Operation. Code
executing from flash.
13. 4 MHz core, system, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. All peripheral clocks
disabled. Code executing from flash.
14. 4 MHz core, system, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. All peripheral clocks
enabled but peripherals are not in active operation. Code executing from flash.
15. 4 MHz core, system, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. All peripheral clocks
disabled.
16. Includes 32kHz oscillator current and RTC operation.
Table 7. Low power mode peripheral adders—typical value
Symbol Description Temperature (°C) Unit
-40 25 50 70 85 105
IIREFSTEN4MHz 4 MHz internal reference clock (IRC)
adder. Measured by entering STOP or
VLPS mode with 4 MHz IRC enabled.
56 56 56 56 56 56 µA
IIREFSTEN32KHz 32 kHz internal reference clock (IRC)
adder. Measured by entering STOP
mode with the 32 kHz IRC enabled.
52 52 52 52 52 52 µA
IEREFSTEN4MHz External 4 MHz crystal clock adder.
Measured by entering STOP or VLPS
mode with the crystal enabled.
206 228 237 245 251 258 uA
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General
14 Kinetis K22F 128KB Flash, Rev. 7, 08/2016
NXP Semiconductors
Table 7. Low power mode peripheral adders—typical value (continued)
Symbol Description Temperature (°C) Unit
-40 25 50 70 85 105
IEREFSTEN32KHz External 32 kHz crystal clock adder by
means of the OSC0_CR[EREFSTEN
and EREFSTEN] bits. Measured by
entering all modes with the crystal
enabled.
VLLS1
VLLS3
LLS
VLPS
STOP
440
440
490
510
510
490
490
490
560
560
540
540
540
560
560
560
560
560
560
560
570
570
570
610
610
580
580
680
680
680
nA
I48MIRC 48 Mhz internal reference clock 350 350 350 350 350 350 µA
ICMP CMP peripheral adder measured by
placing the device in VLLS1 mode with
CMP enabled using the 6-bit DAC and a
single external input for compare.
Includes 6-bit DAC power consumption.
22 22 22 22 22 22 µA
IRTC RTC peripheral adder measured by
placing the device in VLLS1 mode with
external 32 kHz crystal enabled by
means of the RTC_CR[OSCE] bit and
the RTC ALARM set for 1 minute.
Includes ERCLK32K (32 kHz external
crystal) power consumption.
432 357 388 475 532 810 nA
IUART UART peripheral adder measured by
placing the device in STOP or VLPS
mode with selected clock source waiting
for RX data at 115200 baud rate.
Includes selected clock source power
consumption.
MCGIRCLK (4 MHz internal reference
clock)
>OSCERCLK (4 MHz external crystal)
66
214
66
237
66
246
66
254
66
260
66
268
µA
IBG Bandgap adder when BGEN bit is set
and device is placed in VLPx, LLS, or
VLLSx mode.
45 45 45 45 45 45 µA
IADC ADC peripheral adder combining the
measured values at VDD and VDDA by
placing the device in STOP or VLPS
mode. ADC is configured for low power
mode using the internal clock and
continuous conversions.
42 42 42 42 42 42 µA
General
Kinetis K22F 128KB Flash, Rev. 7, 08/2016 15
NXP Semiconductors
2.2.5.1 Diagram: Typical IDD_RUN operating behavior
The following data was measured under these conditions:
• MCG in FBE mode for 50 MHz and lower frequencies. MCG in FEE mode at
frequencies between 50 MHz and 100MHz.
• No GPIOs toggled
• Code execution from flash with cache enabled
• For the ALLOFF curve, all peripheral clocks are disabled except FTFA
Figure 3. Run mode supply current vs. core frequency
General
16 Kinetis K22F 128KB Flash, Rev. 7, 08/2016
NXP Semiconductors
Figure 4. VLPR mode supply current vs. core frequency
2.2.6 EMC radiated emissions operating behaviors
Table 8. EMC radiated emissions operating behaviors for 64 LQFP package
Parame
ter
Conditions Clocks Frequency range Level
(Typ.)
Unit Notes
VEME Device configuration,
test conditions and EM
testing per standard IEC
61967-2.
Supply voltages:
Temp = 25°C
FSYS = 100 MHz
FBUS = 50 MHz
External crystal = 10 MHz
150 kHz–50 MHz 13 dBuV 1, 2, 3
50 MHz–150 MHz 24
150 MHz–500 MHz 23
500 MHz–1000 MHz 7
IEC level L 4
1. Measurements were made per IEC 61967-2 while the device was running typical application code.
2. Measurements were performed on the 64LQFP device, MK22FN128VLH10 .
3. The reported emission level is the value of the maximum measured emission, rounded up to the next whole number,
from among the measured orientations in each frequency range.
4. IEC Level Maximums: M ≤ 18dBmV, L ≤ 24dBmV, K ≤ 30dBmV, I ≤ 36dBmV, H ≤ 42dBmV .
General
Kinetis K22F 128KB Flash, Rev. 7, 08/2016 17
NXP Semiconductors
2.2.7 Designing with radiated emissions in mind
To find application notes that provide guidance on designing your system to minimize
interference from radiated emissions:
• Go to nxp.com
• Perform a keyword search for “EMC design.”
2.2.8 Capacitance attributes
Table 9. Capacitance attributes
Symbol Description Min. Max. Unit
CIN_A Input capacitance: analog pins — 7 pF
CIN_D Input capacitance: digital pins — 7 pF
2.3 Switching specifications
2.3.1 Device clock specifications
Table 10. Device clock specifications
Symbol Description Min. Max. Unit Notes
High Speed run mode
fSYS System and core clock — 100 MHz
fBUS Bus clock — 50 MHz
Normal run mode (and High Speed run mode unless otherwise specified above)
fSYS System and core clock — 72 MHz
fSYS_USB System and core clock when Full Speed USB in
operation
20 — MHz
fBUS Bus clock — 50 MHz
fFLASH Flash clock — 25 MHz
fLPTMR LPTMR clock — 25 MHz
VLPR mode1
fSYS System and core clock — 4 MHz
fBUS Bus clock — 4 MHz
fFLASH Flash clock — 1 MHz
fERCLK External reference clock — 16 MHz
Table continues on the next page...
General
18 Kinetis K22F 128KB Flash, Rev. 7, 08/2016
NXP Semiconductors
Table 10. Device clock specifications (continued)
Symbol Description Min. Max. Unit Notes
fLPTMR_pin LPTMR clock — 25 MHz
fLPTMR_ERCLK LPTMR external reference clock — 16 MHz
fI2S_MCLK I2S master clock — 12.5 MHz
fI2S_BCLK I2S bit clock — 4 MHz
1. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for
any other module.
2.3.2 General switching specifications
These general purpose specifications apply to all signals configured for GPIO, UART,
and timers.
Table 11. General switching specifications
Symbol Description Min. Max. Unit Notes
GPIO pin interrupt pulse width (digital glitch filter
disabled) — Synchronous path
1.5 — Bus clock
cycles
1, 2
External RESET and NMI pin interrupt pulse width —
Asynchronous path
100 — ns 3
GPIO pin interrupt pulse width (digital glitch filter
disabled, passive filter disabled) — Asynchronous
path
50 — ns 4
Mode select (EZP_CS) hold time after reset
deassertion
2 — Bus clock
cycles
Port rise and fall time
• Slew disabled
• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V
• Slew enabled
• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V
—
—
—
—
10
5
30
16
ns
ns
ns
ns
5
1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses
may or may not be recognized. In Stop, VLPS, LLS, and VLLSx modes, the synchronizer is bypassed so shorter
pulses can be recognized in that case.
2. The greater of synchronous and asynchronous timing must be met.
3. These pins have a passive filter enabled on the inputs. This is the shortest pulse width that is guaranteed to be
recognized.
4. These pins do not have a passive filter on the inputs. This is the shortest pulse width that is guaranteed to be
recognized.
5. 25 pF load
General
Kinetis K22F 128KB Flash, Rev. 7, 08/2016 19
NXP Semiconductors
2.4 Thermal specifications
2.4.1 Thermal operating requirements
Table 12. Thermal operating requirements
Symbol Description Min. Max. Unit Notes
TJDie junction temperature –40 125 °C
TAAmbient temperature –40 105 °C 1
1. Maximum TA can be exceeded only if the user ensures that TJ does not exceed maximum TJ. The simplest method to
determine TJ is: TJ = TA + RΘJA × chip power dissipation.
2.4.2 Thermal attributes
Board
type Symbol Descripti
on 121
XFBGA 100 LQFP 64 LQFP 64
MAPBGA Unit Notes
Single-layer
(1s)
RθJA Thermal
resistance,
junction to
ambient
(natural
convection)
46.6 63 69 53.8 °C/W 1
Four-layer
(2s2p)
RθJA Thermal
resistance,
junction to
ambient
(natural
convection)
39.3 50 51 46.0 °C/W 2
Single-layer
(1s)
RθJMA Thermal
resistance,
junction to
ambient
(200 ft./min.
air speed)
39.0 53 57 45.8 °C/W 3
Four-layer
(2s2p)
RθJMA Thermal
resistance,
junction to
ambient
(200 ft./min.
air speed)
35.3 44 44 41.0 °C/W 3
— RθJB Thermal
resistance,
junction to
board
36.7 36 33 43.4 °C/W 4
Table continues on the next page...
General
20 Kinetis K22F 128KB Flash, Rev. 7, 08/2016
NXP Semiconductors
Board
type Symbol Descripti
on 121
XFBGA 100 LQFP 64 LQFP 64
MAPBGA Unit Notes
— RθJC Thermal
resistance,
junction to
case
11.5 18 18 25.7 °C/W 5
—ΨJT Thermal
characteriz
ation
parameter,
junction to
package
top outside
center
(natural
convection)
0.9 3 3 0.4 °C/W 6
1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air)with the single layer board horizontal. Board meets JESD51-9 specification.
2. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air).
3. Determined according to JEDEC Standard JESD51-6, Integrated Circuits Thermal Test Method Environmental
Conditions—Forced Convection (Moving Air) with the board horizontal.
4. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental
Conditions—Junction-to-Board.
5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883
Method 1012.1).
6. Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2.
3 Peripheral operating requirements and behaviors
3.1 Core modules
3.1.1 SWD electricals
Table 13. SWD full voltage range electricals
Symbol Description Min. Max. Unit
Operating voltage 1.71 3.6 V
S1 SWD_CLK frequency of operation
• Serial wire debug
0
33
MHz
S2 SWD_CLK cycle period 1/S1 — ns
S3 SWD_CLK clock pulse width
• Serial wire debug
15
—
ns
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Peripheral operating requirements and behaviors
Kinetis K22F 128KB Flash, Rev. 7, 08/2016 21
NXP Semiconductors
Table 13. SWD full voltage range electricals (continued)
Symbol Description Min. Max. Unit
S4 SWD_CLK rise and fall times — 3 ns
S9 SWD_DIO input data setup time to SWD_CLK rise 8 — ns
S10 SWD_DIO input data hold time after SWD_CLK rise 1.4 — ns
S11 SWD_CLK high to SWD_DIO data valid — 25 ns
S12 SWD_CLK high to SWD_DIO high-Z 5 — ns
S2
S3 S3
S4 S4
SWD_CLK (input)
Figure 5. Serial wire clock input timing
S11
S12
S11
S9 S10
Input data valid
Output data valid
Output data valid
SWD_CLK
SWD_DIO
SWD_DIO
SWD_DIO
SWD_DIO
Figure 6. Serial wire data timing
Peripheral operating requirements and behaviors
22 Kinetis K22F 128KB Flash, Rev. 7, 08/2016
NXP Semiconductors
3.1.2 JTAG electricals
Table 14. JTAG limited voltage range electricals
Symbol Description Min. Max. Unit
Operating voltage 2.7 3.6 V
J1 TCLK frequency of operation
• Boundary Scan
• JTAG and CJTAG
0
0
10
20
MHz
J2 TCLK cycle period 1/J1 — ns
J3 TCLK clock pulse width
• Boundary Scan
• JTAG and CJTAG
50
25
—
—
ns
ns
J4 TCLK rise and fall times — 3 ns
J5 Boundary scan input data setup time to TCLK rise 20 — ns
J6 Boundary scan input data hold time after TCLK rise 1 — ns
J7 TCLK low to boundary scan output data valid — 25 ns
J8 TCLK low to boundary scan output high-Z — 25 ns
J9 TMS, TDI input data setup time to TCLK rise 8 — ns
J10 TMS, TDI input data hold time after TCLK rise 1 — ns
J11 TCLK low to TDO data valid — 19 ns
J12 TCLK low to TDO high-Z — 19 ns
J13 TRST assert time 100 — ns
J14 TRST setup time (negation) to TCLK high 8 — ns
Table 15. JTAG full voltage range electricals
Symbol Description Min. Max. Unit
Operating voltage 1.71 3.6 V
J1 TCLK frequency of operation
• Boundary Scan
• JTAG and CJTAG
0
0
10
15
MHz
J2 TCLK cycle period 1/J1 — ns
J3 TCLK clock pulse width
• Boundary Scan
• JTAG and CJTAG
50
33
—
—
ns
ns
J4 TCLK rise and fall times — 3 ns
J5 Boundary scan input data setup time to TCLK rise 20 — ns
J6 Boundary scan input data hold time after TCLK rise 1.4 — ns
J7 TCLK low to boundary scan output data valid — 27 ns
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Table 15. JTAG full voltage range electricals (continued)
Symbol Description Min. Max. Unit
J8 TCLK low to boundary scan output high-Z — 27 ns
J9 TMS, TDI input data setup time to TCLK rise 8 — ns
J10 TMS, TDI input data hold time after TCLK rise 1.4 — ns
J11 TCLK low to TDO data valid — 26.2 ns
J12 TCLK low to TDO high-Z — 26.2 ns
J13 TRST assert time 100 — ns
J14 TRST setup time (negation) to TCLK high 8 — ns
J2
J3 J3
J4 J4
TCLK (input)
Figure 7. Test clock input timing
J7
J8
J7
J5 J6
Input data valid
Output data valid
Output data valid
TCLK
Data inputs
Data outputs
Data outputs
Data outputs
Figure 8. Boundary scan (JTAG) timing
Peripheral operating requirements and behaviors
24 Kinetis K22F 128KB Flash, Rev. 7, 08/2016
NXP Semiconductors
J11
J12
J11
J9 J10
Input data valid
Output data valid
Output data valid
TCLK
TDI/TMS
TDO
TDO
TDO
Figure 9. Test Access Port timing
J14
J13
TCLK
TRST
Figure 10. TRST timing
3.2 System modules
There are no specifications necessary for the device's system modules.
3.3 Clock modules
Peripheral operating requirements and behaviors
Kinetis K22F 128KB Flash, Rev. 7, 08/2016 25
NXP Semiconductors
3.3.1 MCG specifications
Table 16. MCG specifications
Symbol Description Min. Typ. Max. Unit Notes
fints_ft Internal reference frequency (slow clock) —
factory trimmed at nominal VDD and 25 °C
— 32.768 — kHz
Δfints_t Total deviation of internal reference frequency
(slow clock) over voltage and temperature
— +0.5/-0.7 ± 2 %
fints_t Internal reference frequency (slow clock) —
user trimmed
31.25 — 39.0625 kHz
Δfdco_res_t Resolution of trimmed average DCO output
frequency at fixed voltage and temperature —
using SCTRIM and SCFTRIM
— ± 0.3 ± 0.6 %fdco 1
Δfdco_t Total deviation of trimmed average DCO output
frequency over voltage and temperature
— +0.5/-0.7 ± 2 %fdco 1, 2
Δfdco_t Total deviation of trimmed average DCO output
frequency over fixed voltage and temperature
range of 0–70°C
— ± 0.3 ± 1.5 %fdco 1
fintf_ft Internal reference frequency (fast clock) —
factory trimmed at nominal VDD and 25°C
— 4 — MHz
Δfintf_ft Frequency deviation of internal reference clock
(fast clock) over temperature and voltage —
factory trimmed at nominal VDD and 25 °C
— +1/-2 ± 5 %fintf_ft
fintf_t Internal reference frequency (fast clock) — user
trimmed at nominal VDD and 25 °C
3 — 5 MHz
floc_low Loss of external clock minimum frequency —
RANGE = 00
(3/5) x
fints_t
— — kHz
floc_high Loss of external clock minimum frequency —
RANGE = 01, 10, or 11
(16/5) x
fints_t
— — kHz
FLL
ffll_ref FLL reference frequency range 31.25 — 39.0625 kHz
fdco DCO output
frequency range
Low range (DRS=00)
640 × ffll_ref
20 20.97 25 MHz 3, 4
Mid range (DRS=01)
1280 × ffll_ref
40 41.94 50 MHz
Mid-high range (DRS=10)
1920 × ffll_ref
60 62.91 75 MHz
High range (DRS=11)
2560 × ffll_ref
80 83.89 100 MHz
fdco_t_DMX3
2
DCO output
frequency
Low range (DRS=00)
732 × ffll_ref
— 23.99 — MHz 5, 6
Mid range (DRS=01)
1464 × ffll_ref
— 47.97 — MHz
Mid-high range (DRS=10) — 71.99 — MHz
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Peripheral operating requirements and behaviors
26 Kinetis K22F 128KB Flash, Rev. 7, 08/2016
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Table 16. MCG specifications (continued)
Symbol Description Min. Typ. Max. Unit Notes
2197 × ffll_ref
High range (DRS=11)
2929 × ffll_ref
— 95.98 — MHz
Jcyc_fll FLL period jitter
• fVCO = 48 MHz
• fVCO = 98 MHz
—
—
—
180
150
—
—
ps
tfll_acquire FLL target frequency acquisition time — — 1 ms 7
1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock
mode).
2. 2.0 V <= VDD <= 3.6 V.
3. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0.
4. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency
deviation (Δfdco_t) over voltage and temperature should be considered.
5. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1.
6. The resulting clock frequency must not exceed the maximum specified clock frequency of the device.
7. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,
DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE,
FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.
3.3.2 IRC48M specifications
Table 17. IRC48M specifications
Symbol Description Min. Typ. Max. Unit Notes
VDD Supply voltage 1.71 — 3.6 V
IDD48M Supply current — 400 500 μA
firc48m Internal reference frequency — 48 — MHz
Δfirc48m_ol_hv Open loop total deviation of IRC48M frequency at
high voltage (VDD=1.89V-3.6V) over 0°C to 70°C
—
Regulator enable
(USB_CLK_RECOVER_IRC_EN[REG_EN]=1)
— ± 0.2 ± 0.5 %firc48m 1
Δfirc48m_ol_hv Open loop total deviation of IRC48M frequency at
high voltage (VDD=1.89V-3.6V) over full
temperature
Regulator enable
(USB_CLK_RECOVER_IRC_EN[REG_EN]=1)
— ± 0.4 ± 1.0 %firc48m 1
Δfirc48m_ol_lv Open loop total deviation of IRC48M frequency at
low voltage (VDD=1.71V-1.89V) over full
temperature
1
Regulator disable
(USB_CLK_RECOVER_IRC_EN[REG_EN]=0)
— ± 0.4 ± 1.0 %firc48m
Regulator enable
(USB_CLK_RECOVER_IRC_EN[REG_EN]=1)
— ± 0.5 ± 1.5
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Peripheral operating requirements and behaviors
Kinetis K22F 128KB Flash, Rev. 7, 08/2016 27
NXP Semiconductors
Table 17. IRC48M specifications (continued)
Symbol Description Min. Typ. Max. Unit Notes
Δfirc48m_cl Closed loop total deviation of IRC48M frequency
over voltage and temperature
— — ± 0.1 %fhost 2
Jcyc_irc48m Period Jitter (RMS) — 35 150 ps
tirc48mst Startup time — 2 3 μs 3
1. The maximum value represents characterized results equivalent to the mean plus or minus three times the standard
deviation (mean ± 3 sigma).
2. Closed loop operation of the IRC48M is only feasible for USB device operation; it is not usable for USB host operation. It
is enabled by configuring for USB Device, selecting IRC48M as USB clock source, and enabling the clock recover
function (USB_CLK_RECOVER_IRC_CTRL[CLOCK_RECOVER_EN]=1, USB_CLK_RECOVER_IRC_EN[IRC_EN]=1).
3. IRC48M startup time is defined as the time between clock enablement and clock availability for system use. Enable the
clock by one of the following settings:
• USB_CLK_RECOVER_IRC_EN[IRC_EN]=1 or
• MCG operating in an external clocking mode and MCG_C7[OSCSEL]=10 or MCG_C5[PLLCLKEN0]=1, or
• SIM_SOPT2[PLLFLLSEL]=11
3.3.3 Oscillator electrical specifications
3.3.3.1 Oscillator DC electrical specifications
Table 18. Oscillator DC electrical specifications
Symbol Description Min. Typ. Max. Unit Notes
VDD Supply voltage 1.71 — 3.6 V
IDDOSC Supply current — low-power mode (HGO=0)
• 32 kHz
• 4 MHz
• 8 MHz (RANGE=01)
• 16 MHz
• 24 MHz
• 32 MHz
—
—
—
—
—
—
500
200
300
950
1.2
1.5
—
—
—
—
—
—
nA
μA
μA
μA
mA
mA
1
IDDOSC Supply current — high-gain mode (HGO=1)
• 32 kHz
• 4 MHz
• 8 MHz (RANGE=01)
• 16 MHz
• 24 MHz
• 32 MHz
—
—
—
—
—
—
25
400
500
2.5
3
4
—
—
—
—
—
—
μA
μA
μA
mA
mA
mA
1
CxEXTAL load capacitance — — — 2, 3
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Peripheral operating requirements and behaviors
28 Kinetis K22F 128KB Flash, Rev. 7, 08/2016
NXP Semiconductors
Table 18. Oscillator DC electrical specifications (continued)
Symbol Description Min. Typ. Max. Unit Notes
CyXTAL load capacitance — — — 2, 3
RFFeedback resistor — low-frequency, low-power
mode (HGO=0)
— — — MΩ 2, 4
Feedback resistor — low-frequency, high-gain
mode (HGO=1)
— 10 — MΩ
Feedback resistor — high-frequency, low-power
mode (HGO=0)
— — — MΩ
Feedback resistor — high-frequency, high-gain
mode (HGO=1)
— 1 — MΩ
RSSeries resistor — low-frequency, low-power
mode (HGO=0)
— — — kΩ
Series resistor — low-frequency, high-gain
mode (HGO=1)
— 200 — kΩ
Series resistor — high-frequency, low-power
mode (HGO=0)
— — — kΩ
Series resistor — high-frequency, high-gain
mode (HGO=1)
—
0
—
kΩ
Vpp5Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, low-power mode
(HGO=0)
— 0.6 — V
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, high-gain mode
(HGO=1)
— VDD — V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, low-power mode
(HGO=0)
— 0.6 — V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, high-gain mode
(HGO=1)
— VDD — V
1. VDD=3.3 V, Temperature =25 °C
2. See crystal or resonator manufacturer's recommendation
3. Cx and Cy can be provided by using either integrated capacitors or external components.
4. When low-power mode is selected, RF is integrated and must not be attached externally.
5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to
any other device.
3.3.3.2 Oscillator frequency specifications
Table 19. Oscillator frequency specifications
Symbol Description Min. Typ. Max. Unit Notes
fosc_lo Oscillator crystal or resonator frequency — low-
frequency mode (MCG_C2[RANGE]=00)
32 — 40 kHz
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Table 19. Oscillator frequency specifications (continued)
Symbol Description Min. Typ. Max. Unit Notes
fosc_hi_1 Oscillator crystal or resonator frequency —
high-frequency mode (low range)
(MCG_C2[RANGE]=01)
3 — 8 MHz
fosc_hi_2 Oscillator crystal or resonator frequency —
high frequency mode (high range)
(MCG_C2[RANGE]=1x)
8 — 32 MHz
fec_extal Input clock frequency (external clock mode) — — 50 MHz 1, 2
tdc_extal Input clock duty cycle (external clock mode) 40 50 60 %
tcst Crystal startup time — 32 kHz low-frequency,
low-power mode (HGO=0)
— 750 — ms 3, 4
Crystal startup time — 32 kHz low-frequency,
high-gain mode (HGO=1)
— 250 — ms
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), low-power mode
(HGO=0)
— 0.6 — ms
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), high-gain mode
(HGO=1)
— 1 — ms
1. Other frequency limits may apply when external clock is being used as a reference for the FLL
2. When transitioning from FEI or FBI to FBE mode, restrict the frequency of the input clock so that, when it is divided by
FRDIV, it remains within the limits of the DCO input clock frequency.
3. Proper PC board layout procedures must be followed to achieve specifications.
4. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S
register being set.
3.3.4 32 kHz oscillator electrical characteristics
3.3.4.1 32 kHz oscillator DC electrical specifications
Table 20. 32kHz oscillator DC electrical specifications
Symbol Description Min. Typ. Max. Unit
VBAT Supply voltage 1.71 — 3.6 V
RFInternal feedback resistor — 100 — MΩ
Cpara Parasitical capacitance of EXTAL32 and
XTAL32
— 5 7 pF
Vpp1Peak-to-peak amplitude of oscillation — 0.6 — V
1. When a crystal is being used with the 32 kHz oscillator, the EXTAL32 and XTAL32 pins should only be connected to
required oscillator components and must not be connected to any other devices.
Peripheral operating requirements and behaviors
30 Kinetis K22F 128KB Flash, Rev. 7, 08/2016
NXP Semiconductors
3.3.4.2 32 kHz oscillator frequency specifications
Table 21. 32 kHz oscillator frequency specifications
Symbol Description Min. Typ. Max. Unit Notes
fosc_lo Oscillator crystal — 32.768 — kHz
tstart Crystal start-up time — 1000 — ms 1
fec_extal32 Externally provided input clock frequency — 32.768 — kHz 2
vec_extal32 Externally provided input clock amplitude 700 — VBAT mV 2, 3
1. Proper PC board layout procedures must be followed to achieve specifications.
2. This specification is for an externally supplied clock driven to EXTAL32 and does not apply to any other clock input.
The oscillator remains enabled and XTAL32 must be left unconnected.
3. The parameter specified is a peak-to-peak value and VIH and VIL specifications do not apply. The voltage of the
applied clock must be within the range of VSS to VBAT.
3.4 Memories and memory interfaces
3.4.1 Flash electrical specifications
This section describes the electrical characteristics of the flash memory module.
3.4.1.1 Flash timing specifications — program and erase
The following specifications represent the amount of time the internal charge pumps
are active and do not include command overhead.
Table 22. NVM program/erase timing specifications
Symbol Description Min. Typ. Max. Unit Notes
thvpgm4 Longword Program high-voltage time — 7.5 18 μs —
thversscr Sector Erase high-voltage time — 13 113 ms 1
thversall Erase All high-voltage time — 104 904 ms 1
1. Maximum time based on expectations at cycling end-of-life.
3.4.1.2 Flash timing specifications — commands
Table 23. Flash command timing specifications
Symbol Description Min. Typ. Max. Unit Notes
trd1sec2k Read 1s Section execution time (flash sector) — — 60 μs 1
tpgmchk Program Check execution time — — 45 μs 1
Table continues on the next page...
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NXP Semiconductors
Table 23. Flash command timing specifications (continued)
Symbol Description Min. Typ. Max. Unit Notes
trdrsrc Read Resource execution time — — 30 μs 1
tpgm4 Program Longword execution time — 65 145 μs —
tersscr Erase Flash Sector execution time — 14 114 ms 2
trd1all Read 1s All Blocks execution time — — 0.9 ms 1
trdonce Read Once execution time — — 30 μs 1
tpgmonce Program Once execution time — 100 — μs —
tersall Erase All Blocks execution time — 140 1150 ms 2
tvfykey Verify Backdoor Access Key execution time — — 30 μs 1
1. Assumes 25 MHz flash clock frequency.
2. Maximum times for erase parameters based on expectations at cycling end-of-life.
3.4.1.3 Flash high voltage current behaviors
Table 24. Flash high voltage current behaviors
Symbol Description Min. Typ. Max. Unit
IDD_PGM Average current adder during high voltage
flash programming operation
— 2.5 6.0 mA
IDD_ERS Average current adder during high voltage
flash erase operation
— 1.5 4.0 mA
3.4.1.4 Reliability specifications
Table 25. NVM reliability specifications
Symbol Description Min. Typ.1Max. Unit Notes
Program Flash
tnvmretp10k Data retention after up to 10 K cycles 5 50 — years —
tnvmretp1k Data retention after up to 1 K cycles 20 100 — years —
nnvmcycp Cycling endurance 10 K 50 K — cycles 2
1. Typical data retention values are based on measured response accelerated at high temperature and derated to a
constant 25 °C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in
Engineering Bulletin EB619.
2. Cycling endurance represents number of program/erase cycles at –40 °C ≤ Tj ≤ 125 °C.
Peripheral operating requirements and behaviors
32 Kinetis K22F 128KB Flash, Rev. 7, 08/2016
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3.4.2 EzPort switching specifications
Table 26. EzPort switching specifications
Num Description Min. Max. Unit
Operating voltage 1.71 3.6 V
EP1 EZP_CK frequency of operation (all commands except
READ)
— fSYS/2 MHz
EP1a EZP_CK frequency of operation (READ command) — fSYS/8 MHz
EP2 EZP_CS negation to next EZP_CS assertion 2 x tEZP_CK — ns
EP3 EZP_CS input valid to EZP_CK high (setup) 5 — ns
EP4 EZP_CK high to EZP_CS input invalid (hold) 5 — ns
EP5 EZP_D input valid to EZP_CK high (setup) 2 — ns
EP6 EZP_CK high to EZP_D input invalid (hold) 5 — ns
EP7 EZP_CK low to EZP_Q output valid — 25 ns
EP8 EZP_CK low to EZP_Q output invalid (hold) 0 — ns
EP9 EZP_CS negation to EZP_Q tri-state — 12 ns
EP2
EP3 EP4
EP5 EP6
EP7 EP8
EP9
EZP_CK
EZP_CS
EZP_Q (output)
EZP_D (input)
Figure 11. EzPort Timing Diagram
3.5 Security and integrity modules
There are no specifications necessary for the device's security and integrity modules.
Peripheral operating requirements and behaviors
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3.6 Analog
3.6.1 ADC electrical specifications
The 16-bit accuracy specifications listed in Table 27 and Table 28 are achievable on the
differential pins ADCx_DPx, ADCx_DMx.
All other ADC channels meet the 13-bit differential/12-bit single-ended accuracy
specifications.
3.6.1.1 16-bit ADC operating conditions
Table 27. 16-bit ADC operating conditions
Symbol Description Conditions Min. Typ.1Max. Unit Notes
VDDA Supply voltage Absolute 1.71 — 3.6 V
ΔVDDA Supply voltage Delta to VDD (VDD – VDDA) -100 0 +100 mV 2
ΔVSSA Ground voltage Delta to VSS (VSS – VSSA) -100 0 +100 mV 2
VREFH ADC reference
voltage high
1.13 VDDA VDDA V
VREFL ADC reference
voltage low
VSSA VSSA VSSA V
VADIN Input voltage • 16-bit differential mode
• All other modes
VREFL
VREFL
—
—
31/32 *
VREFH
VREFH
V
CADIN Input
capacitance
• 16-bit mode
• 8-bit / 10-bit / 12-bit
modes
—
—
8
4
10
5
pF
RADIN Input series
resistance
— 2 5 kΩ
RAS Analog source
resistance
(external)
13-bit / 12-bit modes
fADCK < 4 MHz
—
—
5
kΩ
3
fADCK ADC conversion
clock frequency
≤ 13-bit mode 1.0 — 24.0 MHz 4
fADCK ADC conversion
clock frequency
16-bit mode 2.0 — 12.0 MHz 4
Crate ADC conversion
rate
≤ 13-bit modes
No ADC hardware averaging
Continuous conversions
enabled, subsequent
conversion time
20
—
1200
Ksps
5
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34 Kinetis K22F 128KB Flash, Rev. 7, 08/2016
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Table 27. 16-bit ADC operating conditions (continued)
Symbol Description Conditions Min. Typ.1Max. Unit Notes
Crate ADC conversion
rate
16-bit mode
No ADC hardware averaging
Continuous conversions
enabled, subsequent
conversion time
37
—
461
Ksps
5
1. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for
reference only, and are not tested in production.
2. DC potential difference.
3. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as
possible. The results in this data sheet were derived from a system that had < 8 Ω analog source resistance. The
RAS/CAS time constant should be kept to < 1 ns.
4. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear.
5. For guidelines and examples of conversion rate calculation, download the ADC calculator tool.
RAS
VAS CAS
ZAS
VADIN
ZADIN
RADIN
RADIN
RADIN
RADIN
CADIN
Pad
leakage
due to
input
protection
INPUT PIN
INPUT PIN
INPUT PIN
SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
ADC SAR
ENGINE
Figure 12. ADC input impedance equivalency diagram
3.6.1.2 16-bit ADC electrical characteristics
Peripheral operating requirements and behaviors
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NXP Semiconductors
Table 28. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA)
Symbol Description Conditions1Min. Typ.2Max. Unit Notes
IDDA_ADC Supply current 0.215 — 1.7 mA 3
fADACK
ADC asynchronous
clock source
• ADLPC = 1, ADHSC = 0
• ADLPC = 1, ADHSC = 1
• ADLPC = 0, ADHSC = 0
• ADLPC = 0, ADHSC = 1
1.2
2.4
3.0
4.4
2.4
4.0
5.2
6.2
3.9
6.1
7.3
9.5
MHz
MHz
MHz
MHz
tADACK = 1/
fADACK
Sample Time See Reference Manual chapter for sample times
TUE Total unadjusted
error
• 12-bit modes
• <12-bit modes
—
—
±4
±1.4
±6.8
±2.1
LSB45
DNL Differential non-
linearity
• 12-bit modes
• <12-bit modes
—
—
±0.7
±0.2
–1.1 to
+1.9
–0.3 to
0.5
LSB45
INL Integral non-linearity • 12-bit modes
• <12-bit modes
—
—
±1.0
±0.5
–2.7 to
+1.9
–0.7 to
+0.5
LSB45
EFS Full-scale error • 12-bit modes
• <12-bit modes
—
—
–4
–1.4
–5.4
–1.8
LSB4VADIN = VDDA5
EQQuantization error • 16-bit modes
• ≤13-bit modes
—
—
–1 to 0
—
—
±0.5
LSB4
ENOB Effective number of
bits
16-bit differential mode
• Avg = 32
• Avg = 4
16-bit single-ended mode
• Avg = 32
• Avg = 4
12.8
11.9
12.2
11.4
14.5
13.8
13.9
13.1
—
—
—
—
bits
bits
bits
bits
6
SINAD Signal-to-noise plus
distortion
See ENOB 6.02 × ENOB + 1.76 dB
THD Total harmonic
distortion
16-bit differential mode
• Avg = 32
16-bit single-ended mode
• Avg = 32
—
—
-94
-85
—
—
dB
dB
7
SFDR Spurious free
dynamic range
16-bit differential mode
• Avg = 32 82 95 —
—
dB
dB
7
Table continues on the next page...
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36 Kinetis K22F 128KB Flash, Rev. 7, 08/2016
NXP Semiconductors
Table 28. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Symbol Description Conditions1Min. Typ.2Max. Unit Notes
16-bit single-ended mode
• Avg = 32
78 90
EIL Input leakage error IIn × RAS mV IIn = leakage
current
(refer to the
MCU's voltage
and current
operating
ratings)
Temp sensor slope Across the full temperature
range of the device
1.55 1.62 1.69 mV/°C 8
VTEMP25 Temp sensor voltage 25 °C 706 716 726 mV 8
1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA
2. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low
power). For lowest power operation, ADC_CFG1[ADLPC] must be set, the ADC_CFG2[ADHSC] bit must be clear with
1 MHz ADC conversion clock speed.
4. 1 LSB = (VREFH - VREFL)/2N
5. ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11)
6. Input data is 100 Hz sine wave. ADC conversion clock < 12 MHz.
7. Input data is 1 kHz sine wave. ADC conversion clock < 12 MHz.
8. ADC conversion clock < 3 MHz
Typical ADC 16-bit Differential ENOB vs ADC Clock
100Hz, 90% FS Sine Input
ENOB
ADC Clock Frequency (MHz)
15.00
14.70
14.40
14.10
13.80
13.50
13.20
12.90
12.60
12.30
12.00
1 2 3 4 5 6 7 8 9 10 1211
Hardware Averaging Disabled
Averaging of 4 samples
Averaging of 8 samples
Averaging of 32 samples
Figure 13. Typical ENOB vs. ADC_CLK for 16-bit differential mode
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Typical ADC 16-bit Single-Ended ENOB vs ADC Clock
100Hz, 90% FS Sine Input
ENOB
ADC Clock Frequency (MHz)
14.00
13.75
13.25
13.00
12.75
12.50
12.00
11.75
11.50
11.25
11.00
1 2 3 4 5 6 7 8 9 10 1211
Averaging of 4 samples
Averaging of 32 samples
13.50
12.25
Figure 14. Typical ENOB vs. ADC_CLK for 16-bit single-ended mode
3.6.2 CMP and 6-bit DAC electrical specifications
Table 29. Comparator and 6-bit DAC electrical specifications
Symbol Description Min. Typ. Max. Unit
VDD Supply voltage 1.71 — 3.6 V
IDDHS Supply current, High-speed mode (EN=1, PMODE=1) — — 200 μA
IDDLS Supply current, low-speed mode (EN=1, PMODE=0) — — 20 μA
VAIN Analog input voltage VSS – 0.3 — VDD V
VAIO Analog input offset voltage — — 20 mV
VHAnalog comparator hysteresis1
• CR0[HYSTCTR] = 00
• CR0[HYSTCTR] = 01
• CR0[HYSTCTR] = 10
• CR0[HYSTCTR] = 11
—
—
—
—
5
10
20
30
—
—
—
—
mV
mV
mV
mV
VCMPOh Output high VDD – 0.5 — — V
VCMPOl Output low — — 0.5 V
tDHS Propagation delay, high-speed mode (EN=1, PMODE=1) 20 50 200 ns
tDLS Propagation delay, low-speed mode (EN=1, PMODE=0) 80 250 600 ns
Analog comparator initialization delay2— — 40 μs
IDAC6b 6-bit DAC current adder (enabled) — 7 — μA
INL 6-bit DAC integral non-linearity –0.5 — 0.5 LSB3
DNL 6-bit DAC differential non-linearity –0.3 — 0.3 LSB
Peripheral operating requirements and behaviors
38 Kinetis K22F 128KB Flash, Rev. 7, 08/2016
NXP Semiconductors
1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD–0.6 V.
2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to
CMP_DACCR[DACEN], CMP_DACCR[VRSEL], CMP_DACCR[VOSEL], CMP_MUXCR[PSEL], and
CMP_MUXCR[MSEL]) and the comparator output settling to a stable level.
3. 1 LSB = Vreference/64
00
01
10
HYSTCTR
Setting
0.1
10
11
Vin level (V)
CMP Hystereris (V)
3.12.82.5
2.2
1.91.61.3
1
0.70.4
0.05
0
0.01
0.02
0.03
0.08
0.07
0.06
0.04
Figure 15. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0)
Peripheral operating requirements and behaviors
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NXP Semiconductors
00
01
10
HYSTCTR
Setting
10
11
0.1 3.12.82.5
2.2
1.91.61.3
1
0.70.4
0.1
0
0.02
0.04
0.06
0.18
0.14
0.12
0.08
0.16
Vin level (V)
CMP Hysteresis (V)
Figure 16. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1)
3.6.3 12-bit DAC electrical characteristics
3.6.3.1 12-bit DAC operating requirements
Table 30. 12-bit DAC operating requirements
Symbol Desciption Min. Max. Unit Notes
VDDA Supply voltage 1.71 3.6 V
VDACR Reference voltage 1.13 3.6 V 1
CLOutput load capacitance — 100 pF 2
ILOutput load current — 1 mA
1. The DAC reference can be selected to be VDDA or VREFH.
2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC.
Peripheral operating requirements and behaviors
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3.6.3.2 12-bit DAC operating behaviors
Table 31. 12-bit DAC operating behaviors
Symbol Description Min. Typ. Max. Unit Notes
IDDA_DACL
P
Supply current — low-power mode — — 330 μA
IDDA_DACH
P
Supply current — high-speed mode — — 1200 μA
tDACLP Full-scale settling time (0x080 to 0xF7F) —
low-power mode
— 100 200 μs 1
tDACHP Full-scale settling time (0x080 to 0xF7F) —
high-power mode
— 15 30 μs 1
tCCDACLP Code-to-code settling time (0xBF8 to
0xC08) — low-power mode and high-
speed mode
— 0.7 1 μs 1
Vdacoutl DAC output voltage range low — high-
speed mode, no load, DAC set to 0x000
— — 100 mV
Vdacouth DAC output voltage range high — high-
speed mode, no load, DAC set to 0xFFF
VDACR
−100
— VDACR mV
INL Integral non-linearity error — high speed
mode
— — ±8 LSB 2
DNL Differential non-linearity error — VDACR > 2
V
— — ±1 LSB 3
DNL Differential non-linearity error — VDACR =
VREF_OUT
— — ±1 LSB 4
VOFFSET Offset error — ±0.4 ±0.8 %FSR 5
EGGain error — ±0.1 ±0.6 %FSR 5
PSRR Power supply rejection ratio, VDDA ≥ 2.4 V 60 — 90 dB
TCO Temperature coefficient offset voltage — 3.7 — μV/C 6
TGE Temperature coefficient gain error — 0.000421 — %FSR/C
Rop Output resistance (load = 3 kΩ) — — 250 Ω
SR Slew rate -80h→ F7Fh→ 80h
• High power (SPHP)
• Low power (SPLP)
1.2
0.05
1.7
0.12
—
—
V/μs
BW 3dB bandwidth
• High power (SPHP)
• Low power (SPLP)
550
40
—
—
—
—
kHz
1. Settling within ±1 LSB
2. The INL is measured for 0 + 100 mV to VDACR −100 mV
3. The DNL is measured for 0 + 100 mV to VDACR −100 mV
4. The DNL is measured for 0 + 100 mV to VDACR −100 mV with VDDA > 2.4 V
5. Calculated by a best fit curve from VSS + 100 mV to VDACR − 100 mV
6. VDDA = 3.0 V, reference select set for VDDA (DACx_CO:DACRFS = 1), high power mode (DACx_C0:LPEN = 0), DAC
set to 0x800, temperature range is across the full range of the device
Peripheral operating requirements and behaviors
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Digital Code
DAC12 INL (LSB)
0
500 1000 1500 2000 2500 3000 3500 4000
2
4
6
8
-2
-4
-6
-8
0
Figure 17. Typical INL error vs. digital code
Peripheral operating requirements and behaviors
42 Kinetis K22F 128KB Flash, Rev. 7, 08/2016
NXP Semiconductors
Temperature °C
DAC12 Mid Level Code Voltage
25 55 85 105 125
1.499
-40
1.4985
1.498
1.4975
1.497
1.4965
1.496
Figure 18. Offset at half scale vs. temperature
3.6.4 Voltage reference electrical specifications
Table 32. VREF full-range operating requirements
Symbol Description Min. Max. Unit Notes
VDDA Supply voltage 1.71 3.6 V
TATemperature Operating temperature
range of the device
°C
CLOutput load capacitance 100 nF 1, 2
1. CL must be connected to VREF_OUT if the VREF_OUT functionality is being used for either an internal or external
reference.
2. The load capacitance should not exceed +/-25% of the nominal specified CL value over the operating temperature
range of the device.
Peripheral operating requirements and behaviors
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Table 33. VREF full-range operating behaviors
Symbol Description Min. Typ. Max. Unit Notes
Vout Voltage reference output with factory trim at
nominal VDDA and temperature=25°C
1.1920 1.1950 1.1980 V 1
Vout Voltage reference output with user trim at
nominal VDDA and temperature=25°C
1.1945 1.1950 1.1955 V 1
Vstep Voltage reference trim step — 0.5 — mV 1
Vtdrift Temperature drift (Vmax -Vmin across the full
temperature range)
— — 15 mV 1
Ibg Bandgap only current — — 80 µA
Ilp Low-power buffer current — — 360 uA 1
Ihp High-power buffer current — — 1 mA 1
ΔVLOAD Load regulation
• current = ± 1.0 mA
—
200
—
µV 1, 2
Tstup Buffer startup time — — 100 µs
Tchop_osc_st
up
Internal bandgap start-up delay with chop
oscillator enabled
— — 35 ms
Vvdrift Voltage drift (Vmax -Vmin across the full voltage
range)
— 2 — mV 1
1. See the chip's Reference Manual for the appropriate settings of the VREF Status and Control register.
2. Load regulation voltage is the difference between the VREF_OUT voltage with no load vs. voltage with defined load
Table 34. VREF limited-range operating requirements
Symbol Description Min. Max. Unit Notes
TATemperature 0 70 °C
Table 35. VREF limited-range operating behaviors
Symbol Description Min. Max. Unit Notes
Vtdrift Temperature drift (Vmax -Vmin across the limited
temperature range)
— 10 mV
3.7 Timers
See General switching specifications.
3.8 Communication interfaces
Peripheral operating requirements and behaviors
44 Kinetis K22F 128KB Flash, Rev. 7, 08/2016
NXP Semiconductors
3.8.1 USB electrical specifications
The USB electricals for the USB On-the-Go module conform to the standards
documented by the Universal Serial Bus Implementers Forum. For the most up-to-
date standards, visit usb.org.
NOTE
The MCGFLLCLK does not meet the USB jitter or
signaling rate specifications for certification.
The IRC48M meets the USB jitter and signaling rate
specifications for certification in Device mode when the
USB clock recovery mode is enabled. It does not meet the
USB signaling rate specifications for certification in Host
mode operation.
3.8.2 DSPI switching specifications (limited voltage range)
The Deserial Serial Peripheral Interface (DSPI) provides a synchronous serial bus
with master and slave operations. Many of the transfer attributes are programmable.
The tables below provide DSPI timing characteristics for classic SPI timing modes.
Refer to the SPI chapter of the Reference Manual for information on the modified
transfer formats used for communicating with slower peripheral devices.
Table 36. Master mode DSPI timing (limited voltage range)
Num Description Min. Max. Unit Notes
Operating voltage 2.7 3.6 V
Frequency of operation — 25 MHz
DS1 DSPI_SCK output cycle time 2 x tBUS — ns
DS2 DSPI_SCK output high/low time (tSCK/2) − 2 (tSCK/2) + 2 ns
DS3 DSPI_PCSn valid to DSPI_SCK delay (tBUS x 2) −
2
— ns 1
DS4 DSPI_SCK to DSPI_PCSn invalid delay (tBUS x 2) −
2
— ns 2
DS5 DSPI_SCK to DSPI_SOUT valid — 8.5 ns
DS6 DSPI_SCK to DSPI_SOUT invalid -2 — ns
DS7 DSPI_SIN to DSPI_SCK input setup 16.2 — ns
DS8 DSPI_SCK to DSPI_SIN input hold 0 — ns
1. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
Peripheral operating requirements and behaviors
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2. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
DS3 DS4
DS1
DS2
DS7 DS8
First data Last data
DS5
First data Data Last data
DS6
Data
DSPI_PCSn
DSPI_SCK
(CPOL=0)
DSPI_SIN
DSPI_SOUT
Figure 19. DSPI classic SPI timing — master mode
Table 37. Slave mode DSPI timing (limited voltage range)
Num Description Min. Max. Unit Notes
Operating voltage 2.7 3.6 V
Frequency of operation — 12.5 MHz 1
DS9 DSPI_SCK input cycle time 4 x tBUS — ns
DS10 DSPI_SCK input high/low time (tSCK/2) − 2 (tSCK/2) + 2 ns
DS11 DSPI_SCK to DSPI_SOUT valid — 21.4 ns
DS12 DSPI_SCK to DSPI_SOUT invalid 0 — ns
DS13 DSPI_SIN to DSPI_SCK input setup 2.6 — ns
DS14 DSPI_SCK to DSPI_SIN input hold 7 — ns
DS15 DSPI_SS active to DSPI_SOUT driven — 17 ns
DS16 DSPI_SS inactive to DSPI_SOUT not driven — 17 ns
1. The maximum operating frequency is measured with noncontinuous CS and SCK. When DSPI is configured with
continuous CS and SCK, the SPI clock must not be greater than 1/6 of the bus clock. For example, when the bus clock
is 60 MHz, the SPI clock must not be greater than 10 MHz.
Peripheral operating requirements and behaviors
46 Kinetis K22F 128KB Flash, Rev. 7, 08/2016
NXP Semiconductors
First data Last data
First data Data Last data
Data
DS15
DS10 DS9
DS16
DS11
DS12
DS14
DS13
DSPI_SS
DSPI_SCK
(CPOL=0)
DSPI_SOUT
DSPI_SIN
Figure 20. DSPI classic SPI timing — slave mode
3.8.3 DSPI switching specifications (full voltage range)
The Deserial Serial Peripheral Interface (DSPI) provides a synchronous serial bus
with master and slave operations. Many of the transfer attributes are programmable.
The tables below provides DSPI timing characteristics for classic SPI timing modes.
Refer to the SPI chapter of the Reference Manual for information on the modified
transfer formats used for communicating with slower peripheral devices.
Table 38. Master mode DSPI timing (full voltage range)
Num Description Min. Max. Unit Notes
Operating voltage 1.71 3.6 V 1
Frequency of operation — 12.5 MHz
DS1 DSPI_SCK output cycle time 4 x tBUS — ns
DS2 DSPI_SCK output high/low time (tSCK/2) - 4 (tSCK/2) + 4 ns
DS3 DSPI_PCSn valid to DSPI_SCK delay (tBUS x 2) −
4
— ns 2
DS4 DSPI_SCK to DSPI_PCSn invalid delay (tBUS x 2) −
4
— ns 3
DS5 DSPI_SCK to DSPI_SOUT valid — 10 ns
DS6 DSPI_SCK to DSPI_SOUT invalid -4.5 — ns
DS7 DSPI_SIN to DSPI_SCK input setup 24.6 — ns
DS8 DSPI_SCK to DSPI_SIN input hold 0 — ns
1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage
range the maximum frequency of operation is reduced.
2. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
3. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
Peripheral operating requirements and behaviors
Kinetis K22F 128KB Flash, Rev. 7, 08/2016 47
NXP Semiconductors
DS3 DS4
DS1
DS2
DS7 DS8
First data Last data
DS5
First data Data Last data
DS6
Data
DSPI_PCSn
DSPI_SCK
(CPOL=0)
DSPI_SIN
DSPI_SOUT
Figure 21. DSPI classic SPI timing — master mode
Table 39. Slave mode DSPI timing (full voltage range)
Num Description Min. Max. Unit
Operating voltage 1.71 3.6 V
Frequency of operation — 6.25 MHz
DS9 DSPI_SCK input cycle time 8 x tBUS — ns
DS10 DSPI_SCK input high/low time (tSCK/2) - 4 (tSCK/2) + 4 ns
DS11 DSPI_SCK to DSPI_SOUT valid — 29.5 ns
DS12 DSPI_SCK to DSPI_SOUT invalid 0 — ns
DS13 DSPI_SIN to DSPI_SCK input setup 3.2 — ns
DS14 DSPI_SCK to DSPI_SIN input hold 7 — ns
DS15 DSPI_SS active to DSPI_SOUT driven — 25 ns
DS16 DSPI_SS inactive to DSPI_SOUT not driven — 25 ns
First data Last data
First data Data Last data
Data
DS15
DS10 DS9
DS16
DS11
DS12
DS14
DS13
DSPI_SS
DSPI_SCK
(CPOL=0)
DSPI_SOUT
DSPI_SIN
Figure 22. DSPI classic SPI timing — slave mode
Peripheral operating requirements and behaviors
48 Kinetis K22F 128KB Flash, Rev. 7, 08/2016
NXP Semiconductors
3.8.4 Inter-Integrated Circuit Interface (I2C) timing
Table 40. I 2C timing
Characteristic Symbol Standard Mode Fast Mode Unit
Minimum Maximum Minimum Maximum
SCL Clock Frequency fSCL 0 100 0 4001kHz
Hold time (repeated) START condition.
After this period, the first clock pulse is
generated.
tHD; STA 4 — 0.6 — µs
LOW period of the SCL clock tLOW 4.7 — 1.25 — µs
HIGH period of the SCL clock tHIGH 4 — 0.6 — µs
Set-up time for a repeated START
condition
tSU; STA 4.7 — 0.6 — µs
Data hold time for I2C bus devices tHD; DAT 023.453040.92µs
Data set-up time tSU; DAT 2505— 1003, 6— ns
Rise time of SDA and SCL signals tr— 1000 20 +0.1Cb7300 ns
Fall time of SDA and SCL signals tf— 300 20 +0.1Cb6300 ns
Set-up time for STOP condition tSU; STO 4 — 0.6 — µs
Bus free time between STOP and
START condition
tBUF 4.7 — 1.3 — µs
Pulse width of spikes that must be
suppressed by the input filter
tSP N/A N/A 0 50 ns
1. The maximum SCL Clock Frequency in Fast mode with maximum bus loading can only be achieved when using the
High drive pins across the full voltage range and when using the Normal drive pins and VDD ≥ 2.7 V.
2. The master mode I2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves
acknowledge this address byte, then a negative hold time can result, depending on the edge rates of the SDA and
SCL lines.
3. The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal.
4. Input signal Slew = 10 ns and Output Load = 50 pF
5. Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty.
6. A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement tSU; DAT ≥ 250 ns
must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If
such a device does stretch the LOW period of the SCL signal, then it must output the next data bit to the SDA line trmax
+ tSU; DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification) before the SCL line is
released.
7. Cb = total capacitance of the one bus line in pF.
Table 41. I 2C 1 Mbps timing
Characteristic Symbol Minimum Maximum Unit
SCL Clock Frequency fSCL 0 11MHz
Hold time (repeated) START condition. After this
period, the first clock pulse is generated.
tHD; STA 0.26 — µs
LOW period of the SCL clock tLOW 0.5 — µs
HIGH period of the SCL clock tHIGH 0.26 — µs
Set-up time for a repeated START condition tSU; STA 0.26 — µs
Data hold time for I2C bus devices tHD; DAT 0 — µs
Table continues on the next page...
Peripheral operating requirements and behaviors
Kinetis K22F 128KB Flash, Rev. 7, 08/2016 49
NXP Semiconductors
Table 41. I 2C 1 Mbps timing (continued)
Characteristic Symbol Minimum Maximum Unit
Data set-up time tSU; DAT 50 — ns
Rise time of SDA and SCL signals tr20 +0.1Cb, 2120 ns
Fall time of SDA and SCL signals tf20 +0.1Cb2120 ns
Set-up time for STOP condition tSU; STO 0.26 — µs
Bus free time between STOP and START
condition
tBUF 0.5 — µs
Pulse width of spikes that must be suppressed by
the input filter
tSP 0 50 ns
1. The maximum SCL clock frequency of 1 Mbps can support maximum bus loading when using the High drive pins across
the full voltage range.
2. Cb = total capacitance of the one bus line in pF.
SDA
HD; STA tHD; DAT
tLOW
tSU; DAT
tHIGH
tSU; STA SR PS
S
tHD; STA tSP
tSU; STO
tBUF
tftr
tftr
SCL
Figure 23. Timing definition for devices on the I2C bus
3.8.5 UART switching specifications
See General switching specifications.
3.8.6 I2S/SAI switching specifications
This section provides the AC timing for the I2S/SAI module in master mode (clocks are
driven) and slave mode (clocks are input). All timing is given for noninverted serial
clock polarity (TCR2[BCP] is 0, RCR2[BCP] is 0) and a noninverted frame sync
(TCR4[FSP] is 0, RCR4[FSP] is 0). If the polarity of the clock and/or the frame sync
have been inverted, all the timing remains valid by inverting the bit clock signal
(BCLK) and/or the frame sync (FS) signal shown in the following figures.
Peripheral operating requirements and behaviors
50 Kinetis K22F 128KB Flash, Rev. 7, 08/2016
NXP Semiconductors
3.8.6.1 Normal Run, Wait and Stop mode performance over a limited
operating voltage range
This section provides the operating performance over a limited operating voltage for
the device in Normal Run, Wait and Stop modes.
Table 42. I2S/SAI master mode timing in Normal Run, Wait and Stop modes (limited voltage
range)
Num. Characteristic Min. Max. Unit
Operating voltage 2.7 3.6 V
S1 I2S_MCLK cycle time 40 — ns
S2 I2S_MCLK pulse width high/low 45% 55% MCLK period
S3 I2S_TX_BCLK/I2S_RX_BCLK cycle time (output) 80 — ns
S4 I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low 45% 55% BCLK period
S5 I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output valid
— 15 ns
S6 I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output invalid
0 — ns
S7 I2S_TX_BCLK to I2S_TXD valid — 15 ns
S8 I2S_TX_BCLK to I2S_TXD invalid 0 — ns
S9 I2S_RXD/I2S_RX_FS input setup before
I2S_RX_BCLK
18 — ns
S10 I2S_RXD/I2S_RX_FS input hold after
I2S_RX_BCLK
0 — ns
S1 S2 S2
S3
S4
S4
S5
S9
S7
S9 S10
S7
S8
S6
S10
S8
I2S_MCLK (output)
I2S_TX_BCLK/
I2S_RX_BCLK (output)
I2S_TX_FS/
I2S_RX_FS (output)
I2S_TX_FS/
I2S_RX_FS (input)
I2S_TXD
I2S_RXD
Figure 24. I2S/SAI timing — master modes
Peripheral operating requirements and behaviors
Kinetis K22F 128KB Flash, Rev. 7, 08/2016 51
NXP Semiconductors
Table 43. I2S/SAI slave mode timing in Normal Run, Wait and Stop modes (limited voltage
range)
Num. Characteristic Min. Max. Unit
Operating voltage 2.7 3.6 V
S11 I2S_TX_BCLK/I2S_RX_BCLK cycle time (input) 80 — ns
S12 I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
(input)
45% 55% MCLK period
S13 I2S_TX_FS/I2S_RX_FS input setup before
I2S_TX_BCLK/I2S_RX_BCLK
4.5 — ns
S14 I2S_TX_FS/I2S_RX_FS input hold after
I2S_TX_BCLK/I2S_RX_BCLK
2 — ns
S15 I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid — 20 ns
S16 I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid 0 — ns
S17 I2S_RXD setup before I2S_RX_BCLK 4.5 — ns
S18 I2S_RXD hold after I2S_RX_BCLK 2 — ns
S19 I2S_TX_FS input assertion to I2S_TXD output valid1— 25 ns
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
S15
S13
S15
S17 S18
S15
S16
S16
S14
S16
S11
S12
S12
I2S_TX_BCLK/
I2S_RX_BCLK (input)
I2S_TX_FS/
I2S_RX_FS (output)
I2S_TXD
I2S_RXD
I2S_TX_FS/
I2S_RX_FS (input) S19
Figure 25. I2S/SAI timing — slave modes
3.8.6.2 Normal Run, Wait and Stop mode performance over the full
operating voltage range
This section provides the operating performance over the full operating voltage for the
device in Normal Run, Wait and Stop modes.
Peripheral operating requirements and behaviors
52 Kinetis K22F 128KB Flash, Rev. 7, 08/2016
NXP Semiconductors
Table 44. I2S/SAI master mode timing in Normal Run, Wait and Stop modes (full voltage
range)
Num. Characteristic Min. Max. Unit
Operating voltage 1.71 3.6 V
S1 I2S_MCLK cycle time 40 — ns
S2 I2S_MCLK pulse width high/low 45% 55% MCLK period
S3 I2S_TX_BCLK/I2S_RX_BCLK cycle time (output) 80 — ns
S4 I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low 45% 55% BCLK period
S5 I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output valid
— 15 ns
S6 I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output invalid
-1.0 — ns
S7 I2S_TX_BCLK to I2S_TXD valid — 15 ns
S8 I2S_TX_BCLK to I2S_TXD invalid 0 — ns
S9 I2S_RXD/I2S_RX_FS input setup before
I2S_RX_BCLK
27 — ns
S10 I2S_RXD/I2S_RX_FS input hold after
I2S_RX_BCLK
0 — ns
S1 S2 S2
S3
S4
S4
S5
S9
S7
S9 S10
S7
S8
S6
S10
S8
I2S_MCLK (output)
I2S_TX_BCLK/
I2S_RX_BCLK (output)
I2S_TX_FS/
I2S_RX_FS (output)
I2S_TX_FS/
I2S_RX_FS (input)
I2S_TXD
I2S_RXD
Figure 26. I2S/SAI timing — master modes
Table 45. I2S/SAI slave mode timing in Normal Run, Wait and Stop modes (full voltage
range)
Num. Characteristic Min. Max. Unit
Operating voltage 1.71 3.6 V
S11 I2S_TX_BCLK/I2S_RX_BCLK cycle time (input) 80 — ns
Table continues on the next page...
Peripheral operating requirements and behaviors
Kinetis K22F 128KB Flash, Rev. 7, 08/2016 53
NXP Semiconductors
Table 45. I2S/SAI slave mode timing in Normal Run, Wait and Stop modes (full voltage
range) (continued)
Num. Characteristic Min. Max. Unit
S12 I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
(input)
45% 55% MCLK period
S13 I2S_TX_FS/I2S_RX_FS input setup before
I2S_TX_BCLK/I2S_RX_BCLK
5.8 — ns
S14 I2S_TX_FS/I2S_RX_FS input hold after
I2S_TX_BCLK/I2S_RX_BCLK
2 — ns
S15 I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid — 28.5 ns
S16 I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output
invalid
0 — ns
S17 I2S_RXD setup before I2S_RX_BCLK 5.8 — ns
S18 I2S_RXD hold after I2S_RX_BCLK 2 — ns
S19 I2S_TX_FS input assertion to I2S_TXD output valid1— 26.3 ns
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
S15
S13
S15
S17 S18
S15
S16
S16
S14
S16
S11
S12
S12
I2S_TX_BCLK/
I2S_RX_BCLK (input)
I2S_TX_FS/
I2S_RX_FS (output)
I2S_TXD
I2S_RXD
I2S_TX_FS/
I2S_RX_FS (input) S19
Figure 27. I2S/SAI timing — slave modes
3.8.6.3 VLPR, VLPW, and VLPS mode performance over the full
operating voltage range
This section provides the operating performance over the full operating voltage for the
device in VLPR, VLPW, and VLPS modes.
Table 46. I2S/SAI master mode timing in VLPR, VLPW, and VLPS modes (full voltage range)
Num. Characteristic Min. Max. Unit
Operating voltage 1.71 3.6 V
Table continues on the next page...
Peripheral operating requirements and behaviors
54 Kinetis K22F 128KB Flash, Rev. 7, 08/2016
NXP Semiconductors
Table 46. I2S/SAI master mode timing in VLPR, VLPW, and VLPS modes (full voltage range)
(continued)
Num. Characteristic Min. Max. Unit
S1 I2S_MCLK cycle time 62.5 — ns
S2 I2S_MCLK pulse width high/low 45% 55% MCLK period
S3 I2S_TX_BCLK/I2S_RX_BCLK cycle time (output) 250 — ns
S4 I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low 45% 55% BCLK period
S5 I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output valid
— 45 ns
S6 I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output invalid
-1 — ns
S7 I2S_TX_BCLK to I2S_TXD valid — 45 ns
S8 I2S_TX_BCLK to I2S_TXD invalid 0 — ns
S9 I2S_RXD/I2S_RX_FS input setup before
I2S_RX_BCLK
45 — ns
S10 I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK 0 — ns
S1 S2 S2
S3
S4
S4
S5
S9
S7
S9 S10
S7
S8
S6
S10
S8
I2S_MCLK (output)
I2S_TX_BCLK/
I2S_RX_BCLK (output)
I2S_TX_FS/
I2S_RX_FS (output)
I2S_TX_FS/
I2S_RX_FS (input)
I2S_TXD
I2S_RXD
Figure 28. I2S/SAI timing — master modes
Table 47. I2S/SAI slave mode timing in VLPR, VLPW, and VLPS modes (full voltage range)
Num. Characteristic Min. Max. Unit
Operating voltage 1.71 3.6 V
S11 I2S_TX_BCLK/I2S_RX_BCLK cycle time (input) 250 — ns
S12 I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
(input)
45% 55% MCLK period
Table continues on the next page...
Peripheral operating requirements and behaviors
Kinetis K22F 128KB Flash, Rev. 7, 08/2016 55
NXP Semiconductors
Table 47. I2S/SAI slave mode timing in VLPR, VLPW, and VLPS modes (full voltage range)
(continued)
Num. Characteristic Min. Max. Unit
S13 I2S_TX_FS/I2S_RX_FS input setup before
I2S_TX_BCLK/I2S_RX_BCLK
30 — ns
S14 I2S_TX_FS/I2S_RX_FS input hold after
I2S_TX_BCLK/I2S_RX_BCLK
7 — ns
S15 I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid — 63 ns
S16 I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output
invalid
0 — ns
S17 I2S_RXD setup before I2S_RX_BCLK 30 — ns
S18 I2S_RXD hold after I2S_RX_BCLK 4 — ns
S19 I2S_TX_FS input assertion to I2S_TXD output valid1— 72 ns
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
S15
S13
S15
S17 S18
S15
S16
S16
S14
S16
S11
S12
S12
I2S_TX_BCLK/
I2S_RX_BCLK (input)
I2S_TX_FS/
I2S_RX_FS (output)
I2S_TXD
I2S_RXD
I2S_TX_FS/
I2S_RX_FS (input) S19
Figure 29. I2S/SAI timing — slave modes
4Dimensions
4.1 Obtaining package dimensions
Package dimensions are provided in package drawings.
To find a package drawing, go to nxp.com and perform a keyword search for the
drawing’s document number:
Dimensions
56 Kinetis K22F 128KB Flash, Rev. 7, 08/2016
NXP Semiconductors
If you want the drawing for this package Then use this document number
64-pin LQFP 98ASS23234W
64-pin MAPBGA 98ASA00420D
100-pin LQFP 98ASS23308W
121-pin XFBGA 98ASA00595D
5 Pinout
5.1 K22 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is
responsible for selecting which ALT functionality is available on each pin.
121
BGA
100
LQFP
64
LQFP
64
MAP
BGA
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort
E4 1 1 A1 PTE0/
CLKOUT32
K
ADC1_
SE4a
ADC1_
SE4a
PTE0/
CLKOUT32
K
SPI1_
PCS1
UART1_TX I2C1_SDA RTC_
CLKOUT
E3 2 2 B1 PTE1/
LLWU_P0
ADC1_
SE5a
ADC1_
SE5a
PTE1/
LLWU_P0
SPI1_
SOUT
UART1_RX I2C1_SCL SPI1_SIN
E2 3 — — PTE2/
LLWU_P1
ADC1_
SE6a
ADC1_
SE6a
PTE2/
LLWU_P1
SPI1_SCK UART1_
CTS_b
F4 4 — — PTE3 ADC1_
SE7a
ADC1_
SE7a
PTE3 SPI1_SIN UART1_
RTS_b
SPI1_
SOUT
H7 5 — — PTE4/
LLWU_P2
DISABLED PTE4/
LLWU_P2
SPI1_
PCS0
LPUART0_
TX
G4 6 — — PTE5 DISABLED PTE5 SPI1_
PCS2
LPUART0_
RX
F3 7 — — PTE6 DISABLED PTE6 SPI1_
PCS3
LPUART0_
CTS_b
I2S0_
MCLK
USB_SOF_
OUT
E6 8 3 C5 VDD VDD VDD
G7 9 4 C4 VSS VSS VSS
L6 — — — VSS VSS VSS
F1 10 5 E1 USB0_DP USB0_DP USB0_DP
F2 11 6 D1 USB0_DM USB0_DM USB0_DM
G1 12 7 E2 USBVDD USBVDD USBVDD
G2 13 8 D2 NC NC NC
H1 14 — — ADC0_DP1 ADC0_DP1 ADC0_DP1
Pinout
Kinetis K22F 128KB Flash, Rev. 7, 08/2016 57
NXP Semiconductors
121
BGA
100
LQFP
64
LQFP
64
MAP
BGA
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort
H2 15 — — ADC0_
DM1
ADC0_
DM1
ADC0_
DM1
J1 16 — — ADC1_
DP1/
ADC0_DP2
ADC1_
DP1/
ADC0_DP2
ADC1_
DP1/
ADC0_DP2
J2 17 — — ADC1_
DM1/
ADC0_
DM2
ADC1_
DM1/
ADC0_
DM2
ADC1_
DM1/
ADC0_
DM2
K1 18 9 G1 ADC0_
DP0/
ADC1_DP3
ADC0_
DP0/
ADC1_DP3
ADC0_
DP0/
ADC1_DP3
K2 19 10 F1 ADC0_
DM0/
ADC1_
DM3
ADC0_
DM0/
ADC1_
DM3
ADC0_
DM0/
ADC1_
DM3
L1 20 11 G2 ADC1_
DP0/
ADC0_DP3
ADC1_
DP0/
ADC0_DP3
ADC1_
DP0/
ADC0_DP3
L2 21 12 F2 ADC1_
DM0/
ADC0_
DM3
ADC1_
DM0/
ADC0_
DM3
ADC1_
DM0/
ADC0_
DM3
F5 22 13 F4 VDDA VDDA VDDA
G5 23 14 G4 VREFH VREFH VREFH
G6 24 15 G3 VREFL VREFL VREFL
F6 25 16 F3 VSSA VSSA VSSA
L3 26 17 H1 VREF_
OUT/
CMP1_IN5/
CMP0_IN5/
ADC1_
SE18
VREF_
OUT/
CMP1_IN5/
CMP0_IN5/
ADC1_
SE18
VREF_
OUT/
CMP1_IN5/
CMP0_IN5/
ADC1_
SE18
K5 27 18 H2 DAC0_
OUT/
CMP1_IN3/
ADC0_
SE23
DAC0_
OUT/
CMP1_IN3/
ADC0_
SE23
DAC0_
OUT/
CMP1_IN3/
ADC0_
SE23
K4 — — — CMP0_IN4/
ADC1_
SE23
CMP0_IN4/
ADC1_
SE23
CMP0_IN4/
ADC1_
SE23
L4 28 19 H3 XTAL32 XTAL32 XTAL32
L5 29 20 H4 EXTAL32 EXTAL32 EXTAL32
K6 30 21 H5 VBAT VBAT VBAT
H5 31 — — PTE24 ADC0_
SE17
ADC0_
SE17
PTE24 I2C0_SCL EWM_
OUT_b
Pinout
58 Kinetis K22F 128KB Flash, Rev. 7, 08/2016
NXP Semiconductors
121
BGA
100
LQFP
64
LQFP
64
MAP
BGA
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort
J5 32 — — PTE25 ADC0_
SE18
ADC0_
SE18
PTE25 I2C0_SDA EWM_IN
H6 33 — — PTE26/
CLKOUT32
K
DISABLED PTE26/
CLKOUT32
K
RTC_
CLKOUT
USB_
CLKIN
J6 34 22 D3 PTA0 JTAG_
TCLK/
SWD_CLK/
EZP_CLK
PTA0 UART0_
CTS_b
FTM0_CH5 JTAG_
TCLK/
SWD_CLK
EZP_CLK
H8 35 23 D4 PTA1 JTAG_TDI/
EZP_DI
PTA1 UART0_RX FTM0_CH6 JTAG_TDI EZP_DI
J7 36 24 E5 PTA2 JTAG_
TDO/
TRACE_
SWO/
EZP_DO
PTA2 UART0_TX FTM0_CH7 JTAG_
TDO/
TRACE_
SWO
EZP_DO
H9 37 25 D5 PTA3 JTAG_
TMS/
SWD_DIO
PTA3 UART0_
RTS_b
FTM0_CH0 JTAG_
TMS/
SWD_DIO
J8 38 26 G5 PTA4/
LLWU_P3
NMI_b/
EZP_CS_b
PTA4/
LLWU_P3
FTM0_CH1 NMI_b EZP_CS_b
K7 39 27 F5 PTA5 DISABLED PTA5 USB_
CLKIN
FTM0_CH2 I2S0_TX_
BCLK
JTAG_
TRST_b
E5 40 — — VDD VDD VDD
G3 41 — — VSS VSS VSS
K8 42 28 H6 PTA12 DISABLED PTA12 FTM1_CH0 I2S0_TXD0 FTM1_QD_
PHA
L8 43 29 G6 PTA13/
LLWU_P4
DISABLED PTA13/
LLWU_P4
FTM1_CH1 I2S0_TX_
FS
FTM1_QD_
PHB
K9 44 — — PTA14 DISABLED PTA14 SPI0_
PCS0
UART0_TX I2S0_RX_
BCLK
L9 45 — — PTA15 DISABLED PTA15 SPI0_SCK UART0_RX I2S0_RXD0
J10 46 — — PTA16 DISABLED PTA16 SPI0_
SOUT
UART0_
CTS_b
I2S0_RX_
FS
H10 47 — — PTA17 ADC1_
SE17
ADC1_
SE17
PTA17 SPI0_SIN UART0_
RTS_b
I2S0_
MCLK
L10 48 30 G7 VDD VDD VDD
K10 49 31 H7 VSS VSS VSS
L11 50 32 H8 PTA18 EXTAL0 EXTAL0 PTA18 FTM0_
FLT2
FTM_
CLKIN0
K11 51 33 G8 PTA19 XTAL0 XTAL0 PTA19 FTM1_
FLT0
FTM_
CLKIN1
LPTMR0_
ALT1
J11 52 34 F8 RESET_b RESET_b RESET_b
G11 53 35 F7 PTB0/
LLWU_P5
ADC0_
SE8/
ADC1_SE8
ADC0_
SE8/
ADC1_SE8
PTB0/
LLWU_P5
I2C0_SCL FTM1_CH0 FTM1_QD_
PHA
Pinout
Kinetis K22F 128KB Flash, Rev. 7, 08/2016 59
NXP Semiconductors
121
BGA
100
LQFP
64
LQFP
64
MAP
BGA
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort
G10 54 36 F6 PTB1 ADC0_
SE9/
ADC1_SE9
ADC0_
SE9/
ADC1_SE9
PTB1 I2C0_SDA FTM1_CH1 FTM1_QD_
PHB
G9 55 37 E7 PTB2 ADC0_
SE12
ADC0_
SE12
PTB2 I2C0_SCL UART0_
RTS_b
FTM0_
FLT3
G8 56 38 E8 PTB3 ADC0_
SE13
ADC0_
SE13
PTB3 I2C0_SDA UART0_
CTS_b
FTM0_
FLT0
D11 — — — PTB8 DISABLED PTB8 LPUART0_
RTS_b
E10 57 — — PTB9 DISABLED PTB9 SPI1_
PCS1
LPUART0_
CTS_b
D10 58 — — PTB10 ADC1_
SE14
ADC1_
SE14
PTB10 SPI1_
PCS0
LPUART0_
RX
FTM0_
FLT1
C10 59 — — PTB11 ADC1_
SE15
ADC1_
SE15
PTB11 SPI1_SCK LPUART0_
TX
FTM0_
FLT2
— 60 — — VSS VSS VSS
— 61 — — VDD VDD VDD
B10 62 39 E6 PTB16 DISABLED PTB16 SPI1_
SOUT
UART0_RX FTM_
CLKIN0
EWM_IN
E9 63 40 D7 PTB17 DISABLED PTB17 SPI1_SIN UART0_TX FTM_
CLKIN1
EWM_
OUT_b
D9 64 41 D6 PTB18 DISABLED PTB18 FTM2_CH0 I2S0_TX_
BCLK
FTM2_QD_
PHA
C9 65 42 C7 PTB19 DISABLED PTB19 FTM2_CH1 I2S0_TX_
FS
FTM2_QD_
PHB
F10 66 — — PTB20 DISABLED PTB20 CMP0_
OUT
F9 67 — — PTB21 DISABLED PTB21 CMP1_
OUT
F8 68 — — PTB22 DISABLED PTB22
E8 69 — — PTB23 DISABLED PTB23 SPI0_
PCS5
B9 70 43 D8 PTC0 ADC0_
SE14
ADC0_
SE14
PTC0 SPI0_
PCS4
PDB0_
EXTRG
USB_SOF_
OUT
D8 71 44 C6 PTC1/
LLWU_P6
ADC0_
SE15
ADC0_
SE15
PTC1/
LLWU_P6
SPI0_
PCS3
UART1_
RTS_b
FTM0_CH0 I2S0_TXD0 LPUART0_
RTS_b
C8 72 45 B7 PTC2 ADC0_
SE4b/
CMP1_IN0
ADC0_
SE4b/
CMP1_IN0
PTC2 SPI0_
PCS2
UART1_
CTS_b
FTM0_CH1 I2S0_TX_
FS
LPUART0_
CTS_b
B8 73 46 C8 PTC3/
LLWU_P7
CMP1_IN1 CMP1_IN1 PTC3/
LLWU_P7
SPI0_
PCS1
UART1_RX FTM0_CH2 CLKOUT I2S0_TX_
BCLK
LPUART0_
RX
— 74 47 E3 VSS VSS VSS
— 75 48 E4 VDD VDD VDD
A8 76 49 B8 PTC4/
LLWU_P8
DISABLED PTC4/
LLWU_P8
SPI0_
PCS0
UART1_TX FTM0_CH3 CMP1_
OUT
LPUART0_
TX
Pinout
60 Kinetis K22F 128KB Flash, Rev. 7, 08/2016
NXP Semiconductors
121
BGA
100
LQFP
64
LQFP
64
MAP
BGA
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort
D7 77 50 A8 PTC5/
LLWU_P9
DISABLED PTC5/
LLWU_P9
SPI0_SCK LPTMR0_
ALT2
I2S0_RXD0 CMP0_
OUT
FTM0_CH2
C7 78 51 A7 PTC6/
LLWU_P10
CMP0_IN0 CMP0_IN0 PTC6/
LLWU_P10
SPI0_
SOUT
PDB0_
EXTRG
I2S0_RX_
BCLK
I2S0_
MCLK
B7 79 52 B6 PTC7 CMP0_IN1 CMP0_IN1 PTC7 SPI0_SIN USB_SOF_
OUT
I2S0_RX_
FS
A7 80 53 A6 PTC8 ADC1_
SE4b/
CMP0_IN2
ADC1_
SE4b/
CMP0_IN2
PTC8 I2S0_
MCLK
D6 81 54 B5 PTC9 ADC1_
SE5b/
CMP0_IN3
ADC1_
SE5b/
CMP0_IN3
PTC9 I2S0_RX_
BCLK
FTM2_
FLT0
C6 82 55 B4 PTC10 ADC1_
SE6b
ADC1_
SE6b
PTC10 I2C1_SCL I2S0_RX_
FS
C5 83 56 A5 PTC11/
LLWU_P11
ADC1_
SE7b
ADC1_
SE7b
PTC11/
LLWU_P11
I2C1_SDA
B6 84 — — PTC12 DISABLED PTC12
A6 85 — — PTC13 DISABLED PTC13
A5 86 — — PTC14 DISABLED PTC14
B5 87 — — PTC15 DISABLED PTC15
F7 88 — — VSS VSS VSS
E7 89 — — VDD VDD VDD
D5 90 — — PTC16 DISABLED PTC16 LPUART0_
RX
C4 91 — — PTC17 DISABLED PTC17 LPUART0_
TX
B4 92 — — PTC18 DISABLED PTC18 LPUART0_
RTS_b
D4 93 57 C3 PTD0/
LLWU_P12
DISABLED PTD0/
LLWU_P12
SPI0_
PCS0
UART2_
RTS_b
LPUART0_
RTS_b
D3 94 58 A4 PTD1 ADC0_
SE5b
ADC0_
SE5b
PTD1 SPI0_SCK UART2_
CTS_b
LPUART0_
CTS_b
C3 95 59 C2 PTD2/
LLWU_P13
DISABLED PTD2/
LLWU_P13
SPI0_
SOUT
UART2_RX LPUART0_
RX
I2C0_SCL
B3 96 60 B3 PTD3 DISABLED PTD3 SPI0_SIN UART2_TX LPUART0_
TX
I2C0_SDA
A3 97 61 A3 PTD4/
LLWU_P14
DISABLED PTD4/
LLWU_P14
SPI0_
PCS1
UART0_
RTS_b
FTM0_CH4 EWM_IN SPI1_
PCS0
A2 98 62 C1 PTD5 ADC0_
SE6b
ADC0_
SE6b
PTD5 SPI0_
PCS2
UART0_
CTS_b
FTM0_CH5 EWM_
OUT_b
SPI1_SCK
B2 99 63 B2 PTD6/
LLWU_P15
ADC0_
SE7b
ADC0_
SE7b
PTD6/
LLWU_P15
SPI0_
PCS3
UART0_RX FTM0_CH6 FTM0_
FLT0
SPI1_
SOUT
A1 100 64 A2 PTD7 DISABLED PTD7 UART0_TX FTM0_CH7 FTM0_
FLT1
SPI1_SIN
A11 — — — NC NC NC
Pinout
Kinetis K22F 128KB Flash, Rev. 7, 08/2016 61
NXP Semiconductors
121
BGA
100
LQFP
64
LQFP
64
MAP
BGA
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort
K3 — — — NC NC NC
H4 — — — NC NC NC
B11 — — — NC NC NC
C11 — — — NC NC NC
H11 — — — NC NC NC
C1 — — — NC NC NC
D2 — — — NC NC NC
D1 — — — NC NC NC
E1 — — — NC NC NC
J3 — — — NC NC NC
H3 — — — NC NC NC
J9 — — — NC NC NC
J4 — — — NC NC NC
A10 — — — NC NC NC
A9 — — — NC NC NC
B1 — — — NC NC NC
C2 — — — NC NC NC
L7 — — — NC NC NC
F11 — — — NC NC NC
E11 — — — NC NC NC
A4 — — — NC NC NC
5.2 Recommended connection for unused analog and digital
pins
The following table shows the recommended connections for analog interface pins if
those analog interfaces are not used in the customer's application.
Table 48. Recommended connection for unused analog interfaces
Pin Type Short recommendation Detailed recommendation
Analog/non GPIO PGAx/ADCx Float Analog input - Float
Analog/non GPIO ADCx/CMPx Float Analog input - Float
Analog/non GPIO VREF_OUT Float Analog output - Float
Analog/non GPIO DACx_OUT Float Analog output - Float
Analog/non GPIO RTC_WAKEUP_B Float Analog output - Float
Analog/non GPIO XTAL32 Float Analog output - Float
Analog/non GPIO EXTAL32 Float Analog input - Float
Table continues on the next page...
Pinout
62 Kinetis K22F 128KB Flash, Rev. 7, 08/2016
NXP Semiconductors
Table 48. Recommended connection for unused analog interfaces (continued)
Pin Type Short recommendation Detailed recommendation
GPIO/Analog PTA18/EXTAL0 Float Analog input - Float
GPIO/Analog PTA19/XTAL0 Float Analog output - Float
GPIO/Analog PTx/ADCx Float Float (default is analog input)
GPIO/Analog PTx/CMPx Float Float (default is analog input)
GPIO/Digital PTA0/JTAG_TCLK Float Float (default is JTAG with
pulldown)
GPIO/Digital PTA1/JTAG_TDI Float Float (default is JTAG with
pullup)
GPIO/Digital PTA2/JTAG_TDO Float Float (default is JTAG with
pullup)
GPIO/Digital PTA3/JTAG_TMS Float Float (default is JTAG with
pullup)
GPIO/Digital PTA4/NMI_b 10kΩ pullup or disable and
float
Pull high or disable in PCR &
FOPT and float
GPIO/Digital PTx Float Float (default is disabled)
USB USB0_DP Float Float
USB USB0_DM Float Float
USB USBVDD Tie to ground through 10kΩ Tie to ground through 10kΩ
VBAT VBAT Float Float
VDDA VDDA Always connect to VDD
potential
Always connect to VDD
potential
VREFH VREFH Always connect to VDD
potential
Always connect to VDD
potential
VREFL VREFL Always connect to VSS
potential
Always connect to VSS
potential
VSSA VSSA Always connect to VSS
potential
Always connect to VSS
potential
5.3 K22 Pinouts
This figure shows the pinout diagram for the devices supported by this document.
Many signals may be multiplexed onto a single pin. To determine what signals can be
used on which pin, see the previous section.
Pinout
Kinetis K22F 128KB Flash, Rev. 7, 08/2016 63
NXP Semiconductors
EXTAL32
XTAL32
DAC0_OUT/CMP1_IN3/ADC0_SE23
VREF_OUT/CMP1_IN5/CMP0_IN5/ADC1_SE18
VSSA
VREFL
VREFH
VDDA
ADC1_DM0/ADC0_DM3
ADC1_DP0/ADC0_DP3
ADC0_DM0/ADC1_DM3
ADC0_DP0/ADC1_DP3
NC
USBVDD
USB0_DM
USB0_DP
VSS
VDD
PTE1/LLWU_P0
PTE0/CLKOUT32K
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
64
63
62
61
PTD7
PTD6/LLWU_P15
PTD5
PTD4/LLWU_P14
PTD3
PTD2/LLWU_P13
PTD1
PTD0/LLWU_P12
PTC11/LLWU_P11
PTC10
PTC9
PTC8
PTC7
PTC6/LLWU_P10
PTC5/LLWU_P9
PTC4/LLWU_P8
VDD
VSS
PTC3/LLWU_P7
PTC2
PTC1/LLWU_P6
PTC0
PTB19
PTB18
PTB17
PTB16
PTB3
PTB2
PTB1
PTB0/LLWU_P5
RESET_b
PTA19
PTA18
VSS
VDD
PTA13/LLWU_P4
PTA12
PTA5
PTA4/LLWU_P3
PTA3
PTA2
PTA1
PTA0
VBAT
Figure 30. K22 64 LQFP Pinout Diagram (top view)
Pinout
64 Kinetis K22F 128KB Flash, Rev. 7, 08/2016
NXP Semiconductors
1
APTE0/
CLKOUT32K
BPTE1/
LLWU_P0
C PTD5
D USB0_DM
E USB0_DP
FADC0_DM0/
ADC1_DM3
GADC0_DP0/
ADC1_DP3
1
H
VREF_OUT/
CMP1_IN5/
CMP0_IN5/
ADC1_SE18
2
PTD7
PTD6/
LLWU_P15
PTD2/
LLWU_P13
NC
USBVDD
ADC1_DM0/
ADC0_DM3
ADC1_DP0/
ADC0_DP3
2
DAC0_OUT/
CMP1_IN3/
ADC0_SE23
3
PTD4/
LLWU_P14
PTD3
PTD0/
LLWU_P12
PTA0
VSS
VSSA
VREFL
3
XTAL32
4
PTD1
PTC10
VSS
PTA1
VDD
VDDA
VREFH
4
EXTAL32
5
PTC11/
LLWU_P11
PTC9
VDD
PTA3
PTA2
PTA5
PTA4/
LLWU_P3
5
VBAT
6
PTC8
PTC7
PTC1/
LLWU_P6
PTB18
PTB16
PTB1
PTA13/
LLWU_P4
6
PTA12
7
PTC6/
LLWU_P10
PTC2
PTB19
PTB17
PTB2
PTB0/
LLWU_P5
VDD
7
VSS
8
A
PTC5/
LLWU_P9
B
PTC4/
LLWU_P8
C
PTC3/
LLWU_P7
D
PTC0
EPTB3
FRESET_b
GPTA19
8
HPTA18
Figure 31. K22 64 MAPBGA Pinout Diagram (transparent top view)
Pinout
Kinetis K22F 128KB Flash, Rev. 7, 08/2016 65
NXP Semiconductors
60
59
58
57
56
55
54
53
52
51
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
ADC1_DP0/ADC0_DP3
ADC0_DM0/ADC1_DM3
ADC0_DP0/ADC1_DP3
ADC1_DM1/ADC0_DM2
ADC1_DP1/ADC0_DP2
ADC0_DM1
ADC0_DP1
NC
USBVDD
USB0_DM
USB0_DP
VSS
VDD
PTE6
PTE5
PTE4/LLWU_P2
PTE3
PTE2/LLWU_P1
PTE1/LLWU_P0
PTE0/CLKOUT32K 75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
VDD
VSS
PTC3/LLWU_P7
PTC2
PTC1/LLWU_P6
PTC0
PTB23
PTB22
PTB21
PTB20
PTB19
PTB18
PTB17
PTB16
VDD
VSS
PTB11
PTB10
PTB9
PTB3
PTB2
PTB1
PTB0/LLWU_P5
RESET_b
PTA19
25
24
23
22
21
VSSA
VREFL
VREFH
VDDA
ADC1_DM0/ADC0_DM3
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
99
79
78
77
76
PTD6/LLWU_P15
PTC7
PTC6/LLWU_P10
PTC5/LLWU_P9
PTC4/LLWU_P8
50
49
48
47
46
45
44
43
42
41
PTA18
VSS
VDD
PTA17
PTA16
PTA15
PTA14
PTA13/LLWU_P4
PTA12
VSS
VDD
PTA5
PTA4/LLWU_P3
PTA3
PTA2
PTA1
PTA0
PTE26/CLKOUT32K
PTE25
PTE24
VBAT
EXTAL32
XTAL32
DAC0_OUT/CMP1_IN3/ADC0_SE23
VREF_OUT/CMP1_IN5/CMP0_IN5/ADC1_SE18
98 PTD5
97 PTD4/LLWU_P14
96 PTD3
95 PTD2/LLWU_P13
94 PTD1
93 PTD0/LLWU_P12
92 PTC18
91 PTC17
90 PTC16
89 VDD
88 VSS
80 PTC8
PTC9
PTC10
81
82
83 PTC11/LLWU_P11
84 PTC12
85 PTC13
86 PTC14
87 PTC15
100 PTD7
Figure 32. K22 100 LQFP Pinout Diagram (top view)
Pinout
66 Kinetis K22F 128KB Flash, Rev. 7, 08/2016
NXP Semiconductors
1
A PTD7
B NC
C NC
D NC
E NC
F USB0_DP
G USBVDD
H ADC0_DP1
JADC1_DP1/
ADC0_DP2
KADC0_DP0/
ADC1_DP3
1
LADC1_DP0/
ADC0_DP3
2
PTD5
PTD6/
LLWU_P15
NC
NC
PTE2/
LLWU_P1
USB0_DM
NC
ADC0_DM1
ADC1_DM1/
ADC0_DM2
ADC0_DM0/
ADC1_DM3
2
ADC1_DM0/
ADC0_DM3
3
PTD4/
LLWU_P14
PTD3
PTD2/
LLWU_P13
PTD1
PTE1/
LLWU_P0
PTE6
VSS
NC
NC
NC
3
VREF_OUT/
CMP1_IN5/
CMP0_IN5/
ADC1_SE18
4
NC
PTC18
PTC17
PTD0/
LLWU_P12
PTE0/
CLKOUT32K
PTE3
PTE5
NC
NC
CMP0_IN4/
ADC1_SE23
4
XTAL32
5
PTC14
PTC15
PTC11/
LLWU_P11
PTC16
VDD
VDDA
VREFH
PTE24
PTE25
DAC0_OUT/
CMP1_IN3/
ADC0_SE23
5
EXTAL32
6
PTC13
PTC12
PTC10
PTC9
VDD
VSSA
VREFL
PTE26/
CLKOUT32K
PTA0
VBAT
6
VSS
7
PTC8
PTC7
PTC6/
LLWU_P10
PTC5/
LLWU_P9
VDD
VSS
VSS
PTE4/
LLWU_P2
PTA2
PTA5
7
NC
8
PTC4/
LLWU_P8
PTC3/
LLWU_P7
PTC2
PTC1/
LLWU_P6
PTB23
PTB22
PTB3
PTA1
PTA4/
LLWU_P3
PTA12
8
PTA13/
LLWU_P4
9
NC
PTC0
PTB19
PTB18
PTB17
PTB21
PTB2
PTA3
NC
PTA14
9
PTA15
10
NC
PTB16
PTB11
PTB10
PTB9
PTB20
PTB1
PTA17
PTA16
VSS
10
VDD
11
ANC
BNC
CNC
DPTB8
ENC
FNC
G
PTB0/
LLWU_P5
H
NC
JRESET_b
KPTA19
11
LPTA18
Figure 33. K22 121 XFBGA Pinout Diagram (top view)
6Part identification
6.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the
values of these fields to determine the specific part you have received.
Part identification
Kinetis K22F 128KB Flash, Rev. 7, 08/2016 67
NXP Semiconductors
6.2 Format
Part numbers for this device have the following format:
Q K## A M FFF R T PP CC N
6.3 Fields
This table lists the possible values for each field in the part number (not all
combinations are valid):
Field Description Values
Q Qualification status • M = Fully qualified, general market flow, full
reel
• P = Prequalification
• K = Fully qualified, general market flow, 100
piece reel
K## Kinetis family • K22
A Key attribute • D = Cortex-M4 w/ DSP
• F = Cortex-M4 w/ DSP and FPU
M Flash memory type • N = Program flash only
• X = Program flash and FlexMemory
FFF Program flash memory size • 128 = 128 KB
• 256 = 256 KB
• 512 = 512 KB
R Silicon revision • Z = Initial
• (Blank) = Main
• A = Revision after main
T Temperature range (°C) • V = –40 to 105
• C = –40 to 85
PP Package identifier • LH = 64 LQFP (10 mm x 10 mm)
• MP = 64 MAPBGA (5 mm x 5 mm)
• LL = 100 LQFP (14 mm x 14 mm)
• MC = 121 XFBGA (8 mm x 8 mm)
• DC = 121 XFBGA (8 mm x 8 mm x 0.5 mm)
CC Maximum CPU frequency (MHz) • 5 = 50 MHz
• 7 = 72 MHz
• 10 = 100 MHz
• 12 = 120 MHz
• 15 = 150 MHz
N Packaging type • R = Tape and reel
Part identification
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NXP Semiconductors
6.4 Example
This is an example part number:
MK22FN128VDC10
6.5 121-pin XFBGA part marking
The 121-pin XFBGA package parts follow the part-marking scheme in the following
table.
Table 49. 121-pin XFBGA part marking
MK Partnumber MK Part Marking
MK22FN128VDC10 M22J7VDC
6.6 64-pin MAPBGA part marking
The 64-pin MAPBGA package parts follow the part-marking scheme in the following
table.
Table 50. 64-pin MAPBGA part marking
MK Partnumber MK Part Marking
MK22FN128VMP10 M22J7V
7 Terminology and guidelines
7.1 Definitions
Key terms are defined in the following table:
Term Definition
Rating A minimum or maximum value of a technical characteristic that, if exceeded, may cause
permanent chip failure:
•Operating ratings apply during operation of the chip.
•Handling ratings apply when the chip is not powered.
Table continues on the next page...
Terminology and guidelines
Kinetis K22F 128KB Flash, Rev. 7, 08/2016 69
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Term Definition
NOTE: The likelihood of permanent chip failure increases rapidly as soon as a characteristic
begins to exceed one of its operating ratings.
Operating requirement A specified value or range of values for a technical characteristic that you must guarantee during
operation to avoid incorrect operation and possibly decreasing the useful life of the chip
Operating behavior A specified value or range of values for a technical characteristic that are guaranteed during
operation if you meet the operating requirements and any other specified conditions
Typical value A specified value for a technical characteristic that:
• Lies within the range of values specified by the operating behavior
• Is representative of that characteristic during operation when you meet the typical-value
conditions or other specified conditions
NOTE: Typical values are provided as design guidelines and are neither tested nor
guaranteed.
7.2 Examples
Operating rating:
Operating requirement:
Operating behavior that includes a typical value:
EXAMPLE
EXAMPLEEXAMPLE
EXAMPLE
7.3 Typical-value conditions
Typical values assume you meet the following conditions (or other conditions as
specified):
Terminology and guidelines
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Symbol Description Value Unit
TAAmbient temperature 25 °C
VDD Supply voltage 3.3 V
7.4 Relationship between ratings and operating requirements
–∞
- No permanent failure
- Correct operation
Normal operating range
Fatal range
Expected permanent failure
Fatal range
Expected permanent failure
∞
Operating rating (max.)
Operating requirement (max.)
Operating requirement (min.)
Operating rating (min.)
Operating (power on)
Degraded operating range Degraded operating range
–∞
No permanent failure
Handling range
Fatal range
Expected permanent failure
Fatal range
Expected permanent failure
∞
Handling rating (max.)
Handling rating (min.)
Handling (power off)
- No permanent failure
- Possible decreased life
- Possible incorrect operation
- No permanent failure
- Possible decreased life
- Possible incorrect operation
7.5 Guidelines for ratings and operating requirements
Follow these guidelines for ratings and operating requirements:
• Never exceed any of the chip’s ratings.
• During normal operation, don’t exceed any of the chip’s operating requirements.
• If you must exceed an operating requirement at times other than during normal
operation (for example, during power sequencing), limit the duration as much as
possible.
8Revision History
The following table provides a revision history for this document.
Revision History
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NXP Semiconductors
Table 51. Revision History
Rev. No. Date Substantial Changes
7 08/2016 • Added Terminology and Guidelines section
• Updated the front matter section
• Added Device Revision Number Table
• Updated Chip Errata naming convention in Related Resource table
6 10/2015 • In "Power consumption operating behaviors" section, added "Low power mode
peripheral adders—typical value" table
• In "Thermal operating requirements" table, in footnote, corrected "TJ = TA + ΘJA" to
"TJ = TA + RΘJA"
• Updated "IRC48M specifications" table
• Updated "NVM program/erase timing specifications" table; updated values for thversall
(Erase All high-voltage time)
• In "Slave mode DSPI timing (limited voltage range)" table, added footnote regarding
maximum frequency of operation
• Added new section, "Recommended connections for unused analog and digital pins"
5 4/2015 • On page 1:
• In first bullet of introduction, updated power consumption data to align with the
data in the "Power consumption operating behaviors" table
• In second bullet of introduction, added "USB FS device crystal-less
functionality"
• Under "Communication interfaces," updated I2C bullet to indicate support for up
to 1 Mbps operation
• Under "Operating characteristics," specified that voltage range includes flash
writes
• In "Voltage and current operating requirements" table:
• Removed content related to positive injection
• Updated footnote 1 to say that all analog and I/O pins are internally clamped to
VSS only (not VSS and VDD)through ESD protection diodes.
• In"Power consumption operating behaviors" table:
• Added additional temperature data in power consumption table
• Added Max IDD values based on characterization results equivalent to mean +
3 sigma
• Updated "EMC radiated emissions operating behaviors" table
• In "Thermal operating requirements" table, added the following footnote for ambient
temperature: "Maximum TA can be exceeded only if the user ensures that TJ does not
exceed maximum TJ. The simplest method to determine TJ is: TJ = TA + ΘJA x chip
power dissipation"
• Updated "IRC48M Specifications":
• Updated maximum values for Δfirc48m_ol_lv and Δfirc48m_ol_hv (full temperature)
• Added specifications for Δfirc48m_ol_hv (-40°C to 85°C)
• Updated notes in "USB electrical specifications" section
• In "I2C timing" table,
• Added the following footnote on maximum Fast mode value for SCL Clock
Frequency: "The maximum SCL Clock Frequency in Fast mode with maximum
bus loading can only be achieved when using the High drive pins across the full
voltage range and when using the Normal drive pins and VDD ≥ 2.7 V."
• Updated minimum Fast mode value for LOW period of the SCL clock to 1.25 µ
• Added "I2C 1 Mbps timing" table
• Specified that the figure, "K22F 64 LQFP Pinout Diagram" is a top view
• Specified that the figure, "K22F 64 MAPBGA Pinout Diagram" is a transparent top
view
• Specified that the figure, "K22F 100 LQFP Pinout Diagram" is a top view
Table continues on the next page...
Revision History
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NXP Semiconductors
Table 51. Revision History (continued)
Rev. No. Date Substantial Changes
• Removed Section 6, "Ordering parts."
• Corrected part marking shown in "64-pin MAPBGA part marking" table
4 7/2014 In "Power consumption operating behaviors table":
• Updated existing typical power measurements
• Added new typical power measurements for the following:
• IDD_HSRUN (High Speed Run mode current executing CoreMark code)
• IDD_RUNCO (Run mode current in Compute operation, executing CoreMark
code)
• IDD_RUN (Run mode current in Compute operation, executing while(1) loop)
• IDD_VLPR (Very Low Power mode current executing CoreMark code)
• IDD_VLPR (Very Low Power Run mode current in Compute operation,
executing while(1) loop)
3 5/2014 • In "Voltage and current operating ratings" table, updated maximum digital supply
current
• Updated "Voltage and current operating behaviors" table
• Updated "Power mode transition operating behaviors" table
• Updated "Power consumption operating behaviors" table
• Updated "EMC radiated emissions operating behaviors for 64 LQFP package" table
• Updated "Thermal attributes" table
• Updated "MCG specifications" table
• Updated "IRC48M specifications" table
• Updated "16-bit ADC operating conditions" table
• Updated "Voltage reference electrical specifications" section
• Added "121-pin XFBGA part marking" table
• Added "64-pin MAPBGA part marking" table
24/2014 • In "Voltage and current operating requirements" table, added row for USBVDD
• Updated "Voltage and current operating behaviors" table
• Updated "Thermal attributes" table
• Updated "IRC48M specifications" table
1 3/2014 Initial public release
Revision History
Kinetis K22F 128KB Flash, Rev. 7, 08/2016 73
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Document Number K22P121M100SF9
Revision 7, 08/2016
