Kinetis K22F 128KB Flash
100 MHz ARM® Cortex®-M4 Based Microcontroller with FPU
The Kinetis K22 product family members are optimized for cost-
sensitive applications requiring low-power, USB connectivity,
high peripheral integration and processing efficiency with a
floating-point unit. These devices share the comprehensive
enablement and scalability of the Kinetis family.
This product offers:
• Run power consumption down to 120 μA/MHz. Static
power consumption down to 2.6 μA with full state retention
and 6 μs wakeup. Lowest static mode down to 120 nA.
• USB LS/FS OTG 2.0 with embedded 3.3 V, USB FS device
crystal-less functionality.
Performance
• 100 MHz ARM Cortex-M4 core with DSP instructions
delivering 1.25 Dhrystone MIPS per MHz
Memories and memory interfaces
• 128 KB of embedded flash and 24 KB of RAM
• Serial programming interface(EzPort)
• Pre-programmed Kinetis flashloader for one-time, in-
system factory programming
System peripherals
• Flexible low-power modes, multiple wakeup sources
• 4-channel DMA controller
• Independent External and Software Watchdog monitor
Clocks
• Two crystal oscillators: 32 kHz (RTC) and 32-40 kHz or
3-32 MHz
• Three internal oscillators: 32 kHz, 4 MHz, and 48 MHz
• Multi-purpose clock generator with FLL
Security and integrity modules
• Hardware CRC module
• 128-bit unique identification (ID) number per chip
• Flash access control to protect proprietary software
Human-machine interface
• Up to 67 general-purpose I/O (GPIO)
Analog modules
• Two 16-bit SAR ADCs (1.2 MS/s in 12bit mode)
• One 12-bit DAC
• Two analog comparators (CMP) with 6-bit DAC
• Accurate internal voltage reference
Communication interfaces
• USB LS/FS OTG 2.0 with on-chip transceiver
• USB full-speed device crystal-less operation
• Two SPI modules
• Three UART modules and one low-power UART
• Two I2C: Support for up to 1 Mbps operation
• I2S module
Timers
• One 8-channel general-purpose/PWM timer
• Two 2-channel general-purpose timers with
quadrature decoder functionality
• Periodic interrupt timers
• 16-bit low-power timer
• Real-time clock with independent power domain
• Programmable delay block
Operating Characteristics
• Voltage range (including flash writes): 1.71 to 3.6 V
• Temperature range (ambient): -40 to 105°C
MK22FN128VDC10
MK22FN128VLL10
MK22FN128VMP10
MK22FN128VLH10
121 XFBGA (DC)
8 x 8 x 0.5 Pitch 0.65
mm
100 LQFP (LL)
14 x 14 x 1.4 Pitch 0.5
mm
64 MAPBGA (MP)
5 x 5 x 1.2 Pitch 0.5
mm
64 LQFP (LH)
10 x 10 x 1.4 Pitch 0.5
mm
NXP Semiconductors K22P121M100SF9
Data Sheet: Technical Data Rev. 7, 08/2016
NXP reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products.
Ordering Information
Part Number Memory Number of GPIOs
Flash (KB) SRAM (KB)
MK22FN128VDC10 128 24 67
MK22FN128VLL10 128 24 66
MK22FN128VMP10 128 24 40
MK22FN128VLH10 128 24 40
Device Revision Number
Device Mask Set Number SIM_SDID[REVID] JTAG ID Register[PRN]
0N74K 0000 0000
Related Resources
Type Description Resource
Selector
Guide
The NXP Solution Advisor is a web-based tool that features interactive
application wizards and a dynamic product selector
KINETISKMCUSELGD
Product Brief The Product Brief contains concise overview/summary information to
enable quick evaluation of a device for design suitability.
K22FPB
Reference
Manual
The Reference Manual contains a comprehensive description of the
structure and function (operation) of a device.
K22P121M100SF9RM
Data Sheet The Data Sheet is this document. It includes electrical characteristics
and signal connections.
K22P121M100SF9
Chip Errata The chip mask set Errata provides additional or corrective information for
a particular device mask set.
KINETIS_K_xN74K 1
Package
drawing
Package dimensions are provided by part number:
• MK22FN128VDC10
• MK22FN128VLL10
• MK22FN128VMP10
• MK22FN128VLH10
Package drawing:
•98ASA00595D
•98ASS23308W
•98ASA00420D
•98ASS23234W
1. To find the associated resource, go to nxp.com and perform a search using this term with the x replaced by the revision
of the device you are using.
Figure 1 shows the functional modules in the chip.
2Kinetis K22F 128KB Flash, Rev. 7, 08/2016
NXP Semiconductors
Memories and Memory Interfaces
Program
(128 KB)
RAM
CRC
Programmable
Analog Timers Communication InterfacesSecurity
and Integrity
x1
Clocks
Frequency-
Core
Debug
interfaces DSP
Interrupt
controller
Comparator
x2
16-bit
timer
Human-Machine
Interface (HMI)
Up to
System
DMA (4 ch)
Low-leakage
wakeup
locked loop
Serial
programming
interface
(EzPort)
reference
Internal
clocks
delay block
timers
interrupt
Periodic
real-time
Independent
clock
oscillators
Low/high
frequency
UART
x3
®
Cortex™-M4ARM
FPU
voltage ref
USB OTG
LS/FS
USB LS/FS
transceiver
IS
2
x2
IC
2
Timers
x1 (8ch)
SAR ADC x2
SPI
x2
LPUART
High
performance
Flash access
control
low-power
67 GPIOs
(24 KB)
flash
Internal
watchdogs
and external
with 6-bit DAC
12-bit DAC
x1
x2 (2ch)
16-bit
Figure 1. Functional block diagram
Kinetis K22F 128KB Flash, Rev. 7, 08/2016 3
NXP Semiconductors
Table of Contents
1 Ratings....................................................................................5
1.1 Thermal handling ratings................................................. 5
1.2 Moisture handling ratings................................................ 5
1.3 ESD handling ratings.......................................................5
1.4 Voltage and current operating ratings............................. 5
2 General................................................................................... 6
2.1 AC electrical characteristics.............................................6
2.2 Nonswitching electrical specifications..............................6
2.2.1 Voltage and current operating requirements....... 6
2.2.2 LVD and POR operating requirements................7
2.2.3 Voltage and current operating behaviors.............8
2.2.4 Power mode transition operating behaviors........ 9
2.2.5 Power consumption operating behaviors............ 10
2.2.6 EMC radiated emissions operating behaviors.....17
2.2.7 Designing with radiated emissions in mind..........18
2.2.8 Capacitance attributes.........................................18
2.3 Switching specifications...................................................18
2.3.1 Device clock specifications..................................18
2.3.2 General switching specifications......................... 19
2.4 Thermal specifications.....................................................20
2.4.1 Thermal operating requirements......................... 20
2.4.2 Thermal attributes................................................20
3 Peripheral operating requirements and behaviors.................. 21
3.1 Core modules.................................................................. 21
3.1.1 SWD electricals .................................................. 21
3.1.2 JTAG electricals.................................................. 22
3.2 System modules.............................................................. 25
3.3 Clock modules................................................................. 25
3.3.1 MCG specifications..............................................25
3.3.2 IRC48M specifications.........................................27
3.3.3 Oscillator electrical specifications........................28
3.3.4 32 kHz oscillator electrical characteristics...........30
3.4 Memories and memory interfaces................................... 31
3.4.1 Flash electrical specifications..............................31
3.4.2 EzPort switching specifications........................... 32
3.5 Security and integrity modules........................................ 33
3.6 Analog............................................................................. 33
3.6.1 ADC electrical specifications............................... 34
3.6.2 CMP and 6-bit DAC electrical specifications....... 38
3.6.3 12-bit DAC electrical characteristics....................40
3.6.4 Voltage reference electrical specifications.......... 43
3.7 Timers..............................................................................44
3.8 Communication interfaces............................................... 44
3.8.1 USB electrical specifications............................... 45
3.8.2 DSPI switching specifications (limited voltage
range).................................................................. 45
3.8.3 DSPI switching specifications (full voltage
range).................................................................. 47
3.8.4 Inter-Integrated Circuit Interface (I2C) timing...... 48
3.8.5 UART switching specifications............................ 50
3.8.6 I2S/SAI switching specifications..........................50
4 Dimensions............................................................................. 56
4.1 Obtaining package dimensions....................................... 56
5 Pinout......................................................................................57
5.1 K22 Signal Multiplexing and Pin Assignments.................57
5.2 Recommended connection for unused analog and
digital pins........................................................................62
5.3 K22 Pinouts..................................................................... 63
6 Part identification.....................................................................67
6.1 Description.......................................................................67
6.2 Format............................................................................. 67
6.3 Fields............................................................................... 68
6.4 Example...........................................................................68
6.5 121-pin XFBGA part marking.......................................... 69
6.6 64-pin MAPBGA part marking......................................... 69
7 Terminology and guidelines.................................................... 69
7.1 Definitions........................................................................69
7.2 Examples.........................................................................70
7.3 Typical-value conditions.................................................. 70
7.4 Relationship between ratings and operating
requirements....................................................................71
7.5 Guidelines for ratings and operating requirements..........71
8 Revision History...................................................................... 71
4Kinetis K22F 128KB Flash, Rev. 7, 08/2016
NXP Semiconductors
1 Ratings
1.1 Thermal handling ratings
Symbol Description Min. Max. Unit Notes
TSTG Storage temperature –55 150 °C 1
TSDR Solder temperature, lead-free — 260 °C 2
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.2 Moisture handling ratings
Symbol Description Min. Max. Unit Notes
MSL Moisture sensitivity level — 3 — 1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.3 ESD handling ratings
Symbol Description Min. Max. Unit Notes
VHBM Electrostatic discharge voltage, human body model -2000 +2000 V 1
VCDM Electrostatic discharge voltage, charged-device
model
-500 +500 V 2
ILAT Latch-up current at ambient temperature of 105°C -100 +100 mA 3
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human
Body Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.
1.4 Voltage and current operating ratings
Ratings
Kinetis K22F 128KB Flash, Rev. 7, 08/2016 5
NXP Semiconductors
Symbol Description Min. Max. Unit
USBVDD USB Transceiver supply voltage –0.3 3.8 V
VDD Digital supply voltage –0.3 3.8 V
IDD Digital supply current — 145 mA
VDIO Digital input voltage –0.3 VDD + 0.3 V
VAIO Analog1–0.3 VDD + 0.3 V
IDMaximum current single pin limit (applies to all digital pins) –25 25 mA
VDDA Analog supply voltage VDD – 0.3 VDD + 0.3 V
VUSB0_DP USB0_DP input voltage –0.3 3.63 V
VUSB0_DM USB0_DM input voltage –0.3 3.63 V
VBAT RTC battery supply voltage –0.3 3.8 V
1. Analog pins are defined as pins that do not have an associated general purpose I/O port function.
2 General
2.1 AC electrical characteristics
Unless otherwise specified, propagation delays are measured from the 50% to the 50%
point, and rise and fall times are measured at the 20% and 80% points, as shown in the
following figure.
80%
20%
50%
VIL
Input Signal
VIH
Fall Time
High
Low
Rise Time
Midpoint1
The midpoint is VIL + (VIH - VIL) / 2
Figure 2. Input signal measurement reference
2.2 Nonswitching electrical specifications
General
6Kinetis K22F 128KB Flash, Rev. 7, 08/2016
NXP Semiconductors
2.2.1 Voltage and current operating requirements
Table 1. Voltage and current operating requirements
Symbol Description Min. Max. Unit Notes
VDD Supply voltage 1.71 3.6 V
VDDA Analog supply voltage 1.71 3.6 V
VDD – VDDA VDD-to-VDDA differential voltage –0.1 0.1 V
VSS – VSSA VSS-to-VSSA differential voltage –0.1 0.1 V
VBAT RTC battery supply voltage 1.71 3.6 V
USBVDD USB Transceiver supply voltage 3.0 3.6 V 1
VIH Input high voltage
• 2.7 V ≤ VDD ≤ 3.6 V
• 1.7 V ≤ VDD ≤ 2.7 V
0.7 × VDD
0.75 × VDD
—
—
V
V
VIL Input low voltage
• 2.7 V ≤ VDD ≤ 3.6 V
• 1.7 V ≤ VDD ≤ 2.7 V
—
—
0.35 × VDD
0.3 × VDD
V
V
VHYS Input hysteresis 0.06 × VDD — V
IICIO Analog and I/O pin DC injection current — single pin
• VIN < VSS-0.3V (Negative current injection) -3 — mA
2
IICcont Contiguous pin DC injection current —regional limit,
includes sum of negative injection currents or sum of
positive injection currents of 16 contiguous pins
• Negative current injection -25 — mA
VODPU Open drain pullup voltage level VDD VDD V3
VRAM VDD voltage required to retain RAM 1.2 — V
VRFVBAT VBAT voltage required to retain the VBAT register file VPOR_VBAT — V
1. USB nominal operating voltage is 3.3 V.
2. All analog and I/O pins are internally clamped to VSS through ESD protection diodes. If VIN is less than VIO_MIN or
greater than VIO_MAX, a current limiting resistor is required. The negative DC injection current limiting resistor is
calculated as R=(VIO_MIN-VIN)/|IICIO|.
3. Open drain outputs must be pulled to VDD.
2.2.2 LVD and POR operating requirements
Table 2. VDD supply LVD and POR operating requirements
Symbol Description Min. Typ. Max. Unit Notes
VPOR Falling VDD POR detect voltage 0.8 1.1 1.5 V
VLVDH Falling low-voltage detect threshold — high
range (LVDV=01)
2.48 2.56 2.64 V
Table continues on the next page...
General
Kinetis K22F 128KB Flash, Rev. 7, 08/2016 7
NXP Semiconductors
Table 2. VDD supply LVD and POR operating requirements (continued)
Symbol Description Min. Typ. Max. Unit Notes
VLVW1H
VLVW2H
VLVW3H
VLVW4H
Low-voltage warning thresholds — high range
• Level 1 falling (LVWV=00)
• Level 2 falling (LVWV=01)
• Level 3 falling (LVWV=10)
• Level 4 falling (LVWV=11)
2.62
2.72
2.82
2.92
2.70
2.80
2.90
3.00
2.78
2.88
2.98
3.08
V
V
V
V
1
VHYSH Low-voltage inhibit reset/recover hysteresis —
high range
— 80 — mV
VLVDL Falling low-voltage detect threshold — low
range (LVDV=00)
1.54 1.60 1.66 V
VLVW1L
VLVW2L
VLVW3L
VLVW4L
Low-voltage warning thresholds — low range
• Level 1 falling (LVWV=00)
• Level 2 falling (LVWV=01)
• Level 3 falling (LVWV=10)
• Level 4 falling (LVWV=11)
1.74
1.84
1.94
2.04
1.80
1.90
2.00
2.10
1.86
1.96
2.06
2.16
V
V
V
V
1
VHYSL Low-voltage inhibit reset/recover hysteresis —
low range
— 60 — mV
VBG Bandgap voltage reference 0.97 1.00 1.03 V
tLPO Internal low power oscillator period — factory
trimmed
900 1000 1100 μs
1. Rising threshold is the sum of falling threshold and hysteresis voltage
Table 3. VBAT power operating requirements
Symbol Description Min. Typ. Max. Unit Notes
VPOR_VBAT Falling VBAT supply POR detect voltage 0.8 1.1 1.5 V
2.2.3 Voltage and current operating behaviors
Table 4. Voltage and current operating behaviors
Symbol Description Min. Typ. Max. Unit Notes
VOH Output high voltage — Normal drive pad except
RESET_B
2.7 V ≤ VDD ≤ 3.6 V, IOH = -5 mA VDD – 0.5 — — V 1
1.71 V ≤ VDD ≤ 2.7 V, IOH = -2.5 mA VDD – 0.5 — — V
VOH Output high voltage — High drive pad except
RESET_B
2.7 V ≤ VDD ≤ 3.6 V, IOH = -20 mA VDD – 0.5 — — V 1
Table continues on the next page...
General
8Kinetis K22F 128KB Flash, Rev. 7, 08/2016
NXP Semiconductors
Table 4. Voltage and current operating behaviors (continued)
Symbol Description Min. Typ. Max. Unit Notes
1.71 V ≤ VDD ≤ 2.7 V, IOH = -10 mA VDD – 0.5 — — V
IOHT Output high current total for all ports — — 100 mA
VOL Output low voltage — Normal drive pad except
RESET_B
2.7 V ≤ VDD ≤ 3.6 V, IOL = 5 mA — — 0.5 V 1
1.71 V ≤ VDD ≤ 2.7 V, IOL = 2.5 mA — — 0.5 V
VOL Output low voltage — High drive pad except
RESET_B
2.7 V ≤ VDD ≤ 3.6 V, IOL = 20 mA — — 0.5 V 1
1.71 V ≤ VDD ≤ 2.7 V, IOL = 10 mA — — 0.5 V
VOL Output low voltage — RESET_B
2.7 V ≤ VDD ≤ 3.6 V, IOL = 3 mA — — 0.5 V
1.71 V ≤ VDD ≤ 2.7 V, IOL = 1.5 mA — — 0.5 V
IOLT Output low current total for all ports — — 100 mA
IIN Input leakage current (per pin) for full
temperature range
All pins other than high drive port pins — 0.002 0.5 μA 1, 2
High drive port pins — 0.004 0.5 μA
IIN Input leakage current (total all pins) for full
temperature range
— — 1.0 μA 2
RPU Internal pullup resistors 20 — 50 kΩ 3
RPD Internal pulldown resistors 20 — 50 kΩ 4
1. PTB0, PTB1, PTC3, PTC4, PTD4, PTD5, PTD6, and PTD7 I/O have both high drive and normal drive capability
selected by the associated PTx_PCRn[DSE] control bit. All other GPIOs are normal drive only.
2. Measured at VDD=3.6V
3. Measured at VDD supply voltage = VDD min and Vinput = VSS
4. Measured at VDD supply voltage = VDD min and Vinput = VDD
2.2.4 Power mode transition operating behaviors
All specifications except tPOR, and VLLSx→RUN recovery times in the following
table assume this clock configuration:
• CPU and system clocks = 72 MHz
• Bus clock = 36 MHz
• Flash clock = 24 MHz
• MCG mode: FEI
General
Kinetis K22F 128KB Flash, Rev. 7, 08/2016 9
NXP Semiconductors
Table 5. Power mode transition operating behaviors
Symbol Description Min. Typ. Max. Unit Notes
tPOR After a POR event, amount of time from the
point VDD reaches 1.71 V to execution of the
first instruction across the operating temperature
range of the chip.
— — 300 μs 1
• VLLS0 → RUN
—
—
135
μs
• VLLS1 → RUN
—
—
135
μs
• VLLS2 → RUN
—
—
75
μs
• VLLS3 → RUN
—
—
75
μs
• LLS2 → RUN
—
—
6
μs
• LLS3 → RUN
—
—
6
μs
• VLPS → RUN
—
—
5.7
μs
• STOP → RUN
—
—
5.7
μs
1. Normal boot (FTFA_OPT[LPBOOT]=1)
2.2.5 Power consumption operating behaviors
The current parameters in the table below are derived from code executing a while(1)
loop from flash, unless otherwise noted.
The IDD typical values represent the statistical mean at 25°C, and the IDD maximum
values for RUN, WAIT, VLPR, and VLPW represent data collected at 125°C junction
temperature unless otherwise noted. The maximum values represent characterized
results equivalent to the mean plus three times the standard deviation (mean + 3 sigma).
Table 6. Power consumption operating behaviors
Symbol Description Min. Typ. Max. Unit Notes
IDDA Analog supply current — — See note mA 1
IDD_HSRUN High Speed Run mode current - all peripheral
clocks disabled, CoreMark benchmark code
executing from flash
Table continues on the next page...
General
10 Kinetis K22F 128KB Flash, Rev. 7, 08/2016
NXP Semiconductors
Table 6. Power consumption operating behaviors (continued)
Symbol Description Min. Typ. Max. Unit Notes
@ 1.8V — 19.51 20.24 mA 2, 3, 4
@ 3.0V — 19.51 20.24 mA
IDD_HSRUN High Speed Run mode current - all peripheral
clocks disabled, code executing from flash
@ 1.8V — 16.9 17.63 mA 5
@ 3.0V — 17.0 17.73 mA
IDD_HSRUN High Speed Run mode current — all peripheral
clocks enabled, code executing from flash
@ 1.8V — 22.8 23.53 mA 6
@ 3.0V — 22.9 23.63 mA
IDD_RUN Run mode current in Compute operation —
CoreMark benchmark code executing from flash
@ 1.8V — 11.39 12.12 mA 2, 3, 7
@ 3.0V — 11.58 12.31 mA
IDD_RUN Run mode current in Compute operation —
code executing from flash
@ 1.8V — 10.90 11.90 mA 7
@ 3.0V — 10.90 12.23 mA
IDD_RUN Run mode current — all peripheral clocks
disabled, code executing from flash
@ 1.8V — 11.8 12.53 mA 8
@ 3.0V — 11.9 12.63 mA
IDD_RUN Run mode current — all peripheral clocks
enabled, code executing from flash
@ 1.8V — 15.5 16.23 mA 9
@ 3.0V
• @ 25°C — 15.6 16.33 mA
• @ 70°C — 15.6 16.33 mA
• @ 85°C — 15.6 16.33 mA
• @ 105°C — 16.3 17.03 mA
IDD_RUN Run mode current — Compute operation, code
executing from flash
@ 1.8V — 10.9 11.63 mA 10
@ 3.0V
• @ 25°C — 10.9 11.63 mA
• @ 70°C — 10.9 11.63 mA
• @ 85°C — 10.9 11.63 mA
• @ 105°C — 11.5 12.23 mA
Table continues on the next page...
General
Kinetis K22F 128KB Flash, Rev. 7, 08/2016 11
NXP Semiconductors
Table 6. Power consumption operating behaviors (continued)
Symbol Description Min. Typ. Max. Unit Notes
IDD_WAIT Wait mode high frequency current at 3.0 V — all
peripheral clocks disabled
— 6.5 7.23 mA 8
IDD_WAIT Wait mode reduced frequency current at 3.0 V
— all peripheral clocks disabled
— 3.9 4.63 mA 11
IDD_VLPR Very-low-power run mode current in Compute
operation — CoreMark benchmark code
executing from flash
@ 1.8V — 0.60 0.88 mA 2, 3, 12
@ 3.0V — 0.61 0.89 mA
IDD_VLPR Very-low-power run mode current in Compute
operation, code executing from flash
@ 1.8V — 0.48 0.76 mA 12
@ 3.0V — 0.48 0.76 mA
IDD_VLPR Very-low-power run mode current at 3.0 V — all
peripheral clocks disabled
— 0.54 0.82 mA 13
IDD_VLPR Very-low-power run mode current at 3.0 V — all
peripheral clocks enabled
— 0.79 1.07 mA 14
IDD_VLPW Very-low-power wait mode current at 3.0 V —
all peripheral clocks disabled
— 0.30 0.59 mA 15
IDD_STOP Stop mode current at 3.0 V
@ -40°C to 25°C — 0.27 0.33 mA
@ 70°C — 0.31 0.36 mA
@ 85°C — 0.31 0.36 mA
@ 105°C — 0.43 0.66 mA
IDD_VLPS Very-low-power stop mode current at 3.0 V
@ -40°C to 25°C — 4.2 9.00 µA
@ 70°C — 15.8 31.90 µA
@ 85°C — 26.9 50.95 µA
@ 105°C — 43.0 89.00 µA
IDD_LLS3 Low leakage stop mode 3 current at 3.0 V
@ -40°C to 25°C — 2.6 3.30 µA
@ 70°C — 6.2 8.60 µA
@ 85°C — 9.6 12.30 µA
@ 105°C — 15.0 26.00 µA
IDD_LLS2 Low leakage stop mode 2 current at 3.0 V
@ -40°C to 25°C — 2.4 3.00 µA
@ 70°C — 5.2 6.85 µA
@ 85°C — 7.9 9.95 µA
@ 105°C — 12.0 20.00 µA
IDD_VLLS3 Very low-leakage stop mode 3 current at 3.0 V
@ -40°C to 25°C — 1.8 2.10 µA
Table continues on the next page...
General
12 Kinetis K22F 128KB Flash, Rev. 7, 08/2016
NXP Semiconductors
Table 6. Power consumption operating behaviors (continued)
Symbol Description Min. Typ. Max. Unit Notes
@ 70°C — 4.3 5.70 µA
@ 85°C — 6.6 8.10 µA
@ 105°C — 10.0 17.00 µA
IDD_VLLS2 Very low-leakage stop mode 2 current at 3.0 V
@ -40°C to 25°C — 1.6 1.80 µA
@ 70°C — 3.1 3.90 µA
@ 85°C — 4.7 7.00 µA
@ 105°C — 6.8 10.90 µA
IDD_VLLS1 Very low-leakage stop mode 1 current at 3.0 V
@ -40°C to 25°C — 0.70 0.90 µA
@ 70°C — 1.78 2.09 µA
@ 85°C — 2.8 3.25 µA
@ 105°C — 4.0 6.15 µA
IDD_VLLS0 Very low-leakage stop mode 0 current at 3.0 V
with POR detect circuit enabled
@ -40°C to 25°C — 0.40 0.49 µA
@ 70°C — 1.38 1.49 µA
@ 85°C — 2.40 2.70 µA
@ 105°C — 3.6 5.65 µA
IDD_VLLS0 Very low-leakage stop mode 0 current at 3.0 V
with POR detect circuit disabled
@ -40°C to 25°C — 0.12 0.19 µA
@ 70°C — 1.05 1.13 µA
@ 85°C — 2.1 2.45 µA
@ 105°C — 3.3 5.35 µA
IDD_VBAT Average current with RTC and 32kHz disabled
at 3.0 V
@ -40°C to 25°C — 0.18 0.21 µA
@ 70°C — 0.66 0.86 µA
@ 85°C — 1.52 2.24 µA
@ 105°C — 2.92 4.30 µA
IDD_VBAT Average current when CPU is not accessing
RTC registers
@ 1.8V
• @ -40°C to 25°C — 0.57 0.67 µA 16
• @ 70°C — 0.90 1.2 µA
• @ 85°C — 0.90 1.2 µA
• @ 105°C — 2.4 3.5 µA
@ 3.0V
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General
Kinetis K22F 128KB Flash, Rev. 7, 08/2016 13
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Table 6. Power consumption operating behaviors (continued)
Symbol Description Min. Typ. Max. Unit Notes
• @ -40°C to 25°C — 0.67 0.94 µA
• @ 70°C — 1.0 1.4 µA
• @ 85°C — 1.0 1.4 µA
• @ 105°C — 2.7 3.9 µA
1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See
each module's specification for its supply current.
2. Cache on and prefetch on, low compiler optimization.
3. Coremark benchmark compiled using IAR 7.2 withs optimization level low.
4. 100 MHz core and system clock, 50 MHz bus clock, and 25 MHz flash clock. MCG configured for FEE mode. All
peripheral clocks disabled.
5. 100MHz core and system clock, 50MHz bus clock, and 25MHz flash clock. MCG configured for FEI mode. All peripheral
clocks disabled.
6. 100MHz core and system clock, 50MHz bus clock, and 25MHz flash clock. MCG configured for FEI mode. All peripheral
clocks enabled.
7. 72 MHz core and system clock, 36 MHz bus clock, and 24 MHz flash clock. MCG configured for FEE mode. All
peripheral clocks disabled. Compute operation.
8. 72MHz core and system clock, 36MHz bus clock, and 24MHz flash clock. MCG configured for FEI mode. All peripheral
clocks disabled.
9. 72MHz core and system clock, 36MHz bus clock, and 24MHz flash clock. MCG configured for FEI mode. All peripheral
clocks enabled.
10. 72MHz core and system clock, 36MHz bus clock, and 24MHz flash clock. MCG configured for FEI mode. Compute
Operation.
11. 25MHz core and system clock, 25MHz bus clock, and 25MHz flash clock. MCG configured for FEI mode.
12. 4 MHz core, system, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. Compute Operation. Code
executing from flash.
13. 4 MHz core, system, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. All peripheral clocks
disabled. Code executing from flash.
14. 4 MHz core, system, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. All peripheral clocks
enabled but peripherals are not in active operation. Code executing from flash.
15. 4 MHz core, system, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. All peripheral clocks
disabled.
16. Includes 32kHz oscillator current and RTC operation.
Table 7. Low power mode peripheral adders—typical value
Symbol Description Temperature (°C) Unit
-40 25 50 70 85 105
IIREFSTEN4MHz 4 MHz internal reference clock (IRC)
adder. Measured by entering STOP or
VLPS mode with 4 MHz IRC enabled.
56 56 56 56 56 56 µA
IIREFSTEN32KHz 32 kHz internal reference clock (IRC)
adder. Measured by entering STOP
mode with the 32 kHz IRC enabled.
52 52 52 52 52 52 µA
IEREFSTEN4MHz External 4 MHz crystal clock adder.
Measured by entering STOP or VLPS
mode with the crystal enabled.
206 228 237 245 251 258 uA
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14 Kinetis K22F 128KB Flash, Rev. 7, 08/2016
NXP Semiconductors
Table 7. Low power mode peripheral adders—typical value (continued)
Symbol Description Temperature (°C) Unit
-40 25 50 70 85 105
IEREFSTEN32KHz External 32 kHz crystal clock adder by
means of the OSC0_CR[EREFSTEN
and EREFSTEN] bits. Measured by
entering all modes with the crystal
enabled.
VLLS1
VLLS3
LLS
VLPS
STOP
440
440
490
510
510
490
490
490
560
560
540
540
540
560
560
560
560
560
560
560
570
570
570
610
610
580
580
680
680
680
nA
I48MIRC 48 Mhz internal reference clock 350 350 350 350 350 350 µA
ICMP CMP peripheral adder measured by
placing the device in VLLS1 mode with
CMP enabled using the 6-bit DAC and a
single external input for compare.
Includes 6-bit DAC power consumption.
22 22 22 22 22 22 µA
IRTC RTC peripheral adder measured by
placing the device in VLLS1 mode with
external 32 kHz crystal enabled by
means of the RTC_CR[OSCE] bit and
the RTC ALARM set for 1 minute.
Includes ERCLK32K (32 kHz external
crystal) power consumption.
432 357 388 475 532 810 nA
IUART UART peripheral adder measured by
placing the device in STOP or VLPS
mode with selected clock source waiting
for RX data at 115200 baud rate.
Includes selected clock source power
consumption.
MCGIRCLK (4 MHz internal reference
clock)
>OSCERCLK (4 MHz external crystal)
66
214
66
237
66
246
66
254
66
260
66
268
µA
IBG Bandgap adder when BGEN bit is set
and device is placed in VLPx, LLS, or
VLLSx mode.
45 45 45 45 45 45 µA
IADC ADC peripheral adder combining the
measured values at VDD and VDDA by
placing the device in STOP or VLPS
mode. ADC is configured for low power
mode using the internal clock and
continuous conversions.
42 42 42 42 42 42 µA
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Kinetis K22F 128KB Flash, Rev. 7, 08/2016 15
NXP Semiconductors
2.2.5.1 Diagram: Typical IDD_RUN operating behavior
The following data was measured under these conditions:
• MCG in FBE mode for 50 MHz and lower frequencies. MCG in FEE mode at
frequencies between 50 MHz and 100MHz.
• No GPIOs toggled
• Code execution from flash with cache enabled
• For the ALLOFF curve, all peripheral clocks are disabled except FTFA
Figure 3. Run mode supply current vs. core frequency
General
16 Kinetis K22F 128KB Flash, Rev. 7, 08/2016
NXP Semiconductors
Figure 4. VLPR mode supply current vs. core frequency
2.2.6 EMC radiated emissions operating behaviors
Table 8. EMC radiated emissions operating behaviors for 64 LQFP package
Parame
ter
Conditions Clocks Frequency range Level
(Typ.)
Unit Notes
VEME Device configuration,
test conditions and EM
testing per standard IEC
61967-2.
Supply voltages:
Temp = 25°C
FSYS = 100 MHz
FBUS = 50 MHz
External crystal = 10 MHz
150 kHz–50 MHz 13 dBuV 1, 2, 3
50 MHz–150 MHz 24
150 MHz–500 MHz 23
500 MHz–1000 MHz 7
IEC level L 4
1. Measurements were made per IEC 61967-2 while the device was running typical application code.
2. Measurements were performed on the 64LQFP device, MK22FN128VLH10 .
3. The reported emission level is the value of the maximum measured emission, rounded up to the next whole number,
from among the measured orientations in each frequency range.
4. IEC Level Maximums: M ≤ 18dBmV, L ≤ 24dBmV, K ≤ 30dBmV, I ≤ 36dBmV, H ≤ 42dBmV .
General
Kinetis K22F 128KB Flash, Rev. 7, 08/2016 17
NXP Semiconductors
2.2.7 Designing with radiated emissions in mind
To find application notes that provide guidance on designing your system to minimize
interference from radiated emissions:
• Go to nxp.com
• Perform a keyword search for “EMC design.”
2.2.8 Capacitance attributes
Table 9. Capacitance attributes
Symbol Description Min. Max. Unit
CIN_A Input capacitance: analog pins — 7 pF
CIN_D Input capacitance: digital pins — 7 pF
2.3 Switching specifications
2.3.1 Device clock specifications
Table 10. Device clock specifications
Symbol Description Min. Max. Unit Notes
High Speed run mode
fSYS System and core clock — 100 MHz
fBUS Bus clock — 50 MHz
Normal run mode (and High Speed run mode unless otherwise specified above)
fSYS System and core clock — 72 MHz
fSYS_USB System and core clock when Full Speed USB in
operation
20 — MHz
fBUS Bus clock — 50 MHz
fFLASH Flash clock — 25 MHz
fLPTMR LPTMR clock — 25 MHz
VLPR mode1
fSYS System and core clock — 4 MHz
fBUS Bus clock — 4 MHz
fFLASH Flash clock — 1 MHz
fERCLK External reference clock — 16 MHz
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18 Kinetis K22F 128KB Flash, Rev. 7, 08/2016
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Table 10. Device clock specifications (continued)
Symbol Description Min. Max. Unit Notes
fLPTMR_pin LPTMR clock — 25 MHz
fLPTMR_ERCLK LPTMR external reference clock — 16 MHz
fI2S_MCLK I2S master clock — 12.5 MHz
fI2S_BCLK I2S bit clock — 4 MHz
1. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for
any other module.
2.3.2 General switching specifications
These general purpose specifications apply to all signals configured for GPIO, UART,
and timers.
Table 11. General switching specifications
Symbol Description Min. Max. Unit Notes
GPIO pin interrupt pulse width (digital glitch filter
disabled) — Synchronous path
1.5 — Bus clock
cycles
1, 2
External RESET and NMI pin interrupt pulse width —
Asynchronous path
100 — ns 3
GPIO pin interrupt pulse width (digital glitch filter
disabled, passive filter disabled) — Asynchronous
path
50 — ns 4
Mode select (EZP_CS) hold time after reset
deassertion
2 — Bus clock
cycles
Port rise and fall time
• Slew disabled
• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V
• Slew enabled
• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V
—
—
—
—
10
5
30
16
ns
ns
ns
ns
5
1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses
may or may not be recognized. In Stop, VLPS, LLS, and VLLSx modes, the synchronizer is bypassed so shorter
pulses can be recognized in that case.
2. The greater of synchronous and asynchronous timing must be met.
3. These pins have a passive filter enabled on the inputs. This is the shortest pulse width that is guaranteed to be
recognized.
4. These pins do not have a passive filter on the inputs. This is the shortest pulse width that is guaranteed to be
recognized.
5. 25 pF load
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2.4 Thermal specifications
2.4.1 Thermal operating requirements
Table 12. Thermal operating requirements
Symbol Description Min. Max. Unit Notes
TJDie junction temperature –40 125 °C
TAAmbient temperature –40 105 °C 1
1. Maximum TA can be exceeded only if the user ensures that TJ does not exceed maximum TJ. The simplest method to
determine TJ is: TJ = TA + RΘJA × chip power dissipation.
2.4.2 Thermal attributes
Board
type Symbol Descripti
on 121
XFBGA 100 LQFP 64 LQFP 64
MAPBGA Unit Notes
Single-layer
(1s)
RθJA Thermal
resistance,
junction to
ambient
(natural
convection)
46.6 63 69 53.8 °C/W 1
Four-layer
(2s2p)
RθJA Thermal
resistance,
junction to
ambient
(natural
convection)
39.3 50 51 46.0 °C/W 2
Single-layer
(1s)
RθJMA Thermal
resistance,
junction to
ambient
(200 ft./min.
air speed)
39.0 53 57 45.8 °C/W 3
Four-layer
(2s2p)
RθJMA Thermal
resistance,
junction to
ambient
(200 ft./min.
air speed)
35.3 44 44 41.0 °C/W 3
— RθJB Thermal
resistance,
junction to
board
36.7 36 33 43.4 °C/W 4
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20 Kinetis K22F 128KB Flash, Rev. 7, 08/2016
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Board
type Symbol Descripti
on 121
XFBGA 100 LQFP 64 LQFP 64
MAPBGA Unit Notes
— RθJC Thermal
resistance,
junction to
case
11.5 18 18 25.7 °C/W 5
—ΨJT Thermal
characteriz
ation
parameter,
junction to
package
top outside
center
(natural
convection)
0.9 3 3 0.4 °C/W 6
1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air)with the single layer board horizontal. Board meets JESD51-9 specification.
2. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air).
3. Determined according to JEDEC Standard JESD51-6, Integrated Circuits Thermal Test Method Environmental
Conditions—Forced Convection (Moving Air) with the board horizontal.
4. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental
Conditions—Junction-to-Board.
5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883
Method 1012.1).
6. Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2.
3 Peripheral operating requirements and behaviors
3.1 Core modules
3.1.1 SWD electricals
Table 13. SWD full voltage range electricals
Symbol Description Min. Max. Unit
Operating voltage 1.71 3.6 V
S1 SWD_CLK frequency of operation
• Serial wire debug
0
33
MHz
S2 SWD_CLK cycle period 1/S1 — ns
S3 SWD_CLK clock pulse width
• Serial wire debug
15
—
ns
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