SN54AHCT16244, SN74AHCT16244
16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCLS334I – MARCH 1996 – REVISED JANUAR Y 2000
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Members of the Texas Instruments
Widebus
Family
D
EPIC
(Enhanced-Performance Implanted
CMOS) Process
D
Inputs Are TTL-Voltage Compatible
D
Distributed VCC and GND Pins Minimize
High-Speed Switching Noise
D
Flow-Through Architecture Optimizes PCB
Layout
D
Latch-Up Performance Exceeds 250 mA Per
JESD 17
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015
D
Package Options Include Plastic Shrink
Small-Outline (DL), Thin Shrink
Small-Outline (DGG), and Thin Very
Small-Outline (DGV) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings
description
The ’AHCT16244 devices are 16-bit buffers and
line drivers designed specifically to improve the
performance and density of 3-state memory
address drivers, clock drivers, and bus-oriented
receivers and transmitters.
These devices can be used as four 4-bit buffers,
two 8-bit buffers, or one 16-bit buffer. They provide
true outputs and symmetrical active-low
output-enable (OE) inputs.
T o ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54AHCT16244 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74AHCT16244 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each 4-bit buffer/driver)
INPUTS OUTPUT
OE AY
L H H
LLL
H X Z
Copyright 2000, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
SN54AHCT16244 . . . WD PACKAGE
SN74AHCT16244 . . . DGG, DGV, OR DL PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1OE
1Y1
1Y2
GND
1Y3
1Y4
VCC
2Y1
2Y2
GND
2Y3
2Y4
3Y1
3Y2
GND
3Y3
3Y4
VCC
4Y1
4Y2
GND
4Y3
4Y4
4OE
2OE
1A1
1A2
GND
1A3
1A4
VCC
2A1
2A2
GND
2A3
2A4
3A1
3A2
GND
3A3
3A4
VCC
4A1
4A2
GND
4A3
4A4
3OE
SN54AHCT16244, SN74AHCT16244
16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCLS334I – MARCH 1996 – REVISED JANUAR Y 2000
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic symbol†
47
1A1 46
1A2 44
1A3 43
1A4
1Y1
2
1Y2
3
1Y3
5
1Y4
6
41
2A1 40
2A2 38
2A3 37
2A4
2Y1
8
2Y2
9
2Y3
11
2Y4
12
36
3A1 35
3A2 33
3A3 32
3A4
3Y1
13
3Y2
14
3Y3
16
3Y4
17
30
4A1 29
4A2 27
4A3 26
4A4
4Y1
19
4Y2
20
4Y3
22
4Y4
23
EN1
1
EN4
24
1OE
2OE
3OE
4OE
EN2
48
EN3
25
†This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
1
1
1
1
1
2
3
4
SN54AHCT16244, SN74AHCT16244
16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCLS334I – MARCH 1996 – REVISED JANUAR Y 2000
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
1OE
1A1
1A2
1A3
1A4
1Y1
1Y2
1Y3
1Y4
1
47
46
44
43
2
3
5
6
2OE
2A1
2A2
2A3
2A4
2Y1
2Y2
2Y3
2Y4
48
41
40
38
37
8
9
11
12
3OE
3A1
3A2
3A3
3A4
3Y1
3Y2
3Y3
3Y4
25
36
35
33
32
13
14
16
17
4OE
4A1
4A2
4A3
4A4
4Y1
4Y2
4Y3
4Y4
24
30
29
27
26
19
20
22
23
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, VO (see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0) –20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO (VO = 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through each VCC or GND ±75 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 2): DGG package 70°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DGV package 58°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DL package 63°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
SN54AHCT16244, SN74AHCT16244
16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCLS334I – MARCH 1996 – REVISED JANUAR Y 2000
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions (see Note 3)
SN54AHCT16244 SN74AHCT16244
UNIT
MIN MAX MIN MAX
UNIT
VCC Supply voltage 4.5 5.5 4.5 5.5 V
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.8 0.8 V
VIInput voltage 0 5.5 0 5.5 V
VOOutput voltage 0 VCC 0 VCC V
IOH High-level output current –8 –8 mA
IOL Low-level output current 8 8 mA
∆t/∆vInput transition rise or fall rate 20 20 ns/V
TAOperating free-air temperature –55 125 –40 85 °C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25°C SN54AHCT16244 SN74AHCT16244
UNIT
PARAMETER
TEST
CONDITIONS
V
CC MIN TYP MAX MIN MAX MIN MAX
UNIT
VOH
IOH = –50
m
A
45V
4.4 4.5 4.4 4.4
V
V
OH IOH = –8 mA
4
.
5
V
3.94 3.8 3.8
V
VOL
IOL = 50
m
A
45V
0.1 0.1 0.1
V
V
OL IOL = 8 mA
4
.
5
V
0.36 0.44 0.44
V
IIVI = VCC or GND 0 V to 5.5 V ±0.1 ±1* ±1
m
A
IOZ VO = VCC or GND 5.5 V ±0.25 ±2.5 ±2.5
m
A
ICC VI = VCC or GND, IO = 0 5.5 V 4 40 40
m
A
∆ICC†One input at 3.4 V,
Other inputs at VCC or GND 5.5 V 1.35 1.5 1.5 mA
CiVI = VCC or GND 5 V 2.5 10 10 pF
CoVO = VCC or GND 5 V 3 pF
* On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V.
†This is the increase in supply current for each input at one of the specified TTL voltage levels rather than 0 V or VCC.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54AHCT16244, SN74AHCT16244
16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCLS334I – MARCH 1996 – REVISED JANUAR Y 2000
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V ±0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM TO LOAD TA = 25°C SN54AHCT16244 SN74AHCT16244
UNIT
PARAMETER
(INPUT) (OUTPUT) CAPACITANCE MIN TYP MAX MIN MAX MIN MAX
UNIT
tPLH
A
Y
CL=15
p
F
5.4* 8.5* 1* 10* 1 9.5
ns
tPHL
A
Y
C
L =
15
pF
5.4* 8.5* 1* 10* 1 9.5
ns
tPZH
OE
Y
CL=15
p
F
7.7* 10.4* 1* 12* 1 12
ns
tPZL
OE
Y
C
L =
15
pF
7.7* 10.4* 1* 12* 1 12
ns
tPHZ
OE
Y
CL=15
p
F
5* 10.4* 1* 12* 1 12
ns
tPLZ
OE
Y
C
L =
15
pF
5* 10.4* 1* 12* 1 12
ns
tPLH
A
Y
CL=50
p
F
7 9.5 1 11 1 10.5
ns
tPHL
A
Y
C
L =
50
pF
5.9 9.5 1 11 1 10.5
ns
tPZH
OE
Y
CL=50
p
F
8.2 11.4 1 13 1 13
ns
tPZL
OE
Y
C
L =
50
pF
8.2 11.4 1 13 1 13
ns
tPHZ
OE
Y
CL=50
p
F
8.8 11.4 1 13 1 13
ns
tPLZ
OE
Y
C
L =
50
pF
8.8 11.4 1 13 1 13
ns
tsk(o) CL = 50 pF 1** 1 ns
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
** On products compliant to MIL-PRF-38535, this parameter does not apply.
noise characteristics, VCC = 5 V, CL = 50 pF, TA = 25°C (see Note 4)
PARAMETER
SN74AHCT16244
UNIT
PARAMETER
MIN TYP MAX
UNIT
VOL(P) Quiet output, maximum dynamic VOL 0.7 V
VOL(V) Quiet output, minimum dynamic VOL –0.7 V
VOH(V) Quiet output, minimum dynamic VOH 4.8 V
VIH(D) High-level dynamic input voltage 2 V
VIL(D) Low-level dynamic input voltage 0.8 V
NOTE 4: Characteristics are for surface-mount packages only.
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
Cpd Power dissipation capacitance No load, f = 1 MHz 8.2 pF
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54AHCT16244, SN74AHCT16244
16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCLS334I – MARCH 1996 – REVISED JANUAR Y 2000
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
50% VCC
3 V
3 V
0 V
0 V
th
tsu
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Data Input
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
3 V
0 V
50% VCC
50% VCC
Input
Out-of-Phase
Output
In-Phase
Output
Timing Input
50% VCC
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Control
Output
W aveform 1
S1 at VCC
(see Note B)
Output
W aveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
≈VCC
0 V
50% VCC VOL + 0.3 V
50% VCC ≈0 V
3 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
Open
VCC
GND
VCC
TEST S1
3 V
0 V
tw
VOLTAGE WAVEFORMS
PULSE DURATION
Input
NOTES: A. CL includes probe and jig capacitance.
B. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
W aveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
From Output
Under Test CL
(see Note A)
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
S1 VCC
RL = 1 kΩGND
From Output
Under Test CL
(see Note A)
Test
Point
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
Open
VOH – 0.3 V
1.5 V 1.5 V
1.5 V
1.5 V 1.5 V
1.5 V 1.5 V1.5 V 1.5 V
Figure 1. Load Circuit and Voltage Waveforms
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
74AHCT16244DGGRE4 ACTIVE TSSOP DGG 48 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
74AHCT16244DGGRG4 ACTIVE TSSOP DGG 48 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
74AHCT16244DGVRE4 ACTIVE TVSOP DGV 48 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
74AHCT16244DGVRG4 ACTIVE TVSOP DGV 48 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
74AHCT16244DLRG4 ACTIVE SSOP DL 48 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AHCT16244DGGR ACTIVE TSSOP DGG 48 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AHCT16244DGVR ACTIVE TVSOP DGV 48 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AHCT16244DL ACTIVE SSOP DL 48 25 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AHCT16244DLG4 ACTIVE SSOP DL 48 25 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AHCT16244DLR ACTIVE SSOP DL 48 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 18-Sep-2008
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74AHCT16244DGGR TSSOP DGG 48 2000 330.0 24.4 8.6 15.8 1.8 12.0 24.0 Q1
SN74AHCT16244DGVR TVSOP DGV 48 2000 330.0 16.4 7.1 10.2 1.6 12.0 16.0 Q1
SN74AHCT16244DLR SSOP DL 48 1000 330.0 32.4 11.35 16.2 3.1 16.0 32.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 11-Aug-2009
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74AHCT16244DGGR TSSOP DGG 48 2000 346.0 346.0 41.0
SN74AHCT16244DGVR TVSOP DGV 48 2000 346.0 346.0 33.0
SN74AHCT16244DLR SSOP DL 48 1000 346.0 346.0 49.0
PACKAGE MATERIALS INFORMATION
www.ti.com 11-Aug-2009
Pack Materials-Page 2
MECHANICAL DATA
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DL (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
4040048/E 12/01
48 PINS SHOWN
56
0.730
(18,54)
0.720
(18,29)
4828
0.370
(9,40)
(9,65)
0.380
Gage Plane
DIM
0.420 (10,67)
0.395 (10,03)
A MIN
A MAX
0.010 (0,25)
PINS **
0.630
(16,00)
(15,75)
0.620
0.010 (0,25)
Seating Plane
0.020 (0,51)
0.040 (1,02)
25
24
0.008 (0,203)
0.0135 (0,343)
48
1
0.008 (0,20) MIN
A
0.110 (2,79) MAX
0.299 (7,59)
0.291 (7,39)
0.004 (0,10)
M
0.005 (0,13)
0.025 (0,635)
0°–ā8°
0.005 (0,13)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MO-118
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUAR Y 1998
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
4040078/F 12/97
48 PINS SHOWN
0,25
0,15 NOM
Gage Plane
6,00
6,20 8,30
7,90
0,75
0,50
Seating Plane
25
0,27
0,17
24
A
48
1
1,20 MAX
M
0,08
0,10
0,50
0°–8°
56
14,10
13,90
48
DIM
A MAX
A MIN
PINS **
12,40
12,60
64
17,10
16,90
0,15
0,05
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
MECHANICAL DATA
MPDS006C – FEBRUAR Y 1996 – REVISED AUGUST 2000
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE
24 PINS SHOWN
14
3,70
3,50 4,90
5,10
20
DIM
PINS **
4073251/E 08/00
1,20 MAX
Seating Plane
0,05
0,15
0,25
0,50
0,75
0,23
0,13
112
24 13
4,30
4,50
0,16 NOM
Gage Plane
A
7,90
7,70
382416
4,90
5,103,70
3,50
A MAX
A MIN
6,60
6,20
11,20
11,40
56
9,60
9,80
48
0,08
M
0,07
0,40
0°–8°
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
IMPORTANT NOTICE
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