2010-2012 Microchip Technology Inc. DS80507D-page 1
PIC18F87K22 FAMILY
The PIC18F87K22 family devices that you have
received conform functionally to the current Device
Data Sheet (DS39960D), except for the anomalies
des c ribed in this docum ent.
The silicon issues discussed in the following pages are
for silicon revisions with the Device and Revision IDs
listed in Table 1. The silicon issues are summarized in
Table 2.
The errata describ ed in this document will be addressed
in future revisions of the PIC18F87K22 family si licon.
Data Sheet clarifications and co rrections st art on page 8,
following the discu ssion of silicon issues .
The silicon revision level can be identified using the
current version of MPLAB® IDE and Microchip’s pro-
grammers, debuggers, and emulation tools, which are
available at the Microchip corporate web site
(www.microchip.com).
For example, to identify the silicon revision level using
MPLAB IDE in conjunction with MPLAB ICD 2 or
PICkit™ 3:
1. Using the appropriate interface, connect the
device to the MPLAB ICD 2 programmer/
debugger or PICkit™ 3.
2. From the main menu in MPLAB IDE, select
Configure>Select Device, and then select the
target part number in the dialog box.
3. Select the MPLAB hardware tool
(Debugger>Se lect Tool).
4. Perform a “Connect” operation to the device
(Debugger>Connect). Depending on the devel-
opment tool used, the part number and Device
Revisio n ID valu e appear in th e Output window.
The DEVREV values for the various PIC18F87K22
family silicon revisions are shown in Table 1.
Note: This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated in the last column of
Table 2 app ly to the current silicon revision
(B3, C1). Note: If you are unable to extract the silicon
revision level, please contact your local
Microchip sales office for assistance.
TABLE 1: SILICON DEVREV VALUES
Part Number Device ID(1)Revision ID for Silicon Revision(2)
A3 B1 B3 C1
PIC18F65K22 530h
3h 4h 5h 10h
PIC18F66K22 52Ch
PIC18F85K22 536h
PIC18F86K22 532h
PIC18F67K22 518h
PIC18F87K22 51Ch
Note 1: The De vice IDs (DEVID and DEVR EV) are locate d at the last two i mplemented addresse s of c onfigurati on
memory space. They are shown in hexadecimal in the format “DEVID DEVREV”.
2: Refer to the “PIC18F 6XKXX/8XKXX Fam ily Fla sh Microc ontroll er Programmi ng Specific ation” (DS39947)
for detailed information on Device and Revision IDs for your specific device.
PIC18F87K22 Family
Silicon Errata and Data Sheet Clarification
PIC18F87K22 FAMILY
DS80507D-page 2 2010-2012 Microchip Technology Inc.
TABLE 2: SILICON ISSUE SUMMARY
Module Feature Item
Number Issue Summary Affected Revis ions (1)
A3 B1 B3 C1
Analog-to-
Digital
Converter A/D Offset 1. The A/D offset is greater than specified in
the data sheet’s A/D Converter
Characte ris tic s t ab le. X
Ports Leakage 2. I/O port leakage is higher than the D060
spec in the data sheet. XXXX
High/Low-
Voltage
Detect HLVD Trip 3. The high-to-low (VDIRMAG = 0) setting of
the HLVD may send initial interrupts. X X X X
ECCP Auto-Shutdown 4.
The tri-state setting of the auto-
shutdown feature in the e nh an ce d PWM
may no t s uccessfull y d r i ve th e pi n to
tri-state.
XXXX
EUSART Synchronous
Transmit 5. When using the Synchronous Transmit
mode of the EUSART, at high baud rates,
transmitted data may become corrupted. XXXX
IPD, IDD Maximum Limit 6. Maximum current limits may be higher
than specified in Table 31-2 of the data
sheet. X
Ultra
Low-Power
Sleep Slee p E ntry 7.
Entering Ultra Low-Power Sleep
mode, by setting RETEN = 0 and
SRETEN = 1, will c aus e the part to not b e
programmable through ICSP™.
XX X
Resets
(BOR) Enable/Disable 8.
An unex pe cted Reset m ay o c cu r i f t he
Brown-o ut Reset modul e (BOR) is
disabled, and then re-enabled, when
the High/Low-V oltage Detection (HL VD)
module is not enabled (HL VDCON<4> = 0).
XXXX
RG5 Pin Leakage 9. RG5 will cause excess pin l eakage
whenever it is driven low. X
External
Memory
Bus (EMB) Wait States 10. The CE signal will not be extended
properly if Wait states are used. X X X X
Note 1: Only those issues indicated in the last two columns apply to the current silicon revision.
2010-2012 Microchip Technology Inc. DS80507D-page 3
PIC18F87K22 FAMILY
Silicon Errata Issues
1. Module: Analog-to-Digital Converter
(A/D)
The A/D will not meet the Microchip standard
A/D specification. The A/D may be usable if
tested at the user end. The possible issues are
high offset error, high DNL error and multiple
missi ng cod es. The A/D can be test ed and use d
for relative measurements.
The A/D issues will be fixed in a future revision
of this par t.
A/D Offset
The A/D may have a high offset error, up to a
maximum of 50 LSB; it can be used if the A/D is
calibrated for the offset.
Work around
Method to Calibrate for Offset:
In Single-Ended mode, connect the A/D +ve
input to ground and take the A/D reading. This
will be the offset of the device and can be used
to comp ensate for the s ubse quent A/D re ad ings
on the actual inputs.
Affected Silicon Revisions
2. Module: Ports
The input leakage will not match the D060
specification in the data sheet. The leakage will
meet the 200 nA specification at TA = 25ºC. At
TA= 85ºC, the lea kag e w il l be up to a maximum
of 2 µA.
Work around
None.
Affected Silicon Revisions
3. Module: High/Low-Voltage Detect (HLVD)
The high-to-low (VDIRMAG = 0) setting of the
HLVD may send ini tial inter rupts. High trip point s
that are close to the intended operating voltage
are susc eptible to this behavior.
Work around
Select a lowe r trip voltage that allo ws con siste nt
start-up or clear any initial interrupts from the
HLVD on start-up.
Affected Silicon Revisions
4. Module: ECCP
The tri-state setting of the a uto-shut down feature
in the enhanced PWM ma y not successfully drive
the pin to tri-state. The pin will remain an output
and should not be driven externally. All tri-state
settings will be affected.
Work around
None.
Affected Silicon Revisions
5. Module: EUSART
When usi ng th e Sy nch r on ous Transmit mode of
the EUSART, at high baud rates, transmitted
data m ay become corrupted. One or more bit s of
the intended transmit message may be
incorrect.
Work around
Since this problem is related to the baud rate
used, adding a fixed delay before loading the
TXREGx may not be a reliable work around.
Lower the baud rate until no errors occur, or
when loading the TXREGx, check that the
TRMT bit inside of the TXSTAx register is set
instead of checking the TXxIF bit.The following
code can be used :
while(!TXSTAxbits.TRMT);
// wait to load TXREGx until TRMT is set
Affected Silicon Revisions
Note: This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated by the shaded column in
the following tables apply to the current
silicon revision (B3, C1).
A3 B1 B3 C1
X
A3 B1 B3 C1
X X X X
A3 B1 B3 C1
X X X X
A3 B1 B3 C1
X X X X
A3 B1 B3 C1
X X X X
PIC18F87K22 FAMILY
DS80507D-page 4 2010-2012 Microchip Technology Inc.
6. Module: IPD and IDD
The IPD and IDD limits will not match the data
sheet. The values, in bold in Section 31.2 “DC
Characteristics: Power-Down and Supply
Current PIC18F87K22 Family (Industrial)”,
reflect the updated silicon maximum limits.
31.2 DC Characteristi cs: Power-Down and Supply Current
PIC18F87K22 Family (Industrial)
PIC18F87K22 Family
(Industrial) Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
Param
No. Device Typ Max Units Conditions
Power-Down Current (IPD)(1)
All devices 10 500 nA -40°C VDD = 1.8V(4)
(Sleep mode)
Regulator Disabled
20 500 nA +25°C
120 600 nA +60°C
630 2000 nA +85°C
All devices 50 700 nA -40°C VDD = 3.3V(4)
(Sleep mode)
Regulator Disabled
60 900 nA +25°C
170 1100 nA +60°C
700 5000 nA +85°C
All devices 350 1300 nA -40°C VDD = 5V(5)
(Sleep mode)
Regulator Enabled
400 1400 nA +25°C
550 1500 nA +60°C
1350 4000 nA +85°C
Supply Current (IDD) Cont.(2,3)
All devices 3.7 8.5 µA -40°C VDD = 1.8V(4)
Regulat or Di sabled
FOSC = 32 kHz(3)
(SEC_RUN mo de,
SOSCSEL = 01)
5.4 10 µA +25°C
6.60 13 µA +85°C
All devices 8.7 18 µ A -40°C VDD = 3.3V(4)
Regulat or Di sabled
10 20 µA +25°C
12 35 µA +85°C
All devices 60 160 µA -40°C VDD = 5V(5)
Regulat or Enabl ed
90 190 µA +25°C
100 240 µA +85°C
Note 1: The power-down current in Sleep mode does not depend on the os cillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in a high-impedance state and tied to VDD or VSS, and all features that add delta
current are disabled (such as WDT, SOSC oscillator, BOR, etc.).
2: The supply current is mainly a function of operat ing volt age, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature
crystals are available at a much higher cost.
4: Voltage regulator disabled (ENVREG = 0, tied to VSS, RET E N (CONFIG1L<0>) = 1).
5: Voltage regulator enabled (ENVREG = 1, tied to VDD, SRETEN (WDTCON<4>) = 1 and RETEN (CONFIG1L<0>) = 0).
2010-2012 Microchip Technology Inc. DS80507D-page 5
PIC18F87K22 FAMILY
Work around
None.
Affected Silicon Revisions
All devices 1.2 4 µ A -40°C VDD = 1.8V(4)
Regulat or Di sabled
FOSC = 32 kHz(3)
(SEC_IDLE mode,
SOSCSEL = 01)
1.7 5 µA +25°C
2.6 6 µA +85°C
All devices 1.6 7 µ A -40°C VDD = 3.3V(4)
Regulat or Di sabled
2.8 9 µA +25°C
4.1 17 µA +85°C
All devices 60 150 µA -40°C VDD = 5V(5)
Regulat or Enabl ed
80 180 µA +25°C
100 240 µA +85°C
31.2 DC Characteristi cs: Power-Down and Supply Current
PIC18F87K22 Family (Industrial) (Continued)
PIC18F87K22 Family
(Industrial) Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
Param
No. Device Typ Max Units Conditions
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in a high-impedance state and tied to VDD or VSS, and all features that add delta
current are disabled (such as WDT, SOSC oscillator, BOR, etc.).
2: The supply current is mainly a function of operat ing volt age, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature
crystals are available at a much higher cost.
4: Voltage regulator disabled (ENVREG = 0, tied to VSS, RETEN (CO NFIG1L<0>) = 1).
5: Voltage regulator enabled (ENVREG = 1, tied to VDD, SRETEN (WDTCON<4>) = 1 and RETEN (CONFIG1L<0>) = 0).
A3 B1 B3 C1
X
PIC18F87K22 FAMILY
DS80507D-page 6 2010-2012 Microchip Technology Inc.
7. Module: Ultra Low-Power Sleep
Entering Ultra Low-Power Sleep mode, by set-
ting RETEN = 0 and SRETEN = 1, will cause
the part to not be programmable through ICSP.
This issue occurs when the RETEN fuse bit in
CONFIG1L<0> is cleared to ‘0’, t he SRETEN bit
in the WDTCON register is set to ‘1’ and a
SLEEP instruction is executed. This happens
within the first 350 µs of code execution or
whene ver the abov e Slee p mod e is entered and
MCLR is disabl ed. Discon tinue use of t he MCLR
disabled RG5 mode if ICSP reprogramming is
necessary.
Work around
Use norm al Sleep and Low-Pow er Sleep modes
only, or on any Reset, ensure that at least
350 µs passes before executing a SLEEP
instruction when ULP is enabled. To ensure the
Ultra Low- Power Sleep mode is not enabled,
the RET EN fu se bit in CONFIG 1L<0> shoul d be
set to a ‘1’, and the SRETEN bit in the WDTCON
register should be cle ared to a ‘0’. The followin g
code can be used:
//This will ensure the RETEN fuse is
set to 1
#pragma config RETEN = OFF
//This will ensure the SRETEN bit is 0
WDTCONbits.SRETEN = 0;
If the Ultra Low-Power Sleep mode is needed,
then the user must ensure that the minimum
time, before the first SLEEP instruction is
executed, is greater than 350 µs.
Affected Silicon Revisions
8. Module: Resets (BOR)
An unex pected R eset may oc cur if the Brow n-
out Reset (BOR) module is disabled, and then
re-enabled when the High/Low-Voltage
Detection (HLVD) module is not enabled
(HLVDCON<4> = 0). This issue affects
BOR modes: BOREN<1:0> = 10 and
BOREN<1:0> = 01. In both of these modes, if the
BOR module is re-enabled while the device is
active, unexpected Resets may be generated.
Work around
If BOR is required, and power consumption is
not an issue, use BOREN<1:0> = 11. For
BOREN<1:0> = 10 mode, either switch to
BOREN<1:0> = 11 mode or enable the HLVD
(HLVDCON<4> = 1) prior to entering Sleep. If
power co nsumption is an issu e and low power is
desired, do not use BOREN<1:0> = 10 mode.
Instead, use BOREN<1:0> = 01 and follow the
steps below when entering and exiting Sleep.
1. Disable BOR by clearing SBOREN
(RCON<6> = 0).
WDTCON bi ts .S BO RE N = 0;
2. Enter Sleep mode (if desired).
Sleep();
3. Aft er exiting Sleep mo de (if e ntered), enabl e the
HLVD (HLVDCON<4> = 1).
HLVDCONbits.HLVDEN = 1;
4. Wait for the internal reference voltage (TIRVST)
to stabilize (typically 25 µs).
while(!HLVDCONbits.IRVST);
5. Re-enable BOR by setting SBOREN
(RCON<6> = 1).
WDTCON bi ts .S BO RE N = 1;
6. Disable the HLVD by clearing HLVDEN
(HLVDCON<4> = 0).
HLVDCONbits.HLVDEN = 0;
Affected Silicon Revisions
A3 B1 B3 C1
X X X
A3 B1 B3 C1
X X X X
2010-2012 Microchip Technology Inc. DS80507D-page 7
PIC18F87K22 FAMILY
9. Module: RG5 Pin
RG5 will cause excess pin leakage whenever it
is driven low. When RG5 is held at 0V, the pin
will typically source an additional 160 µA of
current.
Work around
In power-sensitive applications, using RG5 as
an input, ensure that any input attached to this
pin Idles high.
Affected Silicon Revisions
10. Module: Ext e rn a l Me m o ry Bus (E M B )
The CE signal will not be extended properly if
Wait states are used. The duration of the CE
signal will remain 0 TCY despite the setting in
MEMCON<5:4>.
Work around
None.
Affected Silicon Revisions
A3 B1 B3 C1
X
A3 B1 B3 C1
X X X X
PIC18F87K22 FAMILY
DS80507D-page 8 2010-2012 Microchip Technology Inc.
Data Sheet Clarifications
The foll owing ty pographic corrections and clar ification s
are to be note d fo r the latest version of the device da t a
sheet (DS39960D):
1. Module: Electrical Characteristics
Table 31-27: A/D Converter Characteristics has
been corrected. The chan ges a r e s hown in bold
in the table below:
TABLE 31-27: A/D CONVERTER CHARACTERISTICS: PIC18F87K22 FAMILY (INDUSTRIAL)
Note: Corrections are shown in bold. Where
possible, the original bold text formatting
has been removed for clarity.
Param
No. Sym Characteristic Min Typ Max Units Conditions
A01 NRResolution — — 12 bit VREF 5.0V
A03 EIL I ntegral Linearity Error —±1 ±6.0 LSB VREF 5.0V
A04 EDL Differential Linearity Error —±1 +3.0/-1.0 LSB VREF 5.0V
A06 EOFF Offset Error —±1 ±18.0 LSB VREF 5.0V
A07 EGN Gain Error —±1 ±8.0 LSB VREF 5.0V
A10 — Monotonicity(1) —— —
—VSS VAIN VREF
A20 VREF Reference Voltage Range
(VREFH – VREFL)3—V
DD – VSS V
A21 VREFH Refer ence Voltage High VSS + 3.0V — VDD + 0.3V V
A22 VREFL Refer ence Voltage Low VSS – 0.3V — VDD – 3.0V V
A25 VAIN Analog Input Voltage VREFL —VREFH V
A30 ZAIN Recommended
Impedance of Analog
Voltage Source
——2.5k
A50 IREF VREF Input Current(2) —
——
—5
150 A
ADuring VAIN acquis itio n.
During A/D conv ersion cycl e.
Note 1: The A/D conversion result never decreas es with an increase in the input voltage.
2: VREFH current is from the RA3/AN3/VREF+ pin or VDD, whichever is selected as the V REFH source. VREFL current is from
the RA2/AN2/VREF-/CVREF pin or VSS, whichever is selected as the VREFL source.
2010-2012 Microchip Technology Inc. DS80507D-page 9
PIC18F87K22 FAMILY
2. Module: Voltage Regulator Pins
(ENVREG and VCAP/VDDCORE)
In Section 2.4 “Voltage Regulator Pins (ENVREG and
VCAP/VDDCORE)”, the description of the Regulator
Disabled mode has changed. The changes are shown
in bold below:
When the regu lator is disa ble d, the VCAP/VDDCORE pin
must only be tied to a 0.1 µF capacitor. Refer to
Section 31 .0 “Electri cal Charac terist ics” for inf ormatio n
on VDD and VDDCORE.
3. Module: DC Characteristics
(Injection Current)
The follow ing ta ble of spec ifications fo r current inje cted
into the microcontroller w ill be added to Section 31.0
“Electrical Characteristics”.
31.4 DC Characteristics: PIC18F87K22 Family (Indust rial)
DC CHARACTERISTICS Standard Operating Conditions: 1.8V to 5.5V
Operati ng tem pera ture -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic Min Typ Max Units Conditions
D160a IICL Input Low Inje cti on Curren t 0 — -5(1)mA All pins except VDD, VSS,
AVDD, A VSS, MCLR, VCAP,
SOSCI, SOSCO
D160b IICH Input High Injection Current 0 — +5(1)mA All pins except VDD, VSS,
AVDD, A VSS, MCLR, VCAP,
SOSCI, SOSCO
D160c ÅIICT Total Input Injection Current
(sum of all I/O and control
pins)
-20(1,2)—+20
(1,2)mA Absolute instantaneous
sum of all input injection
currents from all I/O pins
( IICL + IICH) IICT
Note 1: Inje ction currents > 0 can affect the A/D results.
2: Any number and/or combination of I/O pins not excluded under IICL or IICH co ndi tio ns are permit ted.
PIC18F87K22 FAMILY
DS80507D-page 10 2010-2012 Microchip Technology Inc.
APPENDIX A: DOCUMENT
REVISION HISTORY
Rev A Document (6/2010)
Initial release of this document. Silicon issues 1 (A/D),
2 (BOR), 3 (HLVD). and 4 (Ports).
Rev B Document (12/2010)
Removed Silicon issue 2 (Brown-out Reset). Changes
were made to Silicon issue 3 (HLVD). Added Silicon
issues 4 (ECCP), 5 (EUSART) and 6 (IPD and IDD).
Rev C Document (4/2011)
Added silicon issues 7 (Ultra Low-Power Sleep),
8 (Resets – BOR) and 9 (RG5 Pin). Removed data
sheet clarifications 1-3 (Voltage Regulator Pins –
ENVREG and VCAP/VDDCORE). Added data sheet
clarification 1 (Electrical Characteristics).
Rev D Document (2/2012)
Added silicon issue 10 (External Memory Bus – EMB).
Added data sheet clarifications 2 (Voltage Regulator
Pins – ENVREG and VCAP/VDDCORE) and 3 (DC
Characteristics – Injection Current).
2010-2012 Microchip Technology Inc. DS80507D-page 11
Information contained in this publication regarding device
applications a nd the lik e is provided only f or yo ur convenience
and may be supers ed ed by u pda t es . It is y our responsibil it y to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPL AB, PIC , PIC micro, PI C START,
PIC32 logo, rfPIC and UNI/O are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, M XLAB, SE EVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, chipKIT,
chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net,
dsPICworks, dsSPEAK, ECAN, ECONOMONITOR,
FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP,
Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB,
MPLINK, mTouch, Omniscient Code Generation, PICC,
PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE,
rfLAB, Select Mode, Total Endurance , TSHARC,
UniWinDriver, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip T echnology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2010-2012, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-62076-041-3
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that it s family of products is one of the most secure families of it s kind on the market t oday, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is c onstantly evolving. We a t Microc hip are co m mitted to continuously improving the code prot ect ion featur es of our
products. Attempts to break Microchip’ s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and d sPIC® DSCs, KEELOQ® code hopp ing
devices, Serial EEPROMs, microperiph erals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS80507D-page 12 2010-2012 Microchip Technology Inc.
AMERICAS
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
Web Address:
www.microchip.com
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
Boston
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
Chicago
Itasc a , IL
Tel: 630-285-0071
Fax: 630-285-0075
Cleveland
Independence, OH
Tel: 216-447-0464
Fax: 216-447-0643
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
Detroit
Farmington Hills, MI
Tel: 248-538-2250
Fax: 248-538-2260
Indianapolis
Noblesville, IN
Tel: 317-773-8323
Fax: 317-773-5453
Los A n ge les
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
Santa Clara
Santa Clara, CA
Tel: 408-961-6444
Fax: 408-961-6445
Toronto
Mississauga, Ontario,
Canada
Tel: 905-673-0699
Fax: 905-673-6509
ASIA/PACIFIC
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
Hong Kong
Tel: 852-2401-1200
Fax: 852-2401-3431
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
China - Beijing
Tel: 86-10-8569-7000
Fax: 86-10-8528-2104
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
China - Chongqing
Tel: 86-23-8980-9588
Fax: 86-23-8980-9500
China - Hangzhou
Tel: 86-571-2819-3187
Fax: 86-571-2819-3189
China - Hong K ong SAR
Tel: 852-2401-1200
Fax: 852-2401-3431
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
China - Shenzhen
Tel: 86-755-8203-2660
Fax: 86-755-8203-1760
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
ASIA/PACIFIC
India - Bangalore
Tel: 91-80-3090-4444
Fax: 91-80-3090-4123
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11 - 4160-8632
India - Pune
Tel: 91-20-2566-1512
Fax: 91-20-2566-1513
Japan - Osaka
Tel: 81-66-152-7160
Fax: 81-66-152-9310
Japan - Yokohama
Tel: 81-45-471- 6166
Fax: 81-45-471-6122
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
Taiwan - Hsin Chu
Tel: 886-3-5778-366
Fax: 886-3-5770-955
Taiwan - Kaohsiung
Tel: 886-7-536-4818
Fax: 886-7-330-9305
Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
Thailand - Bangko k
Tel: 66-2-694-1351
Fax: 66-2-694-1350
EUROPE
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Cop e nha gen
Tel: 45-4450-2828
Fax: 45-4485-2829
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-14 4-44
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08 -91
UK - Wokingham
Tel: 44-118-921- 5869
Fax: 44-118-921-5820
Worldwide Sales and Service
11/29/11
