74LVC2G86 Dual 2-input EXCLUSIVE-OR gate Rev. 12 -- 15 December 2016 Product data sheet 1. General description The 74LVC2G86 provides a dual 2-input EXCLUSIVE-OR gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 V and 5 V environment. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. 2. Features and benefits Wide supply voltage range from 1.65 V to 5.5 V 5 V tolerant inputs for interfacing with 5 V logic High noise immunity Complies with JEDEC standard: JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8B/JESD36 (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V 24 mA output drive (VCC = 3.0 V) CMOS low-power consumption Latch-up performance exceeds 250 mA Direct interface with TTL levels Inputs accept voltages up to 5 V Multiple package options Specified from 40 C to +85 C and 40 C to +125 C 74LVC2G86 Nexperia Dual 2-input EXCLUSIVE-OR gate 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC2G86DP 40 C to +125 C TSSOP8 plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm SOT505-2 74LVC2G86DC 40 C to +125 C VSSOP8 plastic very thin shrink small outline package; 8 leads; body width 2.3 mm SOT765-1 74LVC2G86GT 40 C to +125 C XSON8 plastic extremely thin small outline package; no leads; 8 terminals; body 1 1.95 0.5 mm SOT833-1 74LVC2G86GF 40 C to +125 C XSON8 extremely thin small outline package; no leads; 8 terminals; body 1.35 1 0.5 mm SOT1089 74LVC2G86GD 40 C to +125 C XSON8 plastic extremely thin small outline package; no leads; 8 terminals; body 3 2 0.5 mm SOT996-2 74LVC2G86GM 40 C to +125 C XQFN8 plastic, extremely thin quad flat package; no leads; 8 terminals; body 1.6 1.6 0.5 mm SOT902-2 74LVC2G86GN 40 C to +125 C XSON8 extremely thin small outline package; no leads; 8 terminals; body 1.2 1.0 0.35 mm SOT1116 74LVC2G86GS 40 C to +125 C XSON8 extremely thin small outline package; no leads; 8 terminals; body 1.35 1.0 0.35 mm SOT1203 4. Marking Table 2. Marking codes Type number Marking code[1] 74LVC2G86DP V86 74LVC2G86DC V86 74LVC2G86GT V86 74LVC2G86GF VH 74LVC2G86GD V86 74LVC2G86GM V86 74LVC2G86GN VH 74LVC2G86GS VH [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 74LVC2G86 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 12 -- 15 December 2016 (c) Nexperia B.V. 2017. All rights reserved 2 of 21 74LVC2G86 Nexperia Dual 2-input EXCLUSIVE-OR gate 5. Functional diagram $ % < $ % < DDK Fig 1. DDK Logic symbol Fig 2. IEC logic symbol % < $ Fig 3. PQD Logic diagram (one driver) 6. Pinning information 6.1 Pinning /9&* $ 9&& % < < % *1' $ /9&* $ 9&& % < < % *1' $ DDE 7UDQVSDUHQWWRSYLHZ DDE Fig 4. Pin configuration SOT505-2 and SOT765-1 74LVC2G86 Product data sheet Fig 5. Pin configuration SOT833-1, SOT1089, SOT1116 and SOT1203 All information provided in this document is subject to legal disclaimers. Rev. 12 -- 15 December 2016 (c) Nexperia B.V. 2017. All rights reserved 3 of 21 74LVC2G86 Nexperia Dual 2-input EXCLUSIVE-OR gate /9&* 9&& % < < % *1' $ % $ $ % < $ < *1' /9&* 9&& WHUPLQDO LQGH[DUHD DDL 7UDQVSDUHQWWRSYLHZ 7UDQVSDUHQWWRSYLHZ Fig 6. DDI Pin configuration SOT996-2 Fig 7. Pin configuration SOT902-2 6.2 Pin description Table 3. Pin description Symbol Pin Description SOT505-2, SOT765-1, SOT833-1, SOT1089, SOT996-2, SOT1116 and SOT1203 SOT902-2 1A, 2A 1, 5 7, 3 data input 1B, 2B 2, 6 6, 2 data input GND 4 4 ground (0 V) 1Y, 2Y 7, 3 1, 5 data output VCC 8 8 supply voltage 7. Functional description Table 4. Function table[1] Input Output nA nB L L L L H H H L H H H L [1] nY H = HIGH voltage level; L = LOW voltage level 74LVC2G86 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 12 -- 15 December 2016 (c) Nexperia B.V. 2017. All rights reserved 4 of 21 74LVC2G86 Nexperia Dual 2-input EXCLUSIVE-OR gate 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage IIK input clamping current VI input voltage IOK output clamping current output voltage VO IO output current ICC supply current IGND ground current Ptot total power dissipation Tstg storage temperature Conditions VI < 0 V [1] Min Max Unit 0.5 +6.5 V 50 - 0.5 +6.5 V mA - 50 Active mode [1][2] 0.5 VCC + 0.5 V Power-down mode [1][2] 0.5 +6.5 V - 50 mA - 100 mA 100 - mA - 300 mW 65 +150 C VO > VCC or VO < 0 V VO = 0 to VCC Tamb = 40 C to +125 C [3] [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation. [3] mA For TSSOP8 packages: above 55 C the value of Ptot derates linearly with 2.5 mW/K. For VSSOP8 packages: above 110 C the value of Ptot derates linearly with 8.0 mW/K. For XSON8 and XQFN8 packages: above 118 C the value of Ptot derates linearly with 7.8 mW/K. 9. Recommended operating conditions Table 6. Operating conditions Symbol Parameter VCC supply voltage VI input voltage VO output voltage Tamb ambient temperature t/V input transition rise and fall rate 74LVC2G86 Product data sheet Conditions Min Max Unit 1.65 5.5 V 0 5.5 V Active mode 0 VCC V VCC = 0 V; Power-down mode 0 5.5 V 40 +125 C VCC = 1.65 V to 2.7 V - 20 ns/V VCC = 2.7 V to 5.5 V - 10 ns/V All information provided in this document is subject to legal disclaimers. Rev. 12 -- 15 December 2016 (c) Nexperia B.V. 2017. All rights reserved 5 of 21 74LVC2G86 Nexperia Dual 2-input EXCLUSIVE-OR gate 10. Static characteristics Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ[1] Max Unit Tamb = 40 C to +85 C VIH VIL VOL VOH HIGH-level input voltage LOW-level input voltage LOW-level output voltage 0.65 VCC - - V VCC = 2.3 V to 2.7 V 1.7 - - V VCC = 2.7 V to 3.6 V 2.0 - - V VCC = 4.5 V to 5.5 V 0.7 VCC - - V VCC = 1.65 V to 1.95 V 0.35 VCC V VCC = 1.65 V to 1.95 V - - VCC = 2.3 V to 2.7 V - - 0.7 V VCC = 2.7 V to 3.6 V - - 0.8 V VCC = 4.5 V to 5.5 V - - IO = 100 A; VCC = 1.65 V to 5.5 V - - 0.1 V IO = 4 mA; VCC = 1.65 V - 0.07 0.45 V IO = 8 mA; VCC = 2.3 V - 0.12 0.3 V 0.3 VCC V VI = VIH or VIL IO = 12 mA; VCC = 2.7 V - 0.17 0.4 V IO = 24 mA; VCC = 3.0 V - 0.33 0.55 V IO = 32 mA; VCC = 4.5 V - 0.39 0.55 V HIGH-level output voltage VI = VIH or VIL IO = 100 A; VCC = 1.65 V to 5.5 V VCC 0.1 - - V IO = 4 mA; VCC = 1.65 V 1.2 1.54 - V IO = 8 mA; VCC = 2.3 V 1.9 2.15 - V IO = 12 mA; VCC = 2.7 V 2.2 2.50 - V IO = 24 mA; VCC = 3.0 V 2.3 2.62 - V IO = 32 mA; VCC = 4.5 V 3.8 4.11 - V - 0.1 1 A II input leakage current IOFF power-off leakage current VI or VO = 5.5 V; VCC = 0 V - 0.1 2 A ICC supply current VI = 5.5 V or GND; VCC = 1.65 V to 5.5 V; IO = 0 A - 0.1 4 A ICC additional supply current per pin; VI = VCC 0.6 V; IO = 0 A; VCC = 2.3 V to 5.5 V - 5 500 A CI input capacitance - 2.5 - pF 74LVC2G86 Product data sheet VI = 5.5 V or GND; VCC = 0 V to 5.5 V All information provided in this document is subject to legal disclaimers. Rev. 12 -- 15 December 2016 (c) Nexperia B.V. 2017. All rights reserved 6 of 21 74LVC2G86 Nexperia Dual 2-input EXCLUSIVE-OR gate Table 7. Static characteristics ...continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Min Typ[1] Max 0.65 VCC - - V VCC = 2.3 V to 2.7 V 1.7 - - V VCC = 2.7 V to 3.6 V 2.0 - - V VCC = 4.5 V to 5.5 V 0.7 VCC - - V VCC = 1.65 V to 1.95 V - - Conditions Unit Tamb = 40 C to +125 C HIGH-level input voltage VIH LOW-level input voltage VIL LOW-level output voltage VOL VOH VCC = 1.65 V to 1.95 V 0.35 VCC V VCC = 2.3 V to 2.7 V - - 0.7 V VCC = 2.7 V to 3.6 V - - 0.8 V VCC = 4.5 V to 5.5 V - - 0.3 VCC V VI = VIH or VIL IO = 100 A; VCC = 1.65 V to 5.5 V - - 0.1 V IO = 4 mA; VCC = 1.65 V - - 0.70 V IO = 8 mA; VCC = 2.3 V - - 0.45 V IO = 12 mA; VCC = 2.7 V - - 0.60 V IO = 24 mA; VCC = 3.0 V - - 0.80 V IO = 32 mA; VCC = 4.5 V - - 0.80 V VCC 0.1 - - V HIGH-level output voltage VI = VIH or VIL IO = 100 A; VCC = 1.65 V to 5.5 V IO = 4 mA; VCC = 1.65 V 0.95 - - V IO = 8 mA; VCC = 2.3 V 1.7 - - V IO = 12 mA; VCC = 2.7 V 1.9 - - V IO = 24 mA; VCC = 3.0 V 2.0 - - V IO = 32 mA; VCC = 4.5 V 3.4 - - V - - 1 A II input leakage current IOFF power-off leakage current VI or VO = 5.5 V; VCC = 0 V - - 2 A ICC supply current VI = 5.5 V or GND; VCC = 1.65 V to 5.5 V; IO = 0 A - - 4 A ICC additional supply current per pin; VI = VCC 0.6 V; IO = 0 A; VCC = 2.3 V to 5.5 V - - 500 A [1] VI = 5.5 V or GND; VCC = 0 V to 5.5 V All typical values are measured at VCC = 3.3 V and Tamb = 25 C. 74LVC2G86 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 12 -- 15 December 2016 (c) Nexperia B.V. 2017. All rights reserved 7 of 21 74LVC2G86 Nexperia Dual 2-input EXCLUSIVE-OR gate 11. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground 0 V); for test circuit see Figure 9. Symbol Parameter 40 C to +85 C Conditions power dissipation capacitance CPD Min Max Min Max VCC = 1.65 V to 1.95 V 1.4 3.8 9.9 1.4 12.4 ns VCC = 2.3 V to 2.7 V 0.8 2.5 5.7 0.8 7.2 ns VCC = 2.7 V 0.8 3.0 5.7 0.8 7.2 ns VCC = 3.0 V to 3.6 V 0.8 2.3 4.7 0.8 5.9 ns VCC = 4.5 V to 5.5 V 0.6 1.9 3.6 0.6 4.5 ns - 15.8 - - - pF [3] per gate; VI = GND to VCC; VCC = 3.3 V output enabled [1] Typical values are measured at Tamb = 25 C and VCC = 1.8 V, 2.5 V, 2.7 V, 3.3 V and 5.0 V respectively. [2] tpd is the same as tPLH and tPHL [3] Unit [2] propagation delay nA, nB to nY; see Figure 8 tpd 40 C to +125 C Typ[1] CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD VCC2 fi N + (CL VCC2 fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (CL VCC2 fo) = sum of outputs. 12. Waveforms 9, 90 Q$Q%LQSXW *1' W 3+/ W 3/+ 92+ Q<RXWSXW 90 92/ PQD Measurement points are given in Table 9. VOL and VOH are typical output voltage levels that occur with the output load. Fig 8. Propagation delay input (nA, nB) to output (nY) 74LVC2G86 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 12 -- 15 December 2016 (c) Nexperia B.V. 2017. All rights reserved 8 of 21 74LVC2G86 Nexperia Dual 2-input EXCLUSIVE-OR gate Table 9. Measurement points Supply voltage Input Output VCC VM VM 1.65 V to 1.95 V 0.5 VCC 0.5 VCC 2.3 V to 2.7 V 0.5 VCC 0.5 VCC 2.7 V 1.5 V 1.5 V 3.0 V to 3.6 V 1.5 V 1.5 V 4.5 V to 5.5 V 0.5 VCC 0.5 VCC 9(;7 9&& * 9, 5/ 92 '87 57 &/ 5/ PQD Test data is given in Table 10. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 9. Table 10. Test circuit for measuring switching times Test data Supply voltage Input Load VEXT VCC VI tr, tf CL RL tPLH, tPHL 1.65 V to 1.95 V VCC 2.0 ns 30 pF 1 k open 2.3 V to 2.7 V VCC 2.0 ns 30 pF 500 open 2.7 V 2.7 V 2.5 ns 50 pF 500 open 3.0 V to 3.6 V 2.7 V 2.5 ns 50 pF 500 open 4.5 V to 5.5 V VCC 2.5 ns 50 pF 500 open 74LVC2G86 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 12 -- 15 December 2016 (c) Nexperia B.V. 2017. All rights reserved 9 of 21 74LVC2G86 Nexperia Dual 2-input EXCLUSIVE-OR gate 13. Package outline 76623SODVWLFWKLQVKULQNVPDOORXWOLQHSDFNDJHOHDGVERG\ZLGWKPPOHDGOHQJWKPP ' ( $ 627 ; F +( \ Y 0 $ = $ $ $ $ SLQLQGH[ /S / H GHWDLO; Z 0 ES PP VFDOH ',0(16,216 PPDUHWKHRULJLQDOGLPHQVLRQV 81,7 $ PD[ $ $ $ ES F ' ( H +( / /S Y Z \ = PP 1RWH 3ODVWLFRUPHWDOSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG 287/,1( 9(56,21 627 5()(5(1&(6 ,(& -('(& -(,7$ (8523($1 352-(&7,21 ,668('$7( Fig 10. Package outline SOT505-2 (TSSOP8) 74LVC2G86 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 12 -- 15 December 2016 (c) Nexperia B.V. 2017. All rights reserved 10 of 21 74LVC2G86 Nexperia Dual 2-input EXCLUSIVE-OR gate 96623SODVWLFYHU\WKLQVKULQNVPDOORXWOLQHSDFNDJHOHDGVERG\ZLGWKPP ' 627 ( $ ; F \ +( Y $ = 4 $ $ $ SLQLQGH[ $ /S GHWDLO; H / Z ES PP VFDOH 'LPHQVLRQV PPDUHWKHRULJLQDOGLPHQVLRQV 8QLW PP $ PD[ PD[ QRP PLQ $ $ $ ' ( ES F H +( / /S 4 Z \ Y = 1RWH 3ODVWLFRUPHWDOSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG 3ODVWLFRUPHWDOSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG 2XWOLQH YHUVLRQ 627 5HIHUHQFHV ,(& -('(& -(,7$ VRWBSR (XURSHDQ SURMHFWLRQ ,VVXHGDWH 02 Fig 11. Package outline SOT765-1 (VSSOP8) 74LVC2G86 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 12 -- 15 December 2016 (c) Nexperia B.V. 2017. All rights reserved 11 of 21 74LVC2G86 Nexperia Dual 2-input EXCLUSIVE-OR gate ;621SODVWLFH[WUHPHO\WKLQVPDOORXWOLQHSDFNDJHQROHDGVWHUPLQDOVERG\[[PP 627 E i / / H H H H i $ $ ' ( WHUPLQDO LQGH[DUHD PP VFDOH ',0(16,216 PPDUHWKHRULJLQDOGLPHQVLRQV 81,7 $ PD[ $ PD[ E ' ( H H / / PP 1RWHV ,QFOXGLQJSODWLQJWKLFNQHVV &DQEHYLVLEOHLQVRPHPDQXIDFWXULQJSURFHVVHV 5()(5(1&(6 287/,1( 9(56,21 ,(& -('(& -(,7$ 627 02 (8523($1 352-(&7,21 ,668('$7( Fig 12. Package outline SOT833-1 (XSON8) 74LVC2G86 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 12 -- 15 December 2016 (c) Nexperia B.V. 2017. All rights reserved 12 of 21 74LVC2G86 Nexperia Dual 2-input EXCLUSIVE-OR gate ;621H[WUHPHO\WKLQVPDOORXWOLQHSDFNDJHQROHDGV WHUPLQDOVERG\[[PP 627 ( WHUPLQDO LQGH[DUHD ' $ $ GHWDLO; i H / i E H WHUPLQDO LQGH[DUHD / ; VFDOH 'LPHQVLRQV 8QLW PP PP $ PD[ QRP PLQ $ E ' ( H / H / 1RWH ,QFOXGLQJSODWLQJWKLFNQHVV 9LVLEOHGHSHQGLQJXSRQXVHGPDQXIDFWXULQJWHFKQRORJ\ VRWBSR 5HIHUHQFHV 2XWOLQH YHUVLRQ ,(& -('(& -(,7$ 627 02 (XURSHDQ SURMHFWLRQ ,VVXHGDWH Fig 13. Package outline SOT1089 (XSON8) 74LVC2G86 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 12 -- 15 December 2016 (c) Nexperia B.V. 2017. All rights reserved 13 of 21 74LVC2G86 Nexperia Dual 2-input EXCLUSIVE-OR gate ;621SODVWLFH[WUHPHO\WKLQVPDOORXWOLQHSDFNDJHQROHDGV WHUPLQDOVERG\[[PP ' % 627 $ $ ( $ GHWDLO; WHUPLQDO LQGH[DUHD H & & $ % & Y Z E H / \ & \ / / ; PP VFDOH 'LPHQVLRQV PPDUHWKHRULJLQDOGLPHQVLRQV 8QLW PP PD[ QRP PLQ $ $ E ' ( H H / / / Y Z \ \ VRWBSR 2XWOLQH YHUVLRQ 5HIHUHQFHV ,(& -('(& -(,7$ (XURSHDQ SURMHFWLRQ ,VVXHGDWH 627 Fig 14. Package outline SOT996-2 (XSON8) 74LVC2G86 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 12 -- 15 December 2016 (c) Nexperia B.V. 2017. All rights reserved 14 of 21 74LVC2G86 Nexperia Dual 2-input EXCLUSIVE-OR gate ;4)1SODVWLFH[WUHPHO\WKLQTXDGIODWSDFNDJHQROHDGV WHUPLQDOVERG\[[PP 627 ; ' % $ WHUPLQDO LQGH[DUHD ( $ $ GHWDLO; H Y Z E & & $ % & \ & \ H WHUPLQDO LQGH[DUHD / N / / N PHWDODUHD QRWIRUVROGHULQJ / / 'LPHQVLRQV 8QLW PP PD[ QRP PLQ PP VFDOH $ $ E ' ( H H / N / / / Y Z \ \ 1RWH 3ODVWLFRUPHWDOSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG 5HIHUHQFHV 2XWOLQH YHUVLRQ ,(& -('(& -(,7$ 627 02 VRWBSR (XURSHDQ SURMHFWLRQ ,VVXHGDWH Fig 15. Package outline SOT902-2 (XQFN8) 74LVC2G86 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 12 -- 15 December 2016 (c) Nexperia B.V. 2017. All rights reserved 15 of 21 74LVC2G86 Nexperia Dual 2-input EXCLUSIVE-OR gate ;621H[WUHPHO\WKLQVPDOORXWOLQHSDFNDJHQROHDGV WHUPLQDOVERG\[[PP 627 E i / / H H H H i $ $ ' ( WHUPLQDO LQGH[DUHD VFDOH 'LPHQVLRQV 8QLW PP PP $ $ E ' ( H / H PD[ QRP PLQ / 1RWH ,QFOXGLQJSODWLQJWKLFNQHVV 9LVLEOHGHSHQGLQJXSRQXVHGPDQXIDFWXULQJWHFKQRORJ\ VRWBSR 5HIHUHQFHV 2XWOLQH YHUVLRQ ,(& -('(& -(,7$ 627 (XURSHDQ SURMHFWLRQ ,VVXHGDWH Fig 16. Package outline SOT1116 (XSON8) 74LVC2G86 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 12 -- 15 December 2016 (c) Nexperia B.V. 2017. All rights reserved 16 of 21 74LVC2G86 Nexperia Dual 2-input EXCLUSIVE-OR gate ;621H[WUHPHO\WKLQVPDOORXWOLQHSDFNDJHQROHDGV WHUPLQDOVERG\[[PP 627 E i / / H H H H i $ $ ' ( WHUPLQDO LQGH[DUHD VFDOH 'LPHQVLRQV 8QLW PP PP $ $ E ' ( H / H / PD[ QRP PLQ 1RWH ,QFOXGLQJSODWLQJWKLFNQHVV 9LVLEOHGHSHQGLQJXSRQXVHGPDQXIDFWXULQJWHFKQRORJ\ VRWBSR 5HIHUHQFHV 2XWOLQH YHUVLRQ ,(& -('(& -(,7$ 627 (XURSHDQ SURMHFWLRQ ,VVXHGDWH Fig 17. Package outline SOT1203 (XSON8) 74LVC2G86 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 12 -- 15 December 2016 (c) Nexperia B.V. 2017. All rights reserved 17 of 21 74LVC2G86 Nexperia Dual 2-input EXCLUSIVE-OR gate 14. Abbreviations Table 11. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 15. Revision history Table 12. Revision history Document ID Release date Data sheet status Change notice Supersedes 74LVC2G86 v.12 20161215 Product data sheet - 74LVC2G86 v.11 Modifications: 74LVC2G86 v.11 Modifications: 74LVC2G86 v.10 Modifications: 74LVC2G86 v.9 Modifications: * Table 7: The maximum limits for leakage current and supply current have changed. 20130408 * 74LVC2G86 v.10 Product data sheet - 74LVC2G86 v.9 For type number 74LVC2G86GM the sot code has changed to SOT902-2. 20111125 * - For type number 74LVC2G86GD XSON8U has changed to XSON8. 20120521 * Product data sheet Product data sheet - 74LVC2G86 v.8 Legal pages updated. 74LVC2G86 v.8 20101019 Product data sheet - 74LVC2G86 v.7 74LVC2G86 v.7 20080613 Product data sheet - 74LVC2G86 v.6 74LVC2G86 v.6 20080222 Product data sheet - 74LVC2G86 v.5 74LVC2G86 v.5 20070907 Product data sheet - 74LVC2G86 v.4 74LVC2G86 v.4 20061013 Product data sheet - 74LVC2G86 v.3 74LVC2G86 v.3 20050207 Product data sheet - 74LVC2G86 v.2 74LVC2G86 v.2 20041018 Product specification - 74LVC2G86 v.1 74LVC2G86 v.1 20030825 Product specification - - 74LVC2G86 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 12 -- 15 December 2016 (c) Nexperia B.V. 2017. All rights reserved 18 of 21 74LVC2G86 Nexperia Dual 2-input EXCLUSIVE-OR gate 16. Legal information 16.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term `short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. 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This document supersedes and replaces all information supplied prior to the publication hereof. 74LVC2G86 Product data sheet Suitability for use -- Nexperia products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of a Nexperia product can reasonably be expected to result in personal injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. Nexperia makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using Nexperia products, and Nexperia accepts no liability for any assistance with applications or customer product design. It is customer's sole responsibility to determine whether the Nexperia product is suitable and fit for the customer's applications and products planned, as well as for the planned application and use of customer's third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. Nexperia does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer's applications or products, or the application or use by customer's third party customer(s). Customer is responsible for doing all necessary testing for the customer's applications and products using Nexperia products in order to avoid a default of the applications and the products or of the application or use by customer's third party customer(s). Nexperia does not accept any liability in this respect. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale -- Nexperia products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nexperia.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. Nexperia hereby expressly objects to applying the customer's general terms and conditions with regard to the purchase of Nexperia products by customer. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. All information provided in this document is subject to legal disclaimers. Rev. 12 -- 15 December 2016 (c) Nexperia B.V. 2017. All rights reserved 19 of 21 74LVC2G86 Nexperia Dual 2-input EXCLUSIVE-OR gate Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products -- Unless this data sheet expressly states that this specific Nexperia product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. Nexperia accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia's warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond Nexperia's specifications such use shall be solely at customer's own risk, and (c) customer fully indemnifies Nexperia for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond Nexperia's standard warranty and Nexperia's product specifications. Translations -- A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com 74LVC2G86 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 12 -- 15 December 2016 (c) Nexperia B.V. 2017. All rights reserved 20 of 21 Nexperia 74LVC2G86 Dual 2-input EXCLUSIVE-OR gate 18. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 (c) General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 5 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 18 Legal information. . . . . . . . . . . . . . . . . . . . . . . 19 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 19 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Contact information. . . . . . . . . . . . . . . . . . . . . 20 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Nexperia B.V. 2017. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 15 December 2016