DS90LV031A
3V LVDS Quad CMOS Differential Line Driver
General Description
The DS90LV031Ais a quad CMOS differential line driver de-
signed for applications requiring ultra low power dissipation
and high data rates. The device is designed to support data
rates in excess of 400 Mbps (200 MHz) utilizing Low Voltage
Differential Signaling (LVDS) technology.
The DS90LV031A accepts low voltage TTL/CMOS input lev-
els and translates them to low voltage (350 mV) differential
output signals. In addition the driver supports a TRI-STATE®
function that may be used to disable the output stage, dis-
abling the load current, and thus dropping the device to an
ultra low idle power state of 13 mW typical.
The EN and EN* inputs allow active Low or active High con-
trol of the TRI-STATE outputs. The enables are common to
all four drivers. The DS90LV031A and companion line re-
ceiver (DS90LV032A) provide a new alternative to high
power psuedo-ECL devices for high speed point-to-point in-
terface applications.
Features
n>400 Mbps (200 MHz) switching rates
n0.1 ns typical differential skew
n0.4 ns maximum differential skew
n2.0 ns maximum propagation delay
n3.3V power supply design
n±350 mV differential signaling
nLow power dissipation, (13mV at 3.3V static)
nInteroperable with existing 5V LVDS devices
nCompatible with IEEE 1596.3 SCI LVDS standard
nCompatible with TIA/EIA-644 LVDS standard
nIndustrial operating temp. range (−40˚C to +85˚C)
nAvailable in surface mount packaging (SOIC)
Connection Diagram Functional Diagram
Truth Table DRIVER
Enables Input Outputs
EN EN*D
IN
D
OUT+
D
OUT−
LHXZZ
All other combinations of
ENABLE inputs LLH
HHL
TRI-STATE®is a registered trademark of National Semiconductor Corporation.
Dual-In-Line
DS100095-1
Order Number DS90LV031ATM
See NS Package Number M16A
DS100095-2
November 1997
DS90LV031A 3V LVDS Quad CMOS Differential Line Driver
© 1997 National Semiconductor Corporation DS100095 www.national.com
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
CC
) −0.3V to +4V
Input Voltage (D
IN
) −0.3V to (V
CC
+ 0.3V)
Enable Input Voltage (EN, EN*) −0.3V to (V
CC
+ 0.3V)
Output Voltage (D
OUT+
,D
OUT−
) −0.3V to (V
CC
+ 0.3V)
Short Circuit Duration
(D
OUT+
,D
OUT−
) Continuous
Maximum Package Power Dissipation @+25˚C
M Package 1088 mW
Derate M Package 8.5 mW/˚C above +25˚C
Storage Temperature Range −65˚C to +150˚C
Lead Temperature Range
Soldering (4 sec.) +260˚C
Maximum Junction Temperature +150˚C
ESD Rating
(HBM, 1.5 kΩ, 100 pF) ≥6 kV (Note 10)
Recommended Operating
Conditions
Min Typ Max Units
Supply Voltage (V
CC
) +3.0 +3.3 +3.6 V
Operating Free Air
Temperature (T
A
) −40 +25 +85 ˚C
Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified. (Note 2) (Note 3) (Note 4)
Symbol Parameter Conditions Pin Min Typ Max Units
V
OD1
Differential Output Voltage R
L
=100Ω(
Figure 1
)D
OUT−
D
OUT+
250 350 450 mV
∆V
OD1
Change in Magnitude of V
OD1
for Complementary Output
States
4 35 |mV|
V
OS
Offset Voltage 1.125 1.25 1.375 V
∆V
OS
Change in Magnitude of V
OS
for Complementary Output
States
5 25 |mV|
V
OH
Output Voltage High 1.38 1.6 V
V
OL
Output Voltage Low 0.90 1.03 V
V
IH
Input Voltage High D
IN
, EN,
EN* 2.0 V
CC
V
V
IL
Input Voltage Low GND 0.8 V
I
IH
Input Current V
IN
=V
CC
or 2.5V −10 ±1 +10 µA
I
IL
Input Current V
IN
=GND or 0.4V −10 ±1 +10 µA
V
CL
Input Clamp Voltage I
CL
=−18 mA −1.5 −0.8 V
I
OS
Output Short Circuit Current ENABLED, (Note 11)
D
IN
=V
CC
,D
OUT+
=0Vor
D
IN
= GND, D
OUT−
=0V
D
OUT−
D
OUT+
−6.0 −9.0 mA
I
OSD
Differential Output Short
Circuit Current ENABLED, V
OD
=0V
(Note 11) −6.0 −9.0 mA
I
OFF
Power-off Leakage V
OUT
=0V or 3.6V, V
CC
=
0V, or Open −20 ±1 +20 µA
I
OZ
Output TRI-STATE Current EN = 0.8V and EN* = 2.0V
V
OUT
=0V or V
CC
−10 ±1 +10 µA
I
CC
No Load Supply current
Drivers Enabled D
IN
=V
CC
or GND V
CC
5.0 8.0 mA
I
CCL
Loaded Supply Current
Drivers Enabled R
L
= 100ΩAll Channels, D
IN
=V
CC
or GND (all inputs) 23 30 mA
I
CCZ
No Load Supply Current
Drivers Disabled D
IN
=V
CC
or GND, EN =
GND, EN* = V
CC
2.6 6.0 mA
www.national.com 2
Switching Characteristics
V
CC
=+3.3V ±10%,T
A
=−40˚C to +85˚C (Note 3) (Note 9) (Note 12)
Symbol Parameter Conditions Min Typ Max Units
t
PHLD
Differential Propagation
Delay High to Low R
L
=100Ω,C
L
=10 pF
(
Figure 2
and
Figure 3
)0.8 1.18 2.0 ns
t
PLHD
Differential Propagation
Delay Low to High 0.8 1.25 2.0 ns
t
SKD1
Differential Pulse Skew
|t
PHLD
−t
PLHD
|(Note 5) 0 0.07 0.4 ns
t
SKD2
Channel to Channel Skew
(Note 6) 0 0.1 0.5 ns
t
SKD3
Differential Part to Part
Skew(Note 7) 0 1.0 ns
t
SKD4
Differential Part to Part
Skew(Note 8) 0 1.2 ns
t
TLH
Rise Time 0.38 1.5 ns
t
THL
Fall Time 0.40 1.5 ns
t
PHZ
Disable Time High to Z R
L
= 100Ω,C
L
=10pF
(
Figures 4, 5
)5ns
t
PLZ
Disable Time Low to Z 5 ns
t
PZH
Enable Time Z to High 7 ns
t
PZL
Enable Time Z to Low 7 ns
f
MAX
(Note 14) 250 MHz
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the de-
vices should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.
Note 2: Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except: VOD1 and
∆VOD1.
Note 3: All typicals are given for: VCC =+3.3V, TA=+25˚C.
Note 4: The DS90LV031A is a current mode device and only functions within datasheet specifications whaen a resistive load is applied to the driver outputs
typical range is (90Ωto 110Ω)
Note 5: tSKD1,|tPHLD −t
PLHD | is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge
of the same channel.
Note 6: tSKD2 is the Differential Channel to Channel Skew of any event on the same device.
Note 7: tSKD3, Differential Part to Part Skew is defined as the difference between the minimum and maximum specified differential propagation delays. This
specification applies to devices at the same VCC and within 5˚C of each other within the operating temperature range.
Note 8: tSKD4, part to part skew, is the differential channel to channel skew of any event between devices. This specification applies to devices over recom-
mended operating termperature and voltage ranges, and across process distribution. tSKD4 is defined as |Max − Min| differential propagation delay.
Note 9: Generator waveform for all tests unless otherwise specified: f =1 MHz, ZO=50Ω,t
r≤1 ns, and t f≤1 ns.
Note 10: ESD Ratings:
HBM (1.5 kΩ, 100 pF) ≥6kV
Note 11: Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only.
Note 12: CLincludes probe and jig capacitance.
Note 13: All input voltages are for one channel unless otherwise specified. Other inputs are set to GND.
Note 14: fMAX generator input conditions: tr=tf <1ns, (0%to 100%), 50%duty cycle, 0V to 3V. Output Criteria: duty cycle =45%/55
%
, VOD>250mV, all
channels switching.
Parameter Measurement Information
DS100095-3
FIGURE 1. Driver V
OD
and V
OS
Test Circuit
3 www.national.com
Parameter Measurement Information (Continued)
DS100095-4
FIGURE 2. Driver Propagation Delay and Transition Time Test Circuit
DS100095-5
FIGURE 3. Driver Propagation Delay and Transition Time Waveforms
DS100095-6
FIGURE 4. Driver TRI-STATE Delay Test Circuit
www.national.com 4
Parameter Measurement Information (Continued)
Typical Application
Applications Information
General application guidelines and hints for LVDS drivers
and receivers may be found in the following application
notes: LVDS Owner’s Manual (lit #550062-001), AN808,
AN1035, AN977, AN971, AN916, AN805, AN903.
LVDS drivers and receivers are intended to be primarily used
in an uncomplicated point-to-point configuration as is shown
in
Figure 6
. This configuration provides a clean signaling en-
vironment for the quick edge rates of the drivers. The re-
ceiver is connected to the driver through a balanced media
which may be a standard twisted pair cable, a parallel pair
cable, or simply PCB traces. Typically, the characteristic dif-
ferential impedance of the media is in the range of 100Ω.A
termination resistor of 100Ωshould be selected to match the
media, and is located as close to the receiver input pins as
possible. The termination resistor converts the current
sourced by the driver into a voltage that is detected by the re-
ceiver. Other configurations are possible such as a
multi-receiver configuration, but the effects of a mid-stream
connector(s), cable stub(s), and other impedance disconti-
nuities as well as ground shifting, noise margin limits, and to-
tal termination loading must be taken into account.
The DS90LV031A differential line driver is a balanced cur-
rent source design. A current mode driver, generally speak-
ing has a high output impedance and supplies a constant
current for a range of loads (a voltage mode driver on the
other hand supplies a constant voltage for a range of loads).
Current is switched through the load in one direction to pro-
duce a logic state and in the other direction to produce the
other logic state. The output current is typically 3.5 mA, a
minimum of 2.5 mA, and a maximum of 4.5 mA. The current
mode requires (as discussed above) that a resistive termi-
nation be employed to terminate the signal and to complete
the loop as shown in
Figure 6
. AC or unterminated configu-
rations are not allowed. The 3.5 mAloop current will develop
a differential voltage of 350 mV across the 100Ωtermination
resistor which the receiver detects with a 250 mV minimum
differential noise margin neglecting resistive line losses
(driven signal minus receiver threshold (350 mV–100 mV =
250 mV)). The signal is centered around +1.2V (Driver Off-
set, V
OS
) with respect to ground as shown in
Figure 7
. Note
that the steady-state voltage (V
SS
) peak-to-peak swing is
twice the differential voltage (V
OD
) and is typically 680 mV.
The current mode driver provides substantial benefits over
voltage mode drivers, such as an RS-422 driver. Its quies-
cent current remains relatively flat versus switching fre-
quency. Whereas the RS-422 voltage mode driver increases
exponentially in most case between 20 MHz–50 MHz. This
is due to the overlap current that flows between the rails of
the device when the internal gates switch. Whereas the cur-
rent mode driver switches a fixed current between its output
without any substantial overlap current. This is similar to
some ECL and PECL devices, but without the heavy static
I
CC
requirements of the ECL/PECL designs. LVDS requires
>80%less current than similar PECL devices. AC specifica-
tions for the driver are a tenfold improvement over other ex-
isting RS-422 drivers.
DS100095-7
FIGURE 5. Driver TRI-STATE Delay Waveform
DS100095-8
FIGURE 6. Point-to-Point Application
5 www.national.com
Applications Information (Continued)
The TRI-STATE function allows the driver outputs to be dis-
abled, thus obtaining an even lower power state when the
transmission of data is not required.
The footprint of the DS90LV031Ais the same as the industry
standard 26LS31 Quad Differential (RS-422) Driver and is a
step down replacement for the 5V DS90C031 Quad Driver.
Power Decoupling Recommendations:
Bypass capacitors must be used on power pins. High fre-
quency ceramic (surface mount is recommended) 0.1uF in
parallel with 0.01uF, in parallel with 0.001uF at the power
supply pin as well as scattered capacitors over the printed
circuit board. Multiple vias should be used to connect the de-
coupling capacitors to the power planes. A 10uF (35V) or
greater solid tantalum capacitor should be connected at the
power entry point on the printed circuit board.
PC Board considerations:
Use at least 4 PCB layers (top to bottom); LVDS signals,
ground, power, TTL signals.
Isolate TTL signals from LVDS signals, otherwise the TTL
may couple onto the LVDS lines. It is best to put TTL and
LVDS signals on different layers which are isolated by a
power/ground plane(s).
Keep drivers and receivers as close to the (LVDS port side)
connectors as possible.
Differential Traces:
Use controlled impedance traces which match the differen-
tial impedance of your transmission medium (ie. cable) and
termination resistor. Run the differential pair trace lines as
close together as possible as soon as they leave the IC
(stubs should be <10mm long). This will help eliminate re-
flections and ensure noise is coupled as common mode. In
fact, we have seen that differential signals which are 1mm
apart radiate far less noise than traces 3mm apart since
magnetic field cancellation is much better with the closer
traces. Plus, noise induced on the differential lines is much
more likely to appear as common mode which is rejected by
the receiver.
Match electrical lengths between traces to reduce skew.
Skew between the signals of a pair means a phase differ-
ence between signals which destroys the magnetic field can-
cellation benefits of differential signals and EMI will result.
(Note the velocity of propagation, v = c/Er where c (the
speed of light) = 0.2997mm/ps or 0.0118 in/ps). Do not rely
solely on the autoroute function for differential traces. Care-
fully review dimensions to match differential impedance and
provide isolation for the differential lines. Minimize the num-
ber or vias and other discontinuities on the line.
Avoid 90˚ turns (these cause impedance discontinuities).
Use arcs or 45˚ bevels.
Within a pair of traces, the distance between the two traces
should be minimized to maintain common mode rejection of
the receivers. On the printed circuit board, this distance
should remain constant to avoid discontinuities in differential
impedance. Minor violations at connection points are allow-
able.
Termination:
Use a resistor which best matches the differential impedance
or your transmission line. The resistor should be between
90Ωand 130Ω. Remember that the current mode outputs
need the termination resistor to generate the differential volt-
age. LVDS will not work without resistor termination. Typi-
cally, connect a single resistor across the pair at the receiver
end.
Surface mount 1%to 2%resistors are best. PCB stubs,
component lead, and the distance from the termination to the
receiver inputs should be minimized. The distance between
the termination resistor and the receiver should be <7mm
(12mm MAX).
Probing LVDS Transmission Lines:
Always use high impedance (100kΩ), low capacitance
(<2pF) scope probes with a wide bandwidth (3GHz) scope.
Improper probing will give deceiving results.
Cables and Connectors, General Comments:
When choosing cable and connectors for LVDS it is impor-
tant to remember:
Use controlled impedance media. The cables and connec-
tors you use should have a matched differential impedance
of about 100Ω. They should not introduce major impedance
discontinuities.
Balanced cables (e.g. twisted pair) are usually better than
unbalanced cables (ribbon cable, simple coax.) for noise re-
duction and signal quality. Balanced cables tend to generate
less EMI due to field canceling effects and also tend to pick
up electromagnetic radiation a common mode (not differen-
tial mode) noise which is rejected by the receiver. For cable
distances <0.5M, most cables can be made to work effec-
tively. For distances 0.5M≤d≤10M, CAT 3 (category 3)
twisted pair cable works well, is readily available and rela-
tively inexpensive. For distances 10M, CAT 5 twisted pair is
recommended.
Contacts for Cables/Connectors:
Mfg. Phone#
3M 1-800-225-5373
Belden 1-800-235-3361
The receiver also supports a fail-safe feature which provides
a stable (known state) high output voltage for any of the fol-
lowing conditions:
1. Open Input Pins. The DS90LV032A is a quad receiver
device, and if an application requires only 1, 2 or 3 re-
ceivers, the unused channel(s) inputs should be left
OPEN. Do not tie unused receiver inputs to ground or
other voltages. The internal circuitry will guarantee a
high, stable output state.
2. Terminated Input. If the driver is in a TRI-STATE condi-
tion, or if the driver is in a power-off condition, or if the
driver is even disconnected (cable unplugged), the re-
ceiver output will again be in a high state, even with the
end of cable 100Ωtermination resistor across the input
pins.
3. Shorted Inputs. If a cable fault condition occurs that
shorts the twisted pair conductors together, thus result-
ing in a 0V differential input voltage to the receiver, the
receiver output will remain in a high state.
www.national.com 6
Applications Information (Continued)
Pin Descriptions
Pin No. Name Description
1, 7, 9, 15 D
IN
Driver input pin, TTL/CMOS
compatible
2, 6, 10,
14 D
OUT+
Non-inverting driver output pin,
LVDS levels
3, 5, 11,
13 D
OUT−
Inverting driver output pin, LVDS
levels
4 EN Active high enable pin, OR-ed
with EN*
12 EN*Active low enable pin, OR-ed
with EN
16 V
CC
Power supply pin, +3.3V ±0.3V
8 GND Ground pin
Ordering Information
Operating Package Type/ Order Number
Temperature Number
−40˚C to +85˚C SOP/M16A DS90LV031ATM
DS100095-9
FIGURE 7. Driver Output Levels
DS100095-10
FIGURE 8. Typical DS90LV031A, D
OUT
(single ended)
vs R
L
,T
A
= 25˚C
DS100095-11
FIGURE 9. Typical DS90LV031A, D
OUT
vs R
L
,
V
CC
= 3.3V, T
A
= 25˚C
7 www.national.com
Physical Dimensions inches (millimeters) unless otherwise noted
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16-Lead (0.150" Wide) Molded Small Outline Package, JEDEC
Order Number DS90LV031ATM
NS Package Number M16A
DS90LV031A 3V LVDS Quad CMOS Differential Line Driver
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