N EW! -3 S peeds ACTTM 3 Field Programmable Gate Arrays Features * Highly Predictable Performance with 100% Automatic Placement and Routing * 7.5 ns Clock-to-Output Times * Up to 250 MHz On-Chip Performance * Up to 228 User-Programmable I/O Pins * Four Fast, Low-Skew Clock Networks * More Than 500 Macro Functions * Up to 10,000 Gate Array Equivalent Gates (up to 25,000 equivalent PLD Gates) * * * * * * * * Replaces up to twenty 32 macro-cell CPLDs Replaces up to one hundred 20-pin PAL(R) Packages Up to 1153 Dedicated Flip-Flops I/O Drive to 12 mA VQFP, TQFP, BGA, and PQFP Packages Nonvolatile, User Programmable Low-power 0.8 micron CMOS Technology Fully Tested Prior to Shipment Product Family Profile Device A1415A A1425A A1440A A1460A A14100A 1,500 3,750 40 15 2,500 6,250 60 25 4,000 10,000 100 40 6,000 15,000 150 60 10,000 25,000 250 100 Logic Modules S-Module C-Module 200 104 96 310 160 150 564 288 276 848 432 416 1,377 697 680 Dedicated Flip-Flops1 264 360 568 768 1,153 User I/Os (maximum) 80 100 140 168 228 100 84 100 -- 100 -- -- -- 133 84 100, 160 -- 100 -- -- 132 175 84 160 -- 100 176 -- -- 207 -- 160, 208 -- -- 176 225 196 257 -- -- 208 -- -- 313 256 108 MHz 63 MHz 110 MHz 250 MHz 250 MHz 7.5 ns 108 MHz 63 MHz 110 MHz 250 MHz 250 MHz 7.5 ns 100 MHz 63 MHz 110 MHz 250 MHz 250 MHz 8.5 ns 97 MHz 63 MHz 110 MHz 200 MHz 200 MHz 9.0 ns 93 MHz 63 MHz 105 MHz 200 MHz 200 MHz 9.5 ns Capacity Gate Array Equivalent Gates PLD Equivalent Gates TTL Equivalent Packages (40 gates) 20-Pin PAL Equivalent Packages (100 gates) 2 Packages (by pin count) CPGA PLCC PQFP RQFP VQFP TQFP BGA CQFP Performance3 (maximum, worst-case commercial) Chip-to-Chip4 Accumulators (16-bit) Loadable Counter (16-bit) Prescaled Loadable Counters (16-bit) Datapath, Shift Registers Clock-to-Output (pad-to-pad) Notes: 1. One flip-flop per S-Module, two flip-flops per I/O-Module. A14100A-3. 2. See product plan on page 1-156 for package availability. Ma y 1 9 9 5 (c) 1995 Actel Corporation 3. Based on A1415A-3, A1425A-3, A1440A-3, A1460A-3, and 4. Clock-to-Output + Setup 1-153 1 Description PLICE(R) The ACT 3 family, based on Actel's proprietary antifuse technology and 0.8-micron double-metal, double-poly CMOS process, offers a high-performance programmable solution capable of 250 MHz on-chip performance and 7.5 nanosecond clock-to-output speeds. The ACT 3 family spans capacities from 1,500 to 10,000 gate array equivalent gates (up to 25,000 PLD gates), and offers very high pin-to-gate ratios, with up to 228 user I/Os for 10,000 gate designs. Predictable Performance* (Worst-Case Commercial) Accumulators (16-bit) 58-63 MHz Loadable Counters (16-bit) 95-110 MHz Prescaled Loadable Counters (16-bit) 230-250 MHz Shift Registers 250-250 MHz The ACT 3 family represents the third generation of Actel Field Programmable Gate Arrays (FPGAs). The family improves on the proven ACT 2 family two-module architecture, consisting of combinatorial and sequential-combinatorial logic modules. The ACT 3 family offers registered I/O modules delivering 9 ns clock-to-out times. The devices contain four clock distribution networks, including dedicated array and I/O clocks, supporting very fast synchronous and asynchronous designs. In addition, routed clocks can be used to drive high fanout signals like resets or output enables, reducing buffering requirements. The ACT 3 family is supported by the Designer and Designer Advantage systems, allowing logic design implementation with minimum effort. The systems offer Microsoft(R) WindowsTM and X WindowTM graphical user interfaces and integrate with the resident CAE system to provide a complete gate array design environment: schematic capture, simulation, fully automatic placement and routing, timing verification and device programming. The systems also include the ACTmapTM optimization and synthesis tool, and the ACTgenTM Macro Builder, a powerful macro function generator for counters, adders, and other structured blocks. The systems are available for 386/486/Pentium PCs and for HPTM, and SunTM workstations running Viewlogic(R), Mentor Graphics(R), and OrCADTM tools. Chip-to-Chip Performance Chip #1 Chip #2 I/O Module I/O Module 35 pF I/O CLK I/O CLK tCKHS tTRACE tINSU Chip-to-Chip Performance (Worst-Case Commercial) tCKHS tTRACE tINSU Total MHz A1425A-3 7.5 1.0 1.8 10.3 ns 97 A1460A-3 9.0 1.0 1.3 11.3 ns 88 1-154 A C T TM 3 F i e l d P ro g ra m m a b l e Gate Arrays Ordering Information A1425 A - PQ 160 C Application (Temperature Range) C = Commercial (0 to +70C) I = Industrial (-40 to +85C) M = Military (-55 to +125C) B = MIL-STD-883 1 Package Lead Count Package Type PG = Ceramic Pin Grid Array PL = Plastic Leaded Chip Carrier PQ = Plastic Quad Flatpack RQ = Plastic Power Quad Flatpack VQ = Very Thin (1.0 mm) Quad Flatpack TQ = Thin (1.4 mm) Quad Flatpack CQ = Ceramic Quad Flatpack BG = Plastic Ball Grid Array Speed Grade Std = Standard Speed -1 = Approximately 15% faster than Standard -2 = Approximately 25% faster than Standard -3 = Approximately 35% faster than Standard Die Revision Part Number A1415 A1425 A1440 A1460 A14100 = = = = = 1500 Gates 2500 Gates 4000 Gates 6000 Gates 10000 Gates 1-155 Product Plan 1 Speed Grade* Application Std -1 -2 -3 C I M B E P P P P -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- P -- -- -- P P -- -- -- -- -- -- -- -- P P P P P -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- P -- -- -- -- P P -- -- -- -- -- -- -- -- -- -- P P P -- -- P -- -- -- P -- P -- P -- -- -- -- A1415A Device 84-pin Plastic Leaded Chip Carrier (PLCC) 100-pin Plastic Quad Flatpack (PQFP) 100-pin Very Thin Quad Flatpack (VQFP) 100-pin Ceramic Pin Grid Array (CPGA) A1425A Device 84-pin Plastic Leaded Chip Carrier (PLCC) 100-pin Plastic Quad Flatpack (PQFP) 100-pin Very Thin Quad Flatpack (VQFP) 132-pin Ceramic Quad Flatpack (CQFP) 133-pin Ceramic Pin Grid Array (CPGA) 160-pin Plastic Quad Flatpack (PQFP) A1440A Device 84-pin Plastic Leaded Chip Carrier (PLCC) 100-pin Very Thin Quad Flatpack (VQFP) 160-pin Plastic Quad Flatpack (PQFP) 176-pin Thin Quad Flatpack (TQFP) 177-pin Ceramic Pin Grid Array (CPGA) A1460A Device 160-pin Plastic Quad Flatpack (PQFP) 176-pin Thin Quad Flatpack (TQFP) 196-pin Ceramic Quad Flatpack (CQFP) 207-pin Ceramic Pin Grid Array (CPGA) 208-pin Plastic Quad Flatpack (PQFP) 225-pin Platic Ball Grid Array (BGA) A14100A Device 208-pin Power Quad Flatpack (RQFP) 257-pin Ceramic Pin Grid Array (CPGA) 313-pin Plastic Ball Grid Array (BGA) 256-pin Ceramic Quad Flatpack (CQFP) Applications: C = Commercial I = Industrial M = Military Standard. B = MIL-STD-883 E = Extended Availability: = Available P = Planned -- = Not Planned * Speed Grade: -1 = Approx. 15% faster than Standard -2 = Approx. 25% faster than Standard -3 = Approx. 35 % faster than Note: 1. Availability as of October 1994. Please consult Actel Representatives for current availability. 1-156 A C T TM 3 F i e l d P ro g ra m m a b l e Gate Arrays Plastic Device Resources User I/Os PLCC PQFP, RQFP Device Series Logic Modules Gates 84-pin 100-pin A1415A 200 1500 70 A1425A 310 2500 70 A1440A 564 4000 A1460A 848 6000 A14100A 1377 10000 VQFP TQFP BGA 160-pin 208-pin 100-pin 176-pin 225-pin 313-pin 80 -- -- 80 -- -- -- 80 100 -- 83 -- -- -- 70 -- 131 -- 83 140 -- -- -- -- 131 167 -- 151 168 -- -- -- -- 175 -- -- -- 228 Hermetic Device Resources User I/Os CPGA Device Series Logic Modules Gates 100-pin A1415A 200 1500 A1425A 310 2500 A1440A 564 A1460A 848 A14100A 1377 CQFP 133-pin 175-pin 207-pin 257-pin 132-pin 196-pin 256-pin 80 -- -- -- -- 100 -- -- -- -- -- -- -- 100 -- -- 4000 -- -- 140 6000 -- -- -- -- -- -- -- -- 168 -- -- 168 -- 10000 -- -- -- -- 228 -- -- 228 1-157 1 Pin Description CLKA Clock A (Input) TTL Clock input for clock distribution networks. The Clock input is buffered prior to clocking the logic modules. This pin can also be used as an I/O. CLKB Clock B (Input) TTL Clock input for clock distribution networks. The Clock input is buffered prior to clocking the logic modules. This pin can also be used as an I/O. DCLK Diagnostic Clock (Input) TTL Clock input for diagnostic probe and device programming. DCLK is active when the MODE pin is HIGH. This pin functions as an I/O when the MODE pin is LOW. GND Ground LOW supply voltage. HCLK Dedicated (Hard-wired) Array Clock (Input) TTL Clock input for sequential modules. This input is directly wired to each S-Module and offers clock speeds independent of the number of S-Modules being driven. This pin can also be used as an I/O. I/O Input/Output (Input, Output) NC PRA PRB IOCLK V CC IOPCL Dedicated (Hard-wired) I/O Preset/Clear (Input) TTL input for I/O preset or clear. This global input is directly wired to the preset and clear inputs of all I/O registers. This pin functions as an I/O when no I/O preset or clear macros are used. MODE Mode (Input) The MODE pin controls the use of diagnostic pins (DCLK, PRA, PRB, SDI). When the MODE pin is HIGH, the special functions are active. When the MODE pin is LOW, the pins function as I/Os. 1-158 Probe B (Output) The Probe B pin is used to output data from any user-defined design node within the device. This independent diagnostic pin can be used in conjunction with the Probe A pin to allow real-time diagnostic output of any signal path within the device. The Probe B pin can be used as a user-defined I/O when debugging has been completed. The pin's probe capabilities can be permanently disabled to protect programmed design confidentiality. PRB is accessible when the MODE pin is HIGH. This pin functions as an I/O when the MODE pin is LOW. SDI TTL Clock input for I/O modules. This input is directly wired to each I/O module and offers clock speeds independent of the number of I/O modules being driven. This pin can also be used as an I/O. Probe A (Output) The Probe A pin is used to output data from any user-defined design node within the device. This independent diagnostic pin can be used in conjunction with the Probe B pin to allow real-time diagnostic output of any signal path within the device. The Probe A pin can be used as a user-defined I/O when debugging has been completed. The pin's probe capabilities can be permanently disabled to protect programmed design confidentiality. PRA is accessible when the MODE pin is HIGH. This pin functions as an I/O when the MODE pin is LOW. The I/O pin functions as an input, output, three-state, or bidirectional buffer. Input and output levels are compatible with standard TTL and CMOS specifications. Unused I/O pins are automatically driven LOW by the ALS software. Dedicated (Hard-wired) I/O Clock (Input) No Connection This pin is not connected to circuitry within the device. Serial Data Input (Input) Serial data input for diagnostic probe and device programming. SDI is active when the MODE pin is HIGH. This pin functions as an I/O when the MODE pin is LOW. 5 V Supply Voltage HIGH supply voltage. V KS Programming Voltage Supply voltage used for device programming. This pin must be connected to GND during normal operation. V PP Programming Voltage Supply voltage used for device programming. This pin must be connected to VCC during normal operation. V SV Programming Voltage Supply voltage used for device programming. This pin must be connected to VCC during normal operation. A C T TM 3 F i e l d P ro g ra m m a b l e Gate Arrays Architecture Logic Modules This section of the data sheet is meant to familiarize the user with the architecture of the ACT 3 family of FPGA devices. A generic description of the family will be presented first, followed by a detailed description of the logic blocks, the routing structure, the antifuses, and the special function circuits. The on-chip circuitry required to program the devices is not covered. ACT 3 logic modules are enhanced versions of the ACT 2 family logic modules. As in the ACT 2 family, there are two types of modules: C-modules and S-modules. The C-module is functionally equivalent to the ACT 2 C-module and implements high fanin combinatorial macros, such as 5-input AND, 5-input OR, and so on. It is available for use as the CM8 hard macro. The S-module is designed to implement high-speed sequential functions within a single module. S-modules consist of a full C-module driving a flip-flop, which allows an additional level of logic to be implemented without additional propagation delay. It is available for use as the DFM8A/B and DLM8A/B hard macros. C-modules and S-modules are arranged in pairs called module-pairs. Module-pairs are arranged in alternating patterns and make up the bulk of the array. This arrangement allows the placement software to support two-module macros of four types (CC, CS, SC, and SS). The C-module implements the following function: Topology The ACT 3 family architecture is composed of six key elements: Logic modules, I/O modules, I/O Pad Drivers, Routing Tracks, Clock Networks, and Programming and Test Circuits. The basic structure is similar for all devices in the family, differing only in the number of rows, columns, and I/Os. The array itself consists of alternating rows of modules and channels. The logic modules and channels are in the center of the array; the I/O modules are located along the array periphery. A simplified floor plan is depicted in Figure 1. Y = !S1 * !S0 * D00 + !S1 * S0 * D01 + S1 * !S0 * D10 + S1 * S0 * D11 where: S0 = A0 * B0 and S1 = A1 + B1 An Array with n rows and m columns 0 Rows 1 2 3 4 5 c-1 c c+1 m m+1 m+2 m+3 Columns Channels n+2 IO n+1 IO IO CLKM IO IO IO IO IO IO Top I/Os n+1 n IO IO BIN S S C C S S C C S C S IO IO IO IO BIN S S C C S S C C S C S IO IO IO IO BIN S S C C S S C C S C S IO IO IO IO BIN S S C C S S C C S C S IO IO IO IO IO IO IO IO IO IO IO IO Right I/Os Bottom I/Os n n-1 * * * 2 n-1 * * * 2 1 1 Left I/Os 0 BIO IO 0 Figure 1 * Generalized Floor Plan of ACT 3 Device 1-159 1 The S-module contains a full implementation of the C-module plus a clearable sequential element that can either implement a latch or flip-flop function. The S-module can therefore implement any function implemented by the C-module. This allows complex combinatorial-sequential functions to be implemented with no delay penalty. The Action Logic System will automatically combine any C-module macro driving an S-module macro into the S-module, thereby freeing up a logic module and eliminating a module delay. D00 D01 Y D10 OUT D11 The clear input CLR is accessible from the routing channel. In addition, the clock input may be connected to one of three clock networks: CLK0, CLK1, or HCLK. The C-module and S-module functional descriptions are shown in Figures 2 and 3. The clock selection multiplexor selects the clock input to the S-module. I/Os S1 S0 A1 B1 A0 B0 I/O Modules I/O modules provide an interface between the array and the I/O Pad Drivers. I/O modules are located in the array and access the routing channels in a similar fashion to logic modules. There are two types of I/O modules: side and top/bottom. The I/O module schematic is shown in Figure 4. UO1 and UO2 are inputs from the routing channel, one for the routing channel above and one for the routing channel below the module. The top/bottom I/O modules interact with only one channel and therefore have only one UO input. The signals DataIn and DataOut connect to the I/O pad driver. Each I/O module contains two D-type flip-flops. Each flip-flop is connected to the dedicated I/O clock (IOCLK). Each flip-flop can be bypassed by nonsequential I/Os. In addition, each flip-flop contains a data enable input that can be accessed from the routing channels (ODE and IDE). The Figure 2 * C-Module Diagram asynchronous preset/clear input is driven by the dedicated preset/clear network (IOPCL). Either preset or clear can be selected individually on an I/O module by I/O module basis. The I/O module output Y is used to bring Pad signals into the array or to feed the output register back into the array. This allows the output register to be used in high-speed state machine applications. Side I/O modules have a dedicated output segment for Y extending into the routing channels above and below (similar to logic modules). Top/Bottom I/O modules have no dedicated output segment. Signals coming into the chip from the top or bottom are routed using F-fuses and LVTs (F-fuses and LVTs are explained in detail in the routing section). D00 D01 D10 Y D Q D11 S1 S0 CLK A1 B1 Figure 3 * S-Module Diagram 1-160 A0 B0 CLR OUT A C T TM 3 F i e l d P ro g ra m m a b l e Gate Arrays OTB U01 U02 0 MUX 1 D Q 0 MUX 1 DATAOUT CLR/PRE ODE 1 IDE IEN S0 Y 0 S1 1 MUX 2 3 Q D 1 MUX 0 DATAIN CLR/PRE IOPCL IOCLK Figure 4 * Functional Diagram for I/O Module I/O Pad Drivers Clock Networks All pad drivers are capable of being tristate. Each buffer connects to an associated I/O module with four signals: OE (Output Enable), IE (Input Enable), DataOut, and DataIn. Certain special signals used only during programming and test also connect to the pad drivers: OUTEN (global output enable), INEN (global input enable), and SLEW (individual slew selection). See Figure 5. The ACT 3 architecture contains four clock networks: two high-performance dedicated clock networks and two general purpose routed networks. The high-performance networks function up to 200 MHz, while the general purpose routed networks function up to 150 MHz. Special I/Os The special I/Os are of two types: temporary and permanent. Temporary special I/Os are used during programming and testing. They function as normal I/Os when the MODE pin is inactive. Permanent special I/Os are user programmed as either normal I/Os or special I/Os. Their function does not change once the device has been programmed. The permanent special I/Os consist of the array clock input buffers (CLKA and CLKB), the hard-wired array clock input buffer (HCLK), the hard-wired I/O clock input buffer (IOCLK), and the hard-wired I/O register preset/clear input buffer (IOPCL). Their function is determined by the I/O macros selected. Dedicated Clocks Dedicated clock networks support high performance by providing sub-nanosecond skew and guaranteed performance. Dedicated clock networks contain no programming elements in the path from the I/O Pad Driver to the input of S-modules or I/O modules. There are two dedicated clock networks: one for the array registers (HCLK), and one for the I/O registers (IOCLK). The clock networks are accessed by special I/Os. 1-161 CLKB CLKINB CLKA CLKINA OE FROM PADS SLEW CLKMOD DATAOUT S0 S1 INTERNAL SIGNAL CLKO(17) CLOCK DRIVERS CLKO(16) PAD CLKO(15) DATAIN CLKO(2) CLKO(1) IEN CLOCK TRACKS INEN Figure 6 * Clock Networks OUTEN Routing Structure Figure 5 * Function Diagram for I/O Pad Driver Routed Clocks The routed clock networks are referred to as CLK0 and CLK1. Each network is connected to a clock module (CLKMOD) that selects the source of the clock signal and may be driven as follows (see Figure 6): * externally from the CLKA pad * externally from the CLKB pad * internally from the CLKINA input * internally from the CLKINB input The clock modules are located in the top row of I/O modules. Clock drivers and a dedicated horizontal clock track are located in each horizontal routing channel. The function of the clock module is determined by the selection of clock macros from the macro library. The macro CLKBUF is used to connect one of the two external clock pins to a clock network, and the macro CLKINT is used to connect an internally generated clock signal to a clock network. Since both clock networks are identical, the user does not care whether CLK0 or CLK1 is being used. Routed clocks can also be used to drive high fanout nets like resets, output enables, or data enables. This saves logic modules and results in performance increases in some cases. 1-162 The ACT 3 architecture uses vertical and horizontal routing tracks to connect the various logic and I/O modules. These routing tracks are metal interconnects that may either be of continuous length or broken into segments. Segments can be joined together at the ends using antifuses to increase their lengths up to the full length of the track. Horizontal Routing Horizontal channels are located between the rows of modules and are composed of several routing tracks. The horizontal routing tracks within the channel are divided into one or more segments. The minimum horizontal segment length is the width of a module-pair, and the maximum horizontal segment length is the full length of the channel. Any segment that spans more than one-third the row length is considered a long horizontal segment. A typical channel is shown in Figure 7. Undedicated horizontal routing tracks are used to route signal nets. Dedicated routing tracks are used for the global clock networks and for power and ground tie-off tracks. Vertical Routing Other tracks run vertically through the modules. Vertical tracks are of three types: input, output, and long. Vertical tracks are also divided into one or more segments. Each segment in an input track is dedicated to the input of a particular module. Each segment in an output track is A C T TM 3 F i e l d P ro g ra m m a b l e Gate Arrays dedicated to the output of a particular module. Long segments are uncommitted and can be assigned during routing. Each output segment spans four channels (two above and two below), except near the top and bottom of the array where edge effects occur. LVTs contain either one or two segments. An example of vertical routing tracks and segments is shown in Figure 8. MODULE ROW HCLK CLK0 NVCC SIGNAL TRACK SIGNAL (LHT) | | | | | | | SEGMENT HF SIGNAL NVSS CLK1 MODULE ROW Figure 7 * Horizontel Routing Tracks and Segments LVTS S-MODULE MODULE ROW C-MODULE VF CHANNEL XF VERTICLE INPUT SEGMENT FF S-MODULE C-MODULE Figure 8 * Vertical Routing Tracks and Segments 1-163 1 Antifuse Connections An antifuse is a "normally open" structure as opposed to the normally closed fuse structure used in PROMs or PALs. The use of antifuses to implement a programmable logic device results in highly testable structures as well as an efficient programming architecture. The structure is highly testable because there are no preexisting connections; temporary connections can be made using pass transistors. These temporary connections can isolate individual antifuses to be programmed as well as isolate individual circuit structures to be tested. This can be done both before and after programming. For example, all metal tracks can be tested for continuity and shorts between adjacent tracks, and the functionality of all logic modules can be verified. Four types of antifuse connections are used in the routing structure of the ACT 3 array. (The physical structure of the antifuse is identical in each case; only the usage differs.) Table 1 shows four types of antifuses. Table 1 * Antifuse Types that half of the inputs are connected to the channel above and half of the inputs to segments in the channel below as shown in Figure 9. Module Output Connections Module outputs have dedicated output segments. Output segments extend vertically two channels above and two channels below, except at the top or bottom of the array. Output segments twist, as shown in Figure 10, so that only four vertical tracks are required. LVT Connections Outputs may also connect to nondedicated segments called Long Vertical Tracks (LVTs). Each module pair in the array shares four LVTs that span the length of the column. Any module in the column pair can connect to one of the LVTs in the column using an FF connection. The FF connection uses antifuses connected directly to the driver stage of the module output, bypassing the isolation transistor. FF antifuses are programmed at a higher current level than HF, VF, or XF antifuses to produce a lower resistance value. XF Horizontal-to-Vertical Connection Antifuse Connections HF Horizontal-to-Horizontal Connection VF Vertical-to-Vertical Connection FF "Fast" Vertical Connection In general every intersection of a vertical segment and a horizontal segment contains an unprogrammed antifuse (XF-type). One exception is in the case of the clock networks. Clock Connections Examples of all four types of connections are shown in Figures 7 and 8. Module Interface Connections to Logic and I/O modules are made through vertical segments that connect to the module inputs and outputs. These vertical segments lie on vertical tracks that span the entire height of the array. Module Input Connections The tracks dedicated to module inputs are segmented by pass transistors in each module row. During normal user operation, the pass transistors are inactive, which isolates the inputs of a module from the inputs of the module directly above or below it. During certain test modes, the pass transistors are active to verify the continuity of the metal tracks. Vertical input segments span only the channel above or the channel below. The logic modules are arranged such 1-164 To minimize loading on the clock networks, a subset of inputs has antifuses on the clock tracks. Only a few of the C-module and S-module inputs can be connected to the clock networks. To further reduce loading on the clock network, only a subset of the horizontal routing tracks can connect to the clock inputs of the S-module. Programming and Test Circuits The array of logic and I/O modules is surrounded by test and programming circuits controlled by the temporary special I/O pins MODE, SDI, and DCLK. The function of these pins is similar to all ACT family devices. The ACT 3 family also includes support for two Actionprobe(R) circuits allowing complete observability of any logic or I/O module in the array using the temporary special I/O pins, PRA and PRB. A C T TM 3 F i e l d P ro g ra m m a b l e Gate Arrays Y+2 Y+2 Y+1 B1 B0 D01 D00 A1 D10 D11 A0 Y+1 B0 Y Y Y-1 D10 B1 D01 A0 D11 A1 Y-1 Y-2 Y-2 LVTs S-MODULES C-MODULES Figure 9 * Logic Module Routing Interface 1-165 1 Absolute Maximum Ratings 1 Recommended Operating Conditions Free air temperature range Symbol Parameter Supply Voltage2 Parameter Limits Units -0.5 to +7.0 V VCC DC VI Input Voltage -0.5 to VCC +0.5 V VO Output Voltage -0.5 to VCC +0.5 V I/O Source Sink 20 mA -65 to +150 C IIO 3 Current TSTG Storage Temperature Commercial Industrial Military Units Temperature Range1 0 to +70 -40 to +85 -55 to +125 C Power Supply Tolerance 5 10 10 %VCC Note: 1. Ambient temperature (TA) is used for commercial and industrial; case temperature (TC) is used for military. Notes: 1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Device should not be operated outside the Recommended Operating Conditions. 2. 3. VPP , VSV = VCC , except during device programming. Device inputs are normally high impedance and draw extremely low current. However, when input voltage is greater than VCC + 0.5 V or less than GND - 0.5 V, the internal protection diodes will forward bias and can draw excessive current. Electrical Specifications Commercial Symbol Parameter VOL1,2 HIGH Level Output LOW Level Output Military Units Min. VOH1,2 Industrial Test Condition Max. IOH = -4 mA (CMOS) Min. Max. 3.7 Min. Max. 3.7 V IOH = -6 mA (CMOS) 3.84 V IOH = -10 mA (TTL)3 V 2.40 IOL = +6 mA (CMOS) 0.33 IOL = +12 mA (TTL)3 0.50 0.4 0.4 V V VIH HIGH Level Input TTL Inputs 2.0 VCC + 0.3 2.0 VCC + 0.3 2.0 VCC + 0.3 V VIL LOW Level Input TTL Inputs -0.3 0.8 -0.3 0.8 -0.3 0.8 V IIN Input Leakage VI = VCC or GND -10 +10 -10 +10 -10 +10 A IOZ 3-state Output Leakage VO = VCC or GND -10 +10 -10 +10 -10 +10 A CIO I/O Capacitance3,4 10 10 10 pF ICC(S) Standby VCC Supply Current (typical = 0.7 mA) 2 10 20 mA ICC(D) Dynamic VCC Supply Current See "Power Dissipation" Section Notes: 1. Actel devices can drive and receive either CMOS or TTL signal levels. No assignment of I/Os as TTL or CMOS is required. 2. 3. 4. 5. Tested one output at a time, VCC = min. Not tested, for information only. VOUT = 0V, f = 1 MHz. Typical standby current = 0.7 mA. All outputs unloaded. All inputs = VCC or GND. 1-166 A C T TM 3 F i e l d P ro g ra m m a b l e Gate Arrays Package Thermal Characteristics Maximum junction temperature is 150C. The device junction to case thermal characteristic is jc, and the junction to ambient air characteristic is ja. The thermal characteristics for ja are shown with two different air flow rates. A sample calculation of the absolute maximum power dissipation allowed for a CPGA 175-pin package at commercial temperature and still air is as follows: 150C - 70C Max. junction temp. (C) - Max. ambient temp. (C) Absolute Maximum Power Allowed = ------------------------------------------------------------------------------------------------------------------------------ = --------------------------------- = 3.2 W ja (C/W) 25 C/W Pin Count ja Still Air ja 300 ft/min Units Ceramic Pin Grid Array 100 133 175 207 257 35 30 25 22 15 17 15 14 13 8 C/W C/W C/W C/W C/W Ceramic Quad Flatpack 132 196 256 55 36 30 30 24 18 C/W C/W Plastic Quad Flatpack 100 160 208 51 33 33 40 26 26 C/W C/W C/W Very Thin Quad Flatpack 100 43 35 C/W Thin Quad Flatpack 176 32 25 C/W Power Quad Flatpack 208 17 13 C/W Plastic Leaded Chip Carrier 84 37 28 C/W Plastic Ball Grid Array 225 313 25 23 19 17 C/W Package Type1 1 C/W C/W Notes: 1. Maximum Power Dissipation for 160-pin PQFP package is 2.4 Watts, 208-pin PQFP package is 2.4 Watts, 100-pin PQFP package is 1.6 Watts, 100-pin VQFP package is 1.9 Watts, 176-pin TQFP package is 2.5 Watts, 84-pin PLCC package is 2.2 Watts, 208-pin RQFP package is 4.7 Watts, 225-pin BGA package is 3.2 Watts, 313-pin BGA package is 3.5 Watts. Power Dissipation Static Power Component P = [ICC standby+ Iactive] * VCC + IOL * VOL * N + IOH * (VCC - VOH) * M (1) Actel FPGAs have small static power components that result in lower power dissipation than PALs or PLDs. By integrating multiple PALs/PLDs into one FPGA, an even greater reduction in board-level power dissipation can be achieved. Where: ICC standby is the current flowing when no inputs or outputs are changing. Iactive is the current flowing due to CMOS switching. IOL, IOH are TTL sink/source currents. VOL, VOH are TTL level output voltages. N equals the number of outputs driving TTL loads to VOL. M equals the number of outputs driving TTL loads to VOH. An accurate determination of N and M is problematical because their values depend on the design and on the system I/O. The power can be divided into two components: static and active. The power due to standby current is typically a small component of the overall power. Standby power is calculated below for commercial, worst case conditions. ICCVCCPower 2mA5.25 V10.5 mW The static power dissipated by TTL loads depends on the number of outputs driving high or low and the DC load current. Again, this value is typically small. For instance, a 32-bit bus sinking 4 mA at 0.33 V will generate 42 mW with all outputs driving low, and 140 mW with all outputs driving high. The actual dissipation will average somewhere between as I/Os switch states with time. 1-167 Active Power Component n=Number of input buffers switching at fn Power dissipation in CMOS devices is usually dominated by the active (dynamic) power dissipation. This component is frequency dependent, a function of the logic and the external I/O. Active power dissipation results from charging internal chip capacitances of the interconnect, unprogrammed antifuses, module inputs, and module outputs, plus external capacitance due to PC board traces and load device inputs. An additional component of the active power dissipation is the totem-pole current in CMOS transistor pairs. The net effect can be associated with an equivalent capacitance that can be combined with frequency and voltage to represent active power dissipation. p=Number of output buffers switching at fp CEQI=Equivalent capacitance of input buffers in pF Equivalent Capacitance CEQO=Equivalent capacitance of output buffers in pF The power dissipated by a CMOS circuit can be expressed by the Equation 2. Power (uW) = CEQ * VCC2 * F (2) Where: CEQ is the equivalent capacitance expressed in pF. VCC is the power supply in volts. F is the switching frequency in MHz. Equivalent capacitance is calculated by measuring ICCactive at a specified frequency and voltage for each circuit component of interest. Measurements have been made over a range of frequencies at a fixed value of VCC. Equivalent capacitance is frequency independent so that the results may be used over a wide range of operating conditions. Equivalent capacitance values are shown below. q1=Number of clock loads on the first routed array clock q2=Number of clock loads on the second routed array clock r1=Fixed capacitance due to first routed array clock r2=Fixed capacitance due to second routed array clock s1=Fixed number of clock loads on the dedicated array clock s2=Fixed number of clock loads on the dedicated I/O clock CEQM=Equivalent capacitance of logic modules in pF CEQCR=Equivalent capacitance of routed array clock in pF CEQCD=Equivalent capacitance of dedicated array clock in pF CEQCI=Equivalent capacitance of dedicated I/O clock in pF CL=Output lead capacitance in pF fm=Average logic module switching rate in MHz fn=Average input buffer switching rate in MHz fp=Average output buffer switching rate in MHz fq1=Average first routed array clock rate in MHz fq2=Average second routed array clock rate in MHz fs1=Average dedicated array clock rate in MHz fs2=Average dedicated I/O clock rate in MHz Fixed Capacitance Values for Actel FPGAs (pF) C EQ Values for Actel FPGAs r1r2 Modules (CEQM)6.7 Device Typerouted_Clk1routed_Clk2 Input Buffers (CEQI)7.2 A1415A6060 Output Buffers (CEQO)10.4 A1425A7575 Routed Array Clock Buffer Loads (CEQCR)1.6 A1440A105105 Dedicated Clock Buffer Loads (CEQCD)0.7 A1460A165165 I/O Clock Buffer Loads (CEQCI)0.9 A14100A195195 To calculate the active power dissipated from the complete design, the switching frequency of each part of the logic must be known. Equation 3 shows a piece-wise linear summation over all components. Fixed Clock Loads (s 1 /s 2 ) Power =VCC2 * [(m * CEQM* fm)modules + (n * CEQI* fn)inputs + (p * (CEQO+ CL) * fp)outputs + 0.5 * (q1 * CEQCR * fq1)routed_Clk1 + (r1 * fq1)routed_Clk1 + 0.5 * (q2 * CEQCR * fq2)routed_Clk2 + (r2 * fq2)routed_Clk2 + 0.5 * (s1 * CEQCD * fs1)dedicated_Clk (3) + (s2 * CEQCI * fs2)IO_Clk] Device Typededicated array clockdedicated I/O clock Where: m=Number of logic modules switching at fm 1-168 s1s2 Clock Loads onClock Loads on A1415A10480 A1425A160100 A1440A288140 A1460A432168 A14100A697228 A C T TM 3 F i e l d P ro g ra m m a b l e Gate Arrays Determining Average Switching Frequency To determine the switching frequency for a design, you must have a detailed understanding of the data input values to the circuit. The following guidelines are meant to represent worst-case scenarios so that they can be generally used to predict the upper limits of power dissipation. These guidelines are as follows: Logic Modules (m) Inputs switching (n) Outputs switching (p) First routed array clock loads (q1) Second routed array clock loads (q2) = 80% modules = # inputs/4 = # output/4 = 40% sequential modules = 40% sequential modules of of Load capacitance (CL) Average logic module switching rate (fm) Average input switching rate (fn) Average output switching rate (fp) Average first routed array clock rate (fq1) Average second routed array clock rate (fq2) Average dedicated array clock rate (fs1) Average dedicated I/O clock rate (fs2) = 35 pF = F/10 = F/5 = F/10 = F/2 = F/2 1 = F = F of ACT 3 Timing Model* Input Delays I/O Module tINY = 2.8 ns Internal Delays Combinatorial Logic Module Predicted Routing Delays Output Delays I/O Module tIRD2 = 1.2 ns tDHS = 5.0 ns D Q tINH = 0.0 ns tINSU = 1.8 ns tICKY = 4.7 ns tPD = 2.0 ns tHCKH = 3.0 ns I/O Module tDHS = 5.0 ns Sequential Logic Module Combin -atorial Logic include d ARRAY CLOCK tRD1 = 0.9 ns tRD4 = 1.7 ns tRD8 = 2.8 ns tSUD = 0.5 ns tHD = 0.0 ns D D Q tRD1 = 0.9 ns tCO = 2.0 ns Q tENZHS = 4.0 ns tOUTH = 0.7 ns tOUTSU = 0.7 ns FHMAX = 250 MHz I/O CLOCK tCKHS = 7.5 ns (pad-pad) FIOMAX = 250 MHz *Values shown for A1425A-3. 1-169 Output Buffer Delays E D VCC In VCC GND 50% VOH 50% Out VOL PAD To AC test loads (shown below) TRIBUFF En 1.5 V 1.5 V Out 50% VCC VCC 50% 1.5 V GND En Out GND 10% VOL tDHS, tENZHS, tDHS, 90% 1.5 V tENZHS, tENHSZ, GND 50% VOH 50% tENHSZ, AC Test Loads Load 1 (Used to measure propagation delay) Load 2 (Used to measure rising/falling edges) VCC GND To the output under test 35 pF R to VCC for tPLZ/tPZL R to GND for tPHZ/tPZH R = 1 k To the output under test 35 pF Input Buffer Delays PAD Module Delays S A B Y INBUF Y VCC S, A or B 50% 50% VCC Out GND 50% 3V In Out GND 50% 50% tINY 1-170 0V 1.5 V 1.5 V VCC tINY tPD GND 50% tPD VCC Out 50% tPD GND tPD 50% A C T TM 3 F i e l d P ro g ra m m a b l e Gate Arrays Sequential Module Timing Characteristics Flip-Flops D Q CLK CLR (Positive edge triggered) 1 tHD D tA tWCLKA tSUD CLK tWCLKA tCO Q tCLR CLR tWASYN I/O Module: Sequential Input Timing Characteristics D E IOCLK Y PRE CLR (Positive edge triggered) tINH D tINSU tIOP tIOPWH IOCLK tIDESU tIOPWL E tICKY Y tICLRY PRE, CLR tIOASPW 1-171 I/O Module: Sequential Output Timing Characteristics D E Q PRE IOCLK CLR Y (Positive edge triggered) tOUTH D tOUTSU tIOP tIOPWH IOCLK tODESU tIOPWL E tOCKY Y tCKHS, tCKLS Q tOCLRY PRE, CLR tIOASPW 1-172 A C T TM 3 F i e l d P ro g ra m m a b l e Gate Arrays Predictable Performance: Tightest Delay Distributions Timing Characteristics Propagation delay between logic modules depends on the resistive and capacitive loading of the routing tracks, the interconnect elements, and the module inputs being driven. Propagation delay increases as the length of routing tracks, the number of interconnect elements, or the number of inputs increases. From a design perspective, the propagation delay can be statistically correlated or modeled by the fanout (number of loads) driven by a module. Higher fanout usually requires some paths to have longer lengths of routing track. The ACT 3 family delivers the tightest fanout delay distribution of any FPGA. This tight distribution is achieved in two ways: by decreasing the delay of the interconnect elements and by decreasing the number of interconnect elements per path. Actel's patented PLICE antifuse offers a very low resistive/capacitive interconnect. The ACT 3 family's antifuses, fabricated in 0.8 micron m lithography, offer nominal levels of 200 resistance and 6 femtofarad (fF) capacitance per antifuse. The ACT 3 fanout distribution is also tighter than alternative devices due to the low number of antifuses required per interconnect path. The ACT 3 family's proprietary architecture limits the number of antifuses per path to only four, with 90% of interconnects using only two antifuses. Table 2 * Logic Module + Routing Delay, by fanout (ns) (Worst-Case Commercial Conditions) Family FO=1 FO=2 FO=3 FO=4 FO=8 ACT 1 -2 4.5 5.1 5.9 7.0 11.1 ACT 2 -2 4.9 5.5 6.1 6.6 8.2 ACT 3 -3 2.9 3.2 3.4 3.7 4.8 The ACT 3 family's tight fanout delay distribution offers an FPGA design environment in which fanout can be traded for the increased performance of reduced logic level designs. This also simplifies performance estimates when designing with ACT 3 devices. Timing characteristics for ACT 3 devices fall into three categories: family dependent, device dependent, and design dependent. The input and output buffer characteristics are common to all ACT 3 family members. Internal routing delays are device dependent. Design dependency means actual delays are not determined until after placement and routing of the user's design is complete. Delay values may then be determined by using the ALS Timer utility or performing simulation with post-layout delays. Critical Nets and Typical Nets Propagation delays are expressed only for typical nets, which are used for initial design performance evaluation. Critical net delays can then be applied to the most time-critical paths. Critical nets are determined by net property assignment prior to placement and routing. Up to 6% of the nets in a design may be designated as critical, while 90% of the nets in a design are typical. Long Tracks Some nets in the design use long tracks. Long tracks are special routing resources that span multiple rows, columns, or modules. Long tracks employ three and sometimes four antifuse connections. This increases capacitance and resistance, resulting in longer net delays for macros connected to long tracks. Typically up to 6% of nets in a fully utilized device require long tracks. Long tracks contribute approximatley 4 ns to 14 ns delay. This additional delay is represented statistically in higher fanout (FO=8) routing delays in the data sheet specifications section. Timing Derating ACT 3 devices are manufactured in a CMOS process. Therefore, device performance varies according to temperature, voltage, and process variations. Minimum timing parameters reflect maximum operating voltage, minimum operating temperature, and best-case processing. Maximum timing parameters reflect minimum operating voltage, maximum operating temperature, and worst-case processing. 1-173 1 Timing Derating Factor (Temperature and Voltage) Industrial (Commercial Minimum/Maximum Specification) x Military Min. Max. Min. Max. 0.66 1.07 0.63 1.17 Timing Derating Factor for Designs at Typical Temperature (T J = 25C) and Voltage (5.0 V) (Commercial Maximum Specification) x 0.85 Temperature and Voltage Deratin g Factors (normalized to Worst-Case Commercial, T J = 4.75 V, 70C) -55 -40 0 25 70 85 125 4.50 0.72 0.76 0.85 0.90 1.04 1.07 1.17 4.75 0.70 0.73 0.82 0.87 1.00 1.03 1.12 5.00 0.68 0.71 0.79 0.84 0.97 1.00 1.09 5.25 0.66 0.69 0.77 0.82 0.94 0.97 1.06 5.50 0.63 0.66 0.74 0.79 0.90 0.93 1.01 Junction Temperature and Voltage Derating Curves (normalized to Worst-Case Commercial, T J = 4.75 V, 70C) 1.20 Derating Factor 1.10 1.00 0.90 0.80 0.70 0.60 4.50 4.75 5.00 Voltage (V) Note: 1-174 This derating factor applies to all routing and propagation dealys. 5.25 5.50