© Semiconductor Components Industries, LLC, 2011
August, 2011 − Rev. 5
1Publication Order Number:
NTR4502P/D
NTR4502P, NVTR4502P
Power MOSFET
−30 V, −1.95 A, Single, P−Channel,
SOT−23
Features
•Leading Planar Technology for Low Gate Charge / Fast Switching
•Low RDS(ON) for Low Conduction Losses
•SOT−23 Surface Mount for Small Footprint (3 X 3 mm)
•AEC Q101 Qualified − NVTR4502P
•These Devices are Pb−Free and are RoHS Compliant
Applications
•DC to DC Conversion
•Load/Power Switch for Portables and Computing
•Motherboard, Notebooks, Camcorders, Digital Camera’s, etc.
•Battery Charging Circuits
MAXIMUM RATINGS (TJ = 25°C unless otherwise stated)
Parameter Symbol Value Unit
Drain−to−Source Voltage VDSS −30 V
Gate−to−Source Voltage VGS ±20 V
Drain Current (Note 1) t < 10 s TA = 25°C ID−1.95 A
TA = 70°C−1.56
Power Dissipation
(Note 1)
t < 10 s PD1.25 W
Continuous Drain Current
(Note 1)
Steady
State
TA = 25°C ID−1.13 A
TA = 70°C−0.90
Power Dissipation
(Note 1)
Steady State PD0.4 W
Pulsed Drain Current tp = 10 msIDM −6.8 A
Operating Junction and Storage Temperature TJ,
TSTG
−55 to
150
°C
Source Current (Body Diode) IS−1.25 A
Lead Temperature for Soldering Purposes
(1/8 in from case for 10 s)
TL260 °C
THERMAL RESISTANCE RATINGS
Parameter Symbol Max Unit
Junction−to−Ambient – Steady State (Note 1) RqJA 300 °C/W
Junction−to−Ambient – t = 10 s (Note 1) RqJA 100
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Surface−mounted on FR4 board using 1 in sq. pad size
(Cu area = 1.127 in sq. [1 oz] including traces).
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MARKING DIAGRAM/
PIN ASSIGNMENT
S
G
D
P−Channel MOSFET
V(BR)DSS RDS(on) TYP ID Max (Note 1)
−30 V
155 mW @ −10 V
240 mW @ −4.5 V
−1.95 A
Device Package Shipping†
ORDERING INFORMATION
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
NTR4502PT1G SOT−23
(Pb−Free)
3000 / Tape & Reel
NVTR4502PT1G 3000 / Tape & Reel
SOT−23
(Pb−Free)
SOT−23
CASE 318
STYLE 21
TR2 = Device Code
M = Date Code*
G= Pb−Free Package
(Note: Microdot may be in either location)
*Date Code orientation and/or overbar may
vary depending upon manufacturing location.
3
Drain
1
Gate
2
Source
TR2 M G
G
NTR4502P, NVTR4502P
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2
Electrical Characteristics (TJ = 25°C unless otherwise specified)
Parameter Symbol Test Condition Min Typ Max Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage V(BR)DSS VGS = 0 V, ID = −250 mA−30 V
Zero Gate Voltage Drain Current IDSS VGS = 0 V, VDS = −30 V TJ = 25°C−1mA
TJ = 55°C−10
Gate−to−Source Leakage Current IGSS VDS = 0 V, VGS = ±20 V ±100 nA
ON CHARACTERISTICS (Note 3)
Gate Threshold Voltage VGS(TH) VGS = VDS, ID = −250 mA−1.0 −3.0 V
Drain−to−Source On Resistance RDS(on) VGS = −10 V, ID = −1.95 A 155 200 mW
VGS = −4.5 V, ID = −1.5 A 240 350
Forward Transconductance gFS VDS = −10 V, ID=−1.25 A 3 S
CHARGES AND CAPACITANCES
Input Capacitance CISS VGS = 0 V, f = 1 MHz, VDS = −15 V 200 pF
Output Capacitance COSS 80
Reverse Transfer Capacitance CRSS 50
Total Gate Charge QG(TOT) VGS = −10 V, VDS = −15 V; ID = −1.95 A 6 10 nC
Threshold Gate Charge QG(TH) 0.3
Gate−to−Source Charge QGS 1
Gate−to−Drain Charge QGD 1.7
SWITCHING CHARACTERISTICS (Note 4)
Turn−On Delay Time td(ON) VGS =−10 V, VDD = −15 V,
ID = −1.95 A, RG = 6 W
5.2 10 ns
Rise Time tr12 20
Turn−Off Delay Time td(OFF) 19 35
Fall Time tf17.5 30
DRAIN−SOURCE DIODE CHARACTERISTICS (Note 3)
Forward Diode Voltage VSD VGS = 0 V, IS = −1.25 A −0.8 −1.2 V
Reverse Recovery Time tRR VGS = 0 V, dISD/dt = 100 A/ms, IS = −1.25 A 23 ns
2. Surface−mounted on FR4 board using 1 in sq. pad size (Cu area = 1.127 in sq. [1 oz] including traces).
3. Pulse Test: pulse width v 300 ms, duty cycle v 2%.
4. Switching characteristics are independent of operating junction temperatures.
NTR4502P, NVTR4502P
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3
0
1
2
3
4
5
012345678910
Figure 1. On−Region Characteristics
−VDS, DRAIN−TO−SOURCE VOLTAGE (V)
−ID, DRAIN CURRENT (A)
VGS = −2.8 V
VGS = −2.6 V
VGS = −2.4 V
VGS = −3.0 V
VGS = −3.2 V
VGS = −3.4 V
VGS = −3.6 V
VGS = −3.8 V
TJ = 25°C
VGS = −5.0 V
VGS = −7.0 V
VGS = −10 V
0
1
2
3
4
5
1234567
Figure 2. Transfer Characteristics
−VGS, GATE−TO−SOURCE VOLTAGE (V)
−ID, DRAIN CURRENT (A)
VDS = −10 V
VGS = −4.0 V
TJ = 25°C
TJ = 100°C
TJ = −55°C
0.1
0.15
0.2
0.25
0.3
0.35
0.4
345678910
ID = −1.95 A
TJ = 25°C
Figure 3. On−Resistance versus
Gate−to−Source Voltage
−VGS, GATE−TO−SOURCE VOLTAGE (V)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
0.1
0.15
0.2
0.25
0.3
1 1.5 2 2.5 3 3.5 4 4.5 5
TJ = 25°C
VGS = −4.5 V
VGS = −10 V
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
−ID, DRAIN CURRENT (A)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
0.6
0.8
1
1.2
1.4
1.6
1.8
−50 −25 0 25 50 75 100 125 150
ID = −1.9 A
VGS = −10 V
Figure 5. On−Resistance Variation with
Temperature
TJ, JUNCTION TEMPERATURE (°C)
RDS(on), DRAIN−TO−SOURCE RESISTANCE
(NORMALIZED)
1
10
100
1000
2 6 10 14 18 22 26 30
Figure 6. Drain−to−Source Leakage Current
versus Voltage
−VDS, DRAIN−TO−SOURCE VOLTAGE (V)
−IDSS, LEAKAGE (nA)
TJ = 150°C
TJ = 100°C
VGS = 0 V
NTR4502P, NVTR4502P
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4
0
100
200
300
400
500
10 5 0 5 1015202530
Figure 7. Capacitance Variation
GATE−TO−SOURCE OR DRAIN−TO−SOURCE
VOLTAGE (V)
C, CAPACITANCE (pF)
TJ = 25°C
VGS = 0 VVDS = 0 V
CISS
CRSS
COSS
CISS
CRSS
−VGS −VDS
0
2
4
6
8
10
12
01234567
0
3
6
9
12
15
18
QT
QGD
QGS
Figure 8. Gate−to−Source and
Drain−to−Source Voltage versus Total Charge
QG, TOTAL GATE CHARGE (nC)
−VGS, GATE−TO−SOURCE VOLTAGE
(V)
−VDS, DRAIN−TO−SOURCE VOLTAGE
(V)
ID = −1.95 A
TJ = 25°C
1
10
100
1 10 100
t, TIME (ns)
Figure 9. Resistive Switching Time Variation
versus Gate Resistance
RG, GATE RESISTANCE (W)
td(off) tf
tr
td(on)
VDS = −15 V
ID = −1.95 V
VGS = −10 V
0
0.5
1
1.5
2
2.5
3
0.3 0.6 0.9 1.2
Figure 10. Diode Forward Voltage versus
Current
−VSD, SOURCE−TO−DRAIN VOLTAGE (V)
−IS, SOURCE CURRENT
TJ = 25°C
NTR4502P, NVTR4502P
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5
PACKAGE DIMENSIONS
SOT−23 (TO−236)
CASE 318−08
ISSUE AP
D
A1
3
12
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH
THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM
THICKNESS OF BASE MATERIAL.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS.
ǒmm
inchesǓ
SCALE 10:1
0.8
0.031
0.9
0.035
0.95
0.037
0.95
0.037
2.0
0.079
VIEW C
L
0.25
L1
q
e
EE
b
A
SEE VIEW C
DIM
A
MIN NOM MAX MIN
MILLIMETERS
0.89 1.00 1.11 0.035
INCHES
A1 0.01 0.06 0.10 0.001
b0.37 0.44 0.50 0.015
c0.09 0.13 0.18 0.003
D2.80 2.90 3.04 0.110
E1.20 1.30 1.40 0.047
e1.78 1.90 2.04 0.070
L0.10 0.20 0.30 0.004
0.040 0.044
0.002 0.004
0.018 0.020
0.005 0.007
0.114 0.120
0.051 0.055
0.075 0.081
0.008 0.012
NOM MAX
L1
H
2.10 2.40 2.64 0.083 0.094 0.104
HE
0.35 0.54 0.69 0.014 0.021 0.029
c
0−−− 10 0 −−− 10
q°°°°
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
STYLE 21:
PIN 1. GATE
2. SOURCE
3. DRAIN
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NTR4502P/D
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