R6545/R6545E A Rockwell R6545/R6545E CRT Controller (CRTC) DESCRIPTION The A6S45/R6545E CAT Controller (CRTC) interfaces an 8-bit mcroprocessor to CAT raster scan video displays, and adds an advanced CAT controler to the establighed and expanding line of FIBSO0, AiBSO0/* and F6600 microprocessor, microcomputer and pernpheral device products. The Fi6545 and ASS45E devices differ only in the character clock frequency (OCLK) specifications. The maximum COLE frequency is 2.5 MHz for the FI6S45 and 3.7 MHz for the R6S45E. Through out this document, the nomenclature A6545 applies to both devices, unlass speciliad otherwise. The R6545 provides refresh memory addresses and character generator row addresses which allow up io 16K characters with 32 scan lines per character io be addressed. A major advan tage of the Fi6545 Is that the refresh memory may be addressed in either straight binary or by rowfoolurn. Other turctions in the F645 inchude an internal cursor ragister which generates a cursor outpul when its contents are equal to the Current refresh address. Programmable cursor starl and end registers allow a cursor of up to the full character can in height to be placed on any acan lines of the character. Varlable cursor display blink rates are provided. A light pen strobe input allows capture of the cumrent refresh address in an invbennal light pen register. The refresh address lines are configured to pro- vide direct dynamic memory refresh. All timing for the video refresh mamory signals is derived from the character chock input (CLK). Shit register, latch, and nvl- tiplex control signals (when needed) are provided by external high-speed timing. The mode control register allows noninter- laced video cisplay modes at 60 or 60 Hz refresh rale. The internal status regi May be used to moniter the AGs45 Operation. The RES input allows the CATC-generated field rate to be dynamicaily-synchronized with line fraquency jitter. FEATURES Compatibla with 5-bil mictopronessars 3.7 MHz character clock operation (A6545E) 2.5 WH character clock operation (R545) Refresh RAM may be configured in roweolumn of straight binary addressing Alphanumeric and limited graphics capability Up and dewn scrolling by page, line, or character Programmable vertical sync width Fully programmable display (rows, columns, character rravirix) Video display FAM may be configured as part of micro- processor memory field or independently slaved to Fiss45 {Transparent Addressing) Interne oF on-interhackd car S060 Hz refresh rate Fully programmable cursor Light pen register Addresses refresh RAM to 16 characters No external OMA required Internal status register 40-pin ceramic or plastic DIF Pin-compatible with MOG845A Single +5 5%) Vde power supply ORDERING INFORMATION +. f+ + # + # # + & Part Humber: POS45 L.Operating Tamparature (T, to Ty) He Letiers = 0C to 70C E= -40"C to Bc Package Po 40-Fin Plast DIP C= #1 Pin Ceramic (HP J = 44-Fin Plastic Leaded Ghip Garnier (PLC) Operating Frequency (Bus} No Letter = 1 MHz A = 2 MHz Character Chock Frequency (CCL) Ale Lettie on 2.5 MMH E = 3.7 MHz Document No. 20001035 Data Sheet Order No. D135 Rev. 2, June 19387CRT Controller (CRTC) R6545/R6545E it ssaedacsesnanees?? noonnonnonnonnnnnonon FRARRAARRRRARR RAR #0-PiN CP -notnarae SEP eTeetrses eugag7a9ana2ecee45 OEE R6545/A6545E Pin ConfigurationR6545/R6545E INTERFACE SIGNAL DESCRIPTION Figure 1 illustrates the interface between the CPU, the R6545, and the video circuitry. Figure 2 shows typical timing waveforms at the video interface. GND Vec CPU I/F VIDEO I/F HSYNC Do-D7 VSYNC DISPLAY ENABLE o2 CURSOR RW LPEN cs CCLK RS RES MAO-MA13 RAO-RA4S REFRESH RAM AND CHARACTER ROM Figure 1. 6545 Interface Diagram CPU INTERFACE $2 (Phase 2 Clock) The Phase 2 (62) input clock triggers all data transfers between the system processor (CPU) and the R6545. Since there is no maximum limit to the allowable $2 clock time, it is not neces- sary for it to be a continuous clock. This capability permits the R6545 to be easily interfaced to non-6500 compatible microprocessors. R/W (Read/Write) The R/W input signal generated by the processor controls the direction of data transfers. A high on the R/W pin allows the processor to read the data supplied by the R6545, a low on the RAW pin allows data on data fines DO-D7 to be written into the R6545. CS (Chip Select) The Chip Select input is normally connected to the processor address bus either directly or through a decoder. The R6545 is selected when CS is low. Then, data may be written to, or read from, the R6545 depending on the state of RS and R/W. RS (Register Select) The Register Select input allows access to internal registers. A low on this pin permits writing (R/W = low) into the Address Register and reading (R/W = high) from the Status Register. The Address Register selects the register accessed when RS is high. Do-D7 (Data Bus) The eight data lines (DO-D7)} transfer data between the proces- sor and the R6545. These lines are bidirectional and are nor- mally high-impedance except during read cycles when the chip is selected (CS = low). 2-64 CRT Controller (CRTC) VIDEO INTERFACE HSYNC (Horizontal Sync) The HSYNC active-high output signal determines the start of the horizontal raster fine. It may drive a CRT monitor directly or may be used for composite video generation. HSYNC time position and width are fully programmable. VSYNC (Vertical Sync) The VSYNC active-high output signal determines the start of the vertical frame. Like HSYNC, VSYNC may drive a CRT moniter or composite video generation circuits. VSYNC time position and width are both programmable. DISPLAY ENABLE (Display Enable) The DISPLAY ENABLE active-high output signal indicates when the R6545 is generating active display information. The number of horizontal display characters per row and the number of vertical display rows are both fully programmable and together generate the DISPLAY ENABLE signal. DISPLAY ENABLE may be delayed one character time by setting bit 4 of R8 to al. CURSOR (Cursor Coincidence) The CURSOR active-high output signal indicates when the scan coincides with the programmed cursor position. The cursor position is programmable to any character in the address field. Furthermore, within the character, the cursor may be pro- grammed to be any block of scan lines, since the cursor start scan line and end scan line are both programmable. The cur- sor output may be delayed by one character time by setting Bit 5 of R8 to a1. LPEN (Light Pen Strobe) The LPEN edge-sensitive input signal loads the internal Light Pen Register. A low-to-high transition activates LPEN. CCLK (Clock) The CCLK character timing cleck input signal is the time base for all internal count/control functions. RES The RES active-low input signal initializes all internal scan counter circuits. When RES is low, all internal counters stop and clear and ail scan and video outputs go low; control registers are unaffected. RES must stay low for at least one CCLK period. All scan timing initiates when RES goes high. in this way, RES can synchronize display frame timing with line frequency. RES may also synchronize multiple CRTCs in horizontal and/or vertical split screen operation.R6545/R6545E REFRESH RAM AND CHARACTER ROM INTERFACE MAO-MA13 (Refresh RAM Address Lines) These 14 active-high output signals address the refresh RAM for character storage and display operations. The starting scan address is fully programmable and the ending scan address is determined by the total number of characters displayed, which is also programmable, in terms of characters/line and jines/frame. There are two selectable address modes for MAO-MA13: In the straight binary mode (R8, Mode Control, bit 2 = 0), characters are stored in successive memory locations. Thus, the software design must translate row and column character coor- dinates into sequentially-numbered addresses for Refresh memory operations. In the row/column mode (R8, Mode Control, bit 2 = 1), MAO- MA7 become column addresses CCO-CC7 and MA8-MA13 CRT Controller (CRTC) become row address CRO-CAS. In this case, the software manipulates characters in terms of row and column locations, but additional address compression circuits are needed to con- vert the CC0-CC7 and CRO-CRS5 addresses into a memory- efficient binary address scheme. RAO-RA4 (Raster Address Lines) These five active-high output signals select each raster scan within an individual character row. The number of raster scan lines is programmable and determines the character height, in- cluding spaces between character rows. The high-order line, RA4, is unique in that it can also function as a strobe output pin when the R6545 is programmed to oper- ate in the Transparent Address Mode. In this case the strobe is an active-high output and is true at the time the Refresh RAM updates address gates on to the address lines, MAO-MAT3. In this way, updates and readouts of the Refresh RAM can be made under control of the R6545 with only a small amount of external circuitry. 1 COMPLETE FIELD (VERTICAL TOTAL) VERTICAL DISPLAYED VSYNC mar |U UU UU U UU UUW DISPLAY | raoras XY YX OCC YO III OaaOOF 1 COMPLETE SCAN LINE (HORIZONTAL TOTAL) HORIZONTAL DISPLAYED Wl eS | | ENABLE HSYNC MAO-MA13 RAO-RA4 Ld Figure 2. Vertical and Horizontal TimingR6545/R6545E CRT Controller (CRTC) INTERNAL REGISTER DESCRIPTION SR . he i | reai d indicates thei _7_ UR Update Ready Table 1 summarizes the interna registers an indicates thelr 0 Register R31 has been either read or written by the address selection and read/write capabilities. cPu ADDRESS REGISTER 1 An update strobe has occurred. 7 6 5 4 3 2 1 Qo SR A A A _6 LAF LPEN Register Full ~J- i= 1M 3 2 1] Ao 0 Register R16 or R17 has been read by the CPU. 9) : . lepine! . 1 LPEN strobe has been received. This 5-bit write-only register is used as a pointer to direct CRTC/CPU data transfers within the CRTC. It contains the SR number of the desired register (0-31). When AS is low, this _5 VAT Vertical Re-Trace register may be loaded; when RS is high, the selected register 0 Scan is not currently in the vertical re-trace time. is the one whose identity is stored in this address register. 1 Scan is currently in its vertical re-trace time. NOTE: This bit goes to a 1 when vertical retrace STATUS REGISTER (SR) Starts. It goes to a0 five character clock times before 7 6 5 4 3 2 1 0 vertical re-trace ends to ensure that critical timings for refresh RAM operations are met. uR | LRE | vaT | _ _ _ - SR This 3-bit register contains the status of the CRTC. 4-0 Not used. Table 1. Internal Register Summary Address Reg. Reg. Register Bit CS|AS;4/3/2/1] 0] No. Register Name Stored Info. RDiWR| 7 6 5 4 3 2 1 0 1}/Jjf[J/-}] o]o0]/|||| |Address Reg. Reg. No. rad o/;0/||j|| | Status Reg. ao;[t]0f0/0/0]0/] RO | Horiz. Total # Charac. -1 ao} 1/0/0;0|0)11 Ri | Horiz. Displayed # Charac. v ao}; 1 /0})0)0]1 40} R2 | Horiz. Sync Position # Charac. w . # Scan Lines and o;}1/0/10/0/1/]1 ]R3 | VSYNC, HSYNC Widths # Char. Times 0}; 1/0)/0)]1]0)]0'] R4 | Vert. Total # Charac. Row -1 wt 0} 1/0]/0]1]0)] 11] RS | Vert. Total Adjust # Scan Lines o/]1/0/0]1]1)0] R6 | Vert. Displayed # Charac. Rows Oo} 1)0/0]1)]1 41 | R? | Vert. Syne Position # Charac. Rows wt oO}; 11/0)]1/0]0] 0} R8 | Mode Control o}|1{/0]1/010)]11|R9 | Scan Lines # Scan Lines -1 oO; 410/107 4 | | R10 | Cursor Start Scan Line No. a 0; 1/70]1 )0)1 4) 1 | R11 ; Cursor End Scan Line No. a Oo] 1/0/11] 040] Rt2 j Display Start Addr (H) Oo} 1/0/1/]1/]0); 1] R13 | Display Start Addr (L) a 0}; 1/0/1/]11] 1) 0] R14 } Cursor Position (H) |e oOo} 1/0 {1{1 7] 4 | 4 | R15 | Cursor Position (L) wile . . . . e 0 | 1]1/0]0] 0] 0 | Rt6 | Light Pen Reg (H) Pd e . . e e Oo} 1 /1)0)0/]0/] 1] R17 | Light Pen Reg (L) . . e . . . oj} 1/]1/0/]0] 11] 0 | R18 | Update Address Reg (H} . . . . . 0/1 /1/0{]0/] 1] 1 | R19 | Update Address Reg (L) . . e . . . . oO] 1/1/1444 ]1 4 1 | R31 | Dummy Location Notes: [e] Designates used bit in register Designates unused bit in register. Reading this bit is always 0, except for R31, which does not drive the data bus.R6545/R6545E CRT Controller (CRTC) ROHORIZONTAL TOTAL CHARACTERS to the line frequency to ensure flicker-free appearance. If the frame time is adjusted to be longer than the period of the line 7] e[>s[f[e+}tsafte2{tifo frequency, then RES may provide absolute synchronism. NUMBER OF CHARACTERS ~1 This 8-bit write-only register contains the total of displayed and non-displayed characters, minus one, per horizontal line. This register determines the frequency of HSYNC. R1IHORIZONTAL DISPLAYED CHARACTERS 7] 6/5 [4/3 [2] 1 | 0 NUMBER OF CHARACTERS This 8-bit write-only register contains the number of displayed characters per horizontal line. R2HORIZONTAL SYNC POSITION 7Ds[le]llel2)ls]s HORIZONTAL SYNC POSITION This 8-bit write-only register contains the position of HSYNC on the horizontal line, in terms of the character location number on the line. The position of the HSYNC determines the left to right location of the displayed text on the video screen. In this way, the side margins are adjusted. R3HORIZONTAL AND VERTICAL SYNC WIDTHS 7 6 5 4 3 2 1 Q V3 V2 vy Vo Hg He H, Ho This 8-bit write-only register contains the widths of both HSYNC and VSYNC as follows: HVSW 7-4 VSYNC Pulse Width The width of the vertical sync pulse (VSYNC) expressed as the number of scan lines. When bits 4-7 are all 0, VSYNC is 16 scan lines wide. HVSW 3-0 HSYNC Pulse Width The width of the horizontal sync pulse (HSYNC) expressed as the number of character clock times (CCLK). When bits 0-3 are all zero, HSYNC is 16 bit times wide. Control of these parameters allows the R6545 to interface with a variety of CRT monitors, since the HSYNC and VSYNC tim- ing signals may be accommodated without the use of external one shot timing. R4VERTICAL TOTAL ROWS 7 6 | 5 [4f[3fe2ef[31]0 _ NO. OF CHAR. ROWS ~1 The 7-bit Vertical Total Register contains the total number of character rows in a frame, minus one. This register, along with R, determines the overall frame rate, which should be close R5VERTICAL TOTAL LINE ADJUST 4 [3 f]e2{41]0 SCAN LINES 7 6 5 The 5-bit write-only Vertical Total Line Adjust Register (R5) con- tains the number of additional scan lines needed to complete an entire frame scan and is intended as a fine adjustment for the video frame time. R6EVERTICAL DISPLAYED ROWS 7 | 6 [5 | 4/3 [2/1 ]{ 0 = DISPLAYED CHAR. ROWS This 7-bit write-only register contains the number of displayed character rows in each frame. This determines the vertical size of the displayed text. R7VERTICAL SYNC POSITION 7/6 | s [4{f{s3ife2{1 ] o _ VERTICAL POSITION This 7-bit write-only register selects the character row time at which the vertical SYNC pulse occurs and, thus, positions the displayed text in the vertical direction. R8MODE CONTROL (MC) 7 6 5 4 3 2 1 0 UM(T) | US(T) | CSK | DES | RRA | RAD IMC This 8-bit write-only register selects the operating modes of the R6545, as follows: MC _7? _UM(T)Update/Read Mode (Transparent Mode) 0 Update occurs during horizontal and vertical blank- ing times with update strobe. 1 Update interieaves during $2 portion of cycle. MC _6 US(T)Update Strobe (Transparent Mode) 0 Pin 34 functions as memory address (RA4). 1 Pin 34 functions as update strobe (STB). Mc _5 CSK Cursor Skew 0 No delay. 1 Delays Cursor one character time. MC _4 DES ~Display Enable Skew 0 No delay. 1 Display Enable delays one character time.R6545 mc 3 RRA Refresh RAM Access 0 Shared memory access 1 Transparent memory access M ic _2_ RAD Refresh RAM Addressing Mode 0 Straight binary addressing 1 Row/column addressing MC1-MCO IMC interlace Mode Control _1 0 Operation x G Non-interlace 0 1 Interlace SYNC raster scan 1 1 Interlace SYNC and video raster scan R9ROW SCAN LINES 7]/615 |4]3 /2 ]1 {| SCAN LINES -1 This 5-bit write-only register contains the number of scan lines, minus one, per character row, including spacing. A10CURSOR START LINE 7] 615 |4]3 ]2 {1 {[ 0 _ B, Bo START SCAN LINE R11CURSOR END LINE 7] 6 ]5 |4/3 [2 ]1 | o END SCAN LINE These 5-bit write-only registers select the starting and ending scan lines for the cursor. In addition, bits 5 and 6 of R10 are used to select the cursor blink mode, as follows: 8, Bo Cursor Operating Mode 6 9 Display Cursor Continuously 0 1 Blank Cursor 1 0 Blink cursor at 1/16 Field Rate 1 1 Blink Cursor at 1/32 Field Rate Aone character wide cursor can be controlled by storing values into the Cursor Start Line (R10) and Cursor End Line (R11) registers and into the Cursor Position Address High (R14) and Cursor Position Low (R15) registers. R12DISPLAY START ADDRESS HIGH 7 6 s | 4 ]3 [2 [1] 0 ~ | DISPLAY START ADDRESS HIGH R13DISPLAY START ADDRESS LOW 7] 6[sf[4{fs3ife2i{31 io DISPLAY START ADDRESS LOW CRT Controller (CRTC) These registers together form a 14-bit register whose contents are the memory address of the first character to be displayed (the character on the top left of the video display, as in Figure 4). Subsequent memory addresses are generated by the R6545 as a result of CCLK input pulses. Scrolling of the display is accom- plished by changing R12 and R13 to the memory address of the first character of the first line of text to be displayed. Entire pages of text may be scrolled or changed as well via R12 and R13. R14CURSOR POSITION HIGH 7)]6|]5 ]4]3 | 2{[+1 | o | - CURSOR POSITION HIGH R15CURSOR POSITION LOW 7 [6 ]s5 | 4]3 | 2 [1 | 0 CURSOR POSITION LOW These registers together form a 14-bit register whose contents are the memory address of the current cursor position. When the video display scan counter (MA lines) matches the contents of this register, and when the scan line counter (RA lines) falls within the bounds set by R10 and R11, then the CURSOR out- put becomes active. Bit 5 of the Mode Control Register (R8) may be used to delay the CURSOR output by a full CCLK time to accommodate slow access memories. The cursor is positioned on the screen by loading the Cursor Position Address High (R14) and Cursor Position Address Low (R15) registers with the desired refresh RAM address. The cursor can be positioned in any of the 16K character positions. Hard- ware paging and data scrolling is thus allowed without loss of cursor position. Figure 3 is an example of several cursor options. UNOERLINE OVERLINE BOX CURSOR CURSOR CURSOR 1 Ww =OVOMNATH AWN os 1 CURSOR START CUASOR START CURSOR START LINE = 9 LINE = 1 LINE = 7 CURSOR END CURSOR END CURSOR END LINE = 9 LINE =1 LINE = 9 Figure 3. Cursor Display Scan Line Control ExamplesCRT Controller (CRTC) R6545/RA6545E R16LIGHT PEN HIGH 7 | 6 | 5s | 4] 3 fe ]1 { o _ fo LPEN HIGH R17LIGHT PEN LOW 7 {| 6 | 5 [| 4 [3 ]2f41 fo LPEN LOW These registers together form a 14-bit register whose contents are the light pen strobe position, in terms of the video display address at which the strobe occurred. When the LPEN input changes from low to high, then, on the next negative-going edge of CCLK, the contents of the internal scan counter is stored in registers R16 and R17. R18UPDATE ADDRESS HIGH s | 4/3 [2 ]1]0 UPDATE ADDRESS HIGH 7 6 Ri9UPDATE ADDRESS LOW 7 | 6 | 5 | 4 [3 [2 |]4 UPDATE ADDRESS LOW iz These registers together comprise a 14-bit register whose con- tents are the memory address at which the next read or update will occur (for transparent address mode only). Whenever a read/update occurs, the update location automatically incre- ments to allow for fast updates or readouts of consecutive character locations. The section on REFRESH RAM ADDRESS- ING describes this more fully. R31DUMMY LOCATION 6 7 4 This register does not store any data, but i: required to detect transparent addressing updates. This is necessary to increment the Update Address Register and to set the Update Ready bit in the status register. REGISTER FORMATS Register pairs R12/R13, R14/R15, R16/R17, and R18/R19 are formatted in one of two ways: (1) Straight binary, if register R8, bit 2 = 0 (2) Row/Cotumn, if register R8, bit 2 = 1. In this case the low byte is the Character Column and the high byte is the Character Row. r NUMBER OF HORIZONTAL TOTAL CHARACTERS (RO +1) a NUMBER OF HORIZONTAL DISPLAYED CHARACTERS (R1) A DISPLAY START ADDRESS HIGH (R12) wx DISPLAY START ADDRESS LOW (R13) r a= = = = j NUMBER OF Ae === SCAN LINES (R9) ae SES CURSOR START LINE (R10) x CURSOR END LINE (R11) XY CURSOR POSITION ADDRESS HIGH (R14) NUMBER OF vertical J CURSOR POSITION ADDRESS LOW (R15) | opnraL DISPLAY RETRACE NUMBER OF! ows PERIOD TOTAL 4 (R6) (NON-DISPLAY) ROWS DISPLAY PERIOD (R4 +1) \ VERTICAL RETRACE PERIOD (NON-DISPLAY) [ VERTICAL TOTAL { Po st a a jp - ADJUST (R5) == Figure 4. Video Display Format 2-69R6545 CRT Controller (CRTC) DESCRIPTION OF OPERATION VIDEO DISPLAY Figure 4 indicates the relationship of the various program reg- isters in the R6545 and the resulant video display. Non-displayed areas of the Video Display are for horizontal and vertical retrace functions of the CRT monitor. The horizontal and vertical sync signals, HSYNC and VSYNC, are programmed to occur during these intervals and trigger the retrace in the CRT monitor. The pulse widths are constrained by the monitor require- ments. The time position of the pulses may be adjusted to vary the display margins (left, right, top, and bottom). REFRESH RAM ADDRESSING There are two modes of addressing for the video display memory: Shared Memory Mode (R8, BIT 3 = 0) In this mode, the Refresh RAM address lines (MAQ-MA13) directly reflect the contents of the internal refresh scan charac- ter counter. Multiplex control, to permit addressing and selec- tion of the RAM by both the CPU and the CRTC, must be provided externally to the CRTC. In the Row/Column address mode, lines MAQ-MA7 become character column addresses (CCO-CC7) and MA8-MA13 become character row addresses (CRO-CRS). Figure 5 illustrates the system configuration. Transparent Memory Addressing (R8, BIT 3 = 1) For this mode, the display RAM is not directly accessible by the CPU, but is controlled entirely by the R6545. All CPU accesses are made via the R6545 and a small amount of external cir- cuitry. Figure 6 shows the system configuration for this ap- proach. Bus aus pvevNc BUS HSYNC Re54S _ CRT CONTROLLER DISPLAY ENABLE CURSOR To MaAO-MA13 RAO-RAS 10 0 Fb DISPLAY ADDRESS CIRCUITS cpu baci SCAN LINE SHIFT Nv ) CONTROL, COUNT REGISTER cpu ADDRESS BUS gp VIDEO ADDRESS VIDEO -_ DISPLAY C > cpu RAM CHARACTER ROM | SCAN LINE DATA DATA DOT PATTERN Figure 5. Shared Memory System Configuration SYSTEM BUS RS545 CRT CONTROLLER RAS MAO-MA13 RAO-RAS UPDATE DISPLAY/UPDATE| | SCAN LINE cpu STROBE ADDRESS COUNT DATA VIDEO ICHARACTER| HOLD on DISPLAY 0 cpu RAM ROM DATA BUS CHARACTER = CHARACTER DATA DATA Figure 6. Transparent Memory Addressing System Configuration (Data Hold Latch Needed for Horizontal/Vertical Blanking Updates, Only). 2-70R6545/R6545E ADDRESSING MODES Figure 7 illustrates the address sequence for both modes of the Refresh RAM address. Row/Column In this mode, the CATC address lines (MAO-MA13) generate 8 column (MAO-MA7) and 6 row (MA8-MA13) addresses. Extra hardware is needed to compress this addressing into a straight binary sequence in order to conserve memory in the refresh RAM (register R8, bit 2 is a 1). Binary In this mode, the CRTC address lines are straight binary and no compression circuits are needed. However, software com- plexity increases since the CRT characters cannot be stored in terms of their row and column locations, but must be sequen- tial (register RB, bit 2 is a 0). USE OF DYNAMIC RAM FOR REFRESH MEMORY The R6545 permits use of dynamic RAMS as storage devices for the Refresh RAM by continuing to increment memory addresses in the non-display intervals of the scan. This is a CRT Controller (CRTC) viable technique, since the Display Enable signal controls the actual video display blanking. Figure 7 illustrates Refresh RAM addressing for both row/column and binary addressing for 80 columns and 24 rows with 10 non-displayed columns and 10 non-displayed rows. Note that the straight-binary mode has the advantage that all display memory addresses are stored in a continuous memory block, starting with address 0 and ending at 1919. The dis- advantage with this method is that, if it is desired to change a displayed character location, the row and column identity of the location must be converted to its binary address before the memory may be written. The row/column mode, on the other hand, does not need to undergo this conversion. However, memory is not used as efficiently, since the memory addresses are not continuous, gaps exist. This requires that the system be equipped with more memory than actually used and this extra memory is wasted. Alternatively, address compression logic may be employed to translate the row/column format into a con- tinuous address block. The user selects whichever mode is best for the given applica- tion. The trade-offs between the modes are software versus hard- ware. Straight-binary mode minimizes hardware requirements and row/column minimizes software requirements. | ess TOTAL = 90 | 197 | 198 }189 7 160) 161 |---|] 169 237 | 238 | 239 | 240 4 241 |- - -] 249 Koy TOTAL ' t spa --127071271 STRAIGHT BINARY ADDRESSING SEQUENCE DISPLAY = BO 7 COLUMN ADDRESS (MA0-MA7) | 9 1 2 77 78 79 | 20 at a QO 2 y---|---| 77 | 7B | 79 | 80 | at |-- 8 256 | 257 | 258 |-- -}-- 335 [336 | 337 |---) 345 CO TOTAL = 90 tC 24 512 7513] 514 -|-~-] 589 | 590 ; 591 | 592 | 593 |- - -} 60! 4 > TOTAL ( DISPLAY ROW ADDRESS (MAG-MA13) ND x xlsx [ey ROW/COLUMN ADDRESSING SEQUENCE Figure 7. Display Address Sequences (with Start Address = 0) for 80 x 24 ExampleR6545/R6545E MEMORY CONTENTION SCHEMES FOR SHARED MEMORY ADDRESSING From the diagram of Figure 5, it is clear that both the R6545 and the system CPU must address the video display memory. The R6545 repetitively fetches character information to generate the video signals in order to keep the screen display active. The CPU occasionally accesses the memory to change the displayed information or to read out current data characters. Three ways of resolving this dual-contention requirement are apparent: CPU Priority In this technique, the address lines to the video display mem- ory are normally driven by the R6545 unless the CPU needs access, in which case the CPU addresses immediately over- ride those from the R6545 giving the CPU immediate access. $1 and @2 Memory interleaving This method permits both the R6545 and the CPU to access the video display memory by time-sharing. During the @1 por- tion of each cycle (the time when $2 is low), the R6545 address outputs are gated to the video display memory. Dur- ing $2 time, the CPU address lines are switched in. This way, both the R6545 and the CPU have unimpeded access to the memory. Figure 8 illustrates these timings. CPU CYCLE -ePe CPU CYCLE a CLOCK VIDEO DISPLAY CPU MEMORY ADORESS ADDRESSES Figure 8. $1 and $2 Interleaving * Vertical Blanking With this approach, the address circuitry is identical to the case for CPU Priority updates. The only difference is that the Vertical Retrace status bit (bit 5 of the Status Register) is used by the CPU so that access to the video display memory is only made during vertical blanking time (when bit 5 is a 1). In this way, no visible screen perturbations result. See Figure 10 for details. 2-72 CRT Controller (CRTC) TRANSPARENT MEMORY ADDRESSING In this mode of operation, the video display memory address lines are not switched by contention circuits, but are generated by the R6545. In effect, the contention is handled by the R6545. As a result, the schemes for accomplishing CPU memory access are different: 61 and 62 Interleaving This mode is similar to the interleave mode used with shared memory. !n this case, however, the $2 address is generated from the Update Address Register (R18 and R19) in the R6545. The CPU loads the address to be accessed into FA18/R19. This address is then gated onto the MA lines during $2. Figure 9 shows the timing. fe CPU CYCLE w}<._ CPU CYCLE 62 CLOCK MAO+MAI3 Figure 9. @1 and $2 Transparent Interleaving Horizontal/Vertical Blanking In this mode, the CPU loads the Update Address into R18 and R19. This address is gated onto the MA lines during horizontal or vertical blank times, so memory accesses do not interfere with the display appearance. Pin 34 can be pro- grammed, by R8 bit 6, to function as an update strobe which signals the presence of an update address on the MA lines. Data hold latches are necessary to temporarily retain the character to be stored until the retrace time occurs. In this way, the system CPU is not halted waiting for the blanking time to arrive. Figure 11 illustrates the address and strobe timing for this mode. CURSOR AND DISPLAY ENABLE SKEW CONTROL Bits 4 and 5 of the Mode Control register (Ri8) are used to delay the Display Enable and Cursor outputs, respectively. Figure 12 illustrates the effect of the delays.R6545/R6545E CAT Controller (CRTC) FRAME VERTICAL DISPLAYED FRAME VERTICAL BLANKING DISPLAY ' ENABLE 1 1 [ i ' ! ' ' I 1 \ | 1 VERTICAL BLANKING STATUS BIT (STATUS Q" = DISPLAY ACTIVE REGISTER BIT 5) 1" = VERTICAL SWITCHES STATE AT BLANKING END OF LAST DISPLAYED ACTIVE SCAN LINE. Figure 10. Operation of Vertical Blanking Status Bit 2-73R6545/R6545E CRT Controller (CRTC) CCLK l HORIZONTAL/VERTICAL BLANKING DISPLAY ' | DISPLAY { \ ENABLE | | ; | NON-DISPLAY t CRT DISPLAY + 7 , $j ADDRESSES = ' \ CRT DISPLAY ADDRESSES sh ____ ] | I MAO- UPDATE MA13 ADDRESS : : V, { | \ | i | Pe | 1 qT T UPSTB Figure 11. Retrace Update Timing ccLK | | | | | | | | | - ' ' ' (NO DELAY) CURSOR ~+ 1 t (WITH DELAY) | | L = DISPLAY {NO DELAY} | ENABLE _| POSITIVE EDGE (WITH DELAY) (NO DELAY) DISPLAY | oe ENABLE | NEGATIVE EOGE (WITH DELAY) | Figure 12. Cursor and Display Enable Skew 2-74R6545/R6545E CRT Controller (CRTC) BUS WRITE TIMING CHARACTERISTICS (Vc = 5.0V + 5%, Ta = T. fo Ty, unless otherwise noted) 1 MHz 2 MHz Symbol Characteristic Min. Max. Min. Max. Unit teve Cycle Time 1.0 - 0.5 - us ton 62 Pulse Width High 440 - 200 - ns tot $2 Pulse Width Low 420 _ 190 - ns tacw Address Set-Up Time 80 _ 40 _ ns toan Address Hold Time 0 - 0 - ns twew RAW Set-Up Time 80 - 40 - ns town RW Hold Time 0 - 0 - ns toow Data Bus Set-Up Time 165 _ 60 ~ ns thw Data Bus Hold Time 10 - 10 - ns {ta and te = 10 to 30 ns) BUS READ TIMING CHARACTERISTICS (vec = 5.0V + 5%, Ta = T, to Ty, unless otherwise noted) 1 MHz 2 MHz Symbol! Characteristic Min. Max. Min. Max. Unit tere Cycle Time 1.0 - 0.5 - ps tou $2 Pulse Width 440 - 200 - ns te. $2 Pulse Width Low 420 _ 190 - ns tacr Address Set-Up Time 80 - 40 _ ns tcan Address Hold Time 0 _ 0 _ ns twor RW Set-Up Time 80 ~ 40 - ns topa Read Access Time (Valid Data) - 290 - 150 ns tur Read Hold Time 10 _ 10 - ns tepa Data Bus Active Time (Invalid Data) 40 - 40 - ns (tg and te = 10 to 30 ns) BUS WRITE TIMING WAVEFORMS $2 CS, AS RW DATA BUS BUS READ TIMING WAVEFORMS $2 CS, RS RW DATA BUS 2-75R6545/R6545E MEMORY AND VIDEO INTERFACE CHARACTERISTICS (Vec = 5.0V + 5%, Ta = T, to Ty, unless otherwise noted) CRT Controller (CRTC) R6545 R6545E Symbol! P. Min. Typ. Max. Min. Typ. Max. Units toc Minimum Clock Pulse Width, High 200 130 ns tocy Clock Frequency 25 3.7 MHz ta, tr Rise and Fall Time for Clock Input 20 20 ns twap Memory Address Delay Time 180 300 100 160 ns . trap Raster Address Delay Time 180 300 100 160 ns | toro Display Timing Delay Time 240 450 160 300 ns tuso Horizontal Sync Delay Time 240 450 160 300 ns tyso Vertical Sync Delay Time 240 450 160 300 ns tepp Cursor Display Timing Delay Time 240 450 160 300 ns MEMORY AND VIDEO INTERFACE WAVEFORMS f tecy 2.0V 2.0V fy N CCLK o.ay N 0.8V j L 0.8v ta it t >> COR tC | 2.4V MAO-MA13 av e tan <twao | 2.4V RAO-RA4 0.4V < trad + tran zw DISPLAY ENABLE 2.4 0.av Oe ; top * toro v2 HSYNC, VSYNC 0.4V eS |, tuso wis tysp 2 Vsp cursor 2. 0.4v [< tcoo [+ tcp 2-76R6545/R6545E CRT Controller (CRTC) LIGHT PEN STROBE TIMING CHARACTERISTICS (For Reference Only) R6545 R6545A Symbol Characteristic Min. Max. Min. Max Unit tlpH LPEN Hold Time 150 _ 100 _ ns tips LPEN Setup Time _ 120 _ 120 ns tipe CCLK to LPEN Delay - 0 _ 0 ns Note: tp, t- = 20 ns (max) LIGHT PEN STROBE TIMING WAVEFORMS CCLK SEE NOTE +jLP1 {Lp LPEN hon MAO-MA13 n x n+ xX n+2 x NOTE: Safe time position for LPEN positive edge to cause address n+2 to load into Light Pen Register. tip2 and t,p, are time positions causing uncertain results. TEST LOAD Voc R6545 PIN R = 11KQ FOR DO-D7 = 24K0 FOR ALL OTHER OUTPUTS C = 130 pF TOTAL FOR DO-D7 = 30 pF ALL OTHER OUTPUTS 2-77R6545/R6545E CRT Controller (CRTC) CRTC Register Comparison GENERAL FUNCTIONS MC6845R REGISTER HO6845R HD6845S RR6545-1 FI6S45/R6545E RO HORIZONTAL TOT TOT TOT. TOT-1 TOT Ri HORIZONAL DISP ATUAL ACTUAL ACTUAL ACTUAL A2 HORIZONTAL ACTUAL ACTUAL ACTUAL ACTUAL SYNC RS HORIZ AND VERT HORIZONTAL HORIZONTAL HORIZONTAL HORIZONTAL SYNC WIDTH AND VERTICAL AND VERTICAL AND VERTICAL Ra VERTICAL TOT TOT-1 TOT-1 TOT-1 TOT-1 ANY VALUE R5 VERTICAL ANY VALUE ANY VALUE EXCEPT ANY VALUE TOT ADJ R5 = ROH* X R VERTICAL DISP ANY VALUE ANY VALUE ANY VALUE ANY VALUE <R4 <A4 <R4 <R4 R7 VERTICAL PNG POS ACTUAL ACTUAL ACTUAL ACTUAL Re MODE REG INTERLACE INTERLACE _ INTERLACE BITS 0 and 1 MODE SELECT MODE SELECT MODE SELECT ROWICOLUMN ROW/COLUMN airs 2 _ _ OR STRAIGHT OR STRAIGHT BINARY BINARY ADDRESSING ADDRESSING SHARED OR SHARED OR BITS 3 _ _ TRANSPARENT TRANSPARENT ADDR ADDR BITS 4 DISPEN SKEW DISPEN SKEW DISPEN SKEW BITS 5 _ DISPEN SKEW CURSOR SKEW CURSOR SKEW BITS 6 CURSOR SKEW RAQ/UPSTB RA4/UPSTB TRANSPARENT TRANSPARENT BITS 7 - CURSOR SKEW MODE SELECT MODE SELECT R9 SCAN LINES ToT TOT! TOT-1 TOT-1 R10 CURSOR START ACTUAL ACTUAL ACTUAL ACTUAL R11 CURSOR END ACTUAL ACTUAL ACTUAL ACTUAL F12/R13 DISP ADDR WRITE ONLY READWAITE WRITE ONLY WRITE ONLY ae CURSOR WRITE ONLY READIWRITE READAWRITE AEADWRITE Rig/R17 LPEN REG READ ONLY READ ONLY READ ONLY READ ONLY R1g/A19 UPDATE NIA WA TRANSPARENT TRANSPARENT ADDR REG MODE ONLY MODE ONLY TRANSPARENT TRANSPARENT R31 DUMMY REG NIA NIA Sy Sy STATUS REG NO NO YES YES INTERLACE SYNC _ _ _ TOT-1 = ODD RO TOT-1 = ODD TOT-+ = ODD Oe EVEN Ra VERTICAL TOT-1 TOT-2 _ TOT RG VERT DISP TOTI2 TOT _ TOT R7 VERT SYNC ACTUAL ACTUAL _ ACTUAL TOT-1 TOT-2 TOT-1 TOT! RG SCAN LINES EVEN ONLY ODD/EVEN ODDIEVEN ODD/EVEN R10 CURSOR START BOTH ODD OR ODD/EVEN ODD/EVEN R11 GURSOR END BOTH EVEN ODD/EVEN _ ODD/EVEN CHARACTER CLOCK FREQUENCY CCLK 2.5 MHz 3.7 MHz 2.5 MHz 3.7 MHz* Notes: = Does not apply * R6545 = 2.5 MHz R6545E = 3.7 MHz 2-78CRT Controller (CRTC) R6545/R6545E ABSOLUTE MAXIMUM RATINGS* Parameter Symbol Value Unit Supply Voltage Voc ~0.39 to +7.0 Vv Input Voltage Vin -0.3 to +7.0 Vv Operating Temperature Range Ta C Commercial Oto +70 Industrial -40 to +85 Storage Temperature Tste -55 to +150 | C DC CHARACTERISTICS (Vcc = 5.0V 5%, Ty = T_ to Ty, unless otherwise noted) NOTE: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this document is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameter Symbol Min. Typ. Max. Unit Test Conditions Input High Voltage Ving 2.0 Vee Vv Input Low Voltage Vic -0.3 0.8 v Input Leakage lin _ 25 pA $2, RW, RES, CS, RS, LPEN, CCLK Three-State Input Leakage rst 10.0 pA Vin = 0.4V to 2.4V DO-D7 Output High Voltage Vou 2.4 Vv 00-D7 lLoap = 205 pA All other outputs ILoap = 100 pA Output Low Voltage Vor - 0.4 v lLloap = 1.6 mA Input Capacitance _ Cin $2, RW, RES, CS, RS, LPEN, CCLK - 10.0 pF Vin = OV Do-D7 - 12.5 Ta = 25C Output Capacitance Cour _ 10.0 pF f= 1MHz Power Dissipation Pp _ mw Veco = 5.25V Commercial 350 700 industrial 350 800 2-79R6545/R6545E CRT Controller (CRTC) PACKAGE DIMENSIONS IMETERS | _ INCHES 40-PIN PLASTIC DIP MILLIMETE! om | min | max | MN | MAX A_| 51.28 | 52.32 | 2.040 | 2.060 2 B | 1372 | 1422 | 0.540 | 0.560 B c | 3.55 | 5.06 | 0.140 | 0.200 Dp | 036 | 0.51 | 0.014 | 0.020 ' 20 F | 102 | 1:52 | 0.040 | 0.060 FITTV TUT UT TVU OT UU IU Ss 2.54 BSC 9.100 BSC le H | 1.65 | 2.16 | 0.065 | 0.085 A L c Y_ | 020 | 0.30 | 0.008 | 0.012 N : [| 330] 4.32 | 0.130 | 0.170 sy L 15.24 BSC 0.800 BSC | i | | 7 t J w [7 ioe [7 10 iH at leg we ole p Kee nN | ost | 1.02 | 0.020 | 0.040 44-PIN PLASTIC LEADED CHIP CARRIER (PLCC) - SEATING PLANE INDEX MILLIMETERS INCHES: CORNER pim | MIN | MAX | MIN | MAX _ t a | 414] 439 | 0.163 | 0.173 at | 137 | 1.47 | 0.054 | 0.088 q "K a2 | 231 | 2.46 | 0.091 | 0.097 Oo q b | oas7tve | 0.018 TP q PIN 1 p | 17.45 | 17.60 | 0.687 | 0.693 q : Z y : 02 {| INDICATOR pi | 1646 | 1656 | 0.648 | 0.652 | pz | 12.62 | 12.78 | 0.497 | 0.503 2 D3 | 15.75 REF 0.620 REF UUUTTOUTOoT e 1.27 BSC 0.050 BSC. TOP VIEW SIDE VIEW h 1.15 TYP 0.045 TYP J 0.25 TYP 0.010 TYP. | at a 45 TYP 45 TYP a a 0.69 TYP 0.035 TYP Rt 0.25 TYP 0.010 TYP a R SECTION A-A TYP FOR BOTH AXIS (EXCEPT FOR BEVELED EDGE) CHAM. 11 PINS EJECTOR PIN MARKS h x 45 PER SIDE 4 PLCS BOTTOM OF 3 PLCS EQUALLY PACKAGE ONLY SPACES (TYPICAL) BOTTOM VIEW