MKV31F512VLL12P - NXP SEMICONDUCTORS

Kinetis KV30F 64 KB/128 KB

Flash

100 MHz ARM® Cortex®-M4 Based Microcontroller with FPU

The KV30 MCU family is a highly scalable member of the Kinetis

V series and provides a high-performance, cost-competitive

motor-control solution. Built on the ARM® Cortex®-M4 core

running at 100 MHz, combined with floating point and DSP

capability, it delivers a highly capable platform enabling

customers to build a highly scalable solution portfolio.

Additional features include:

• Dual 16-bit ADCs sampling at up to 1.2 MS/s in 12-bit

mode

• Highly accurate and flexible motor control timers

• Excellent processing efficiency, 100 MHz ARM® Cortex®-

M4-based device with Floating-Point Unit in a tiny form

factor

• Enabled to support Kinetis Motor Suite (KMS), a bundled

hardware and software solution that enables rapid

configuration of BLDC and PMSM motor drive systems.

Performance

• 100 MHz ARM Cortex-M4 core with DSP instructions

delivering 1.25 Dhrystone MIPS per MHz

Memories and memory interfaces

• Up to 128 KB of embedded flash and 16 KB of RAM

• Preprogrammed Kinetis flashloader for one-time, in-

system factory programming

System peripherals

• 4-channel DMA controller

• Independent External and Software Watchdog monitor

Clocks

• Crystal oscillator: 32-40 kHz or 3-32 MHz

• Three internal oscillators: 32 kHz, 4 MHz, and 48 MHz

• Multi-purpose clock generator with FLL

Security and integrity modules

• Hardware CRC module

• 128-bit unique identification (ID) number per chip

• Flash access control to protect proprietary software

Human-machine interface

• Up to 46 general-purpose I/O (GPIO)

Analog modules

• Two 16-bit SAR ADCs (1.2 MS/s in 12bit mode)

• One 12-bit DAC

• Two analog comparators (CMP) with 6- bit DAC

• Accurate internal voltage reference (not available in

32-pin QFN package)

Communication interfaces

• One SPI module

• Two UART modules

• One I2C: Support for up to 1 Mbps operation

Timers

• One 6-channel motor-control general-purpose/PWM

timer

• Two 2-channel motor-control general-purpose

timers with quadrature decoder functionality

Operating Characteristics

• Voltage range (including flash writes): 1.71 to 3.6 V

• Temperature range (ambient): -40 to 105°C

Kinetis Motor Suite

• Supports Velocity and Position control of BLDC &

PMSM motors

MKV30F128Vxx10

MKV30F64Vxx10

MKV30F128Vxx10P

MKV30F64Vxx10P

64 LQFP (LH)

10 x 10 x 1.4 Pitch 0.5

48 LQFP (LF)

7 x 7 x 1.4 Pitch 0.5

32 QFN (FM)

5 x 5 x 1 Pitch 0.5 mm

Freescale Semiconductor, Inc. KV30P64M100SFA

Data Sheet: Technical Data Rev. 4, 02/2016

• Implements Field Orient Control (FOC) using Back

EMF to improve motor efficiency

• Utilizes SpinTAC control theory that improves

overall system performance and reliability

Ordering Information

Part Number Memory Number of GPIOs

Flash (KB) SRAM (KB)

MKV30F128VLH10 128 16 46

MKV30F128VLF10 128 16 35

MKV30F128VFM10 128 16 26

MKV30F64VLH10 64 16 46

MKV30F64VLF10 64 16 35

MKV30F64VFM10 64 16 26

MKV30F128VLF10P 120 16 35

MKV30F64VLH10P156 16 46

MKV30F64VLF10P156 16 35

1. This part number is subject to removal

Related Resources

Type Description Resource

Selector

Guide

The Freescale Solution Advisor is a web-based tool that features

interactive application wizards and a dynamic product selector.

Product Selector

Product Brief The Product Brief contains concise overview/summary information to

enable quick evaluation of a device for design suitability.

KV30FKV31FPB

Reference

Manual

The Reference Manual contains a comprehensive description of the

structure and function (operation) of a device.

KV30P64M100SFARM

Data Sheet The Data Sheet includes electrical characteristics and signal

connections.

This document.

KMS User

Guide

The KMS User Guide provides a comprehensive description of the

features and functions of the Kinetis Motor Suite solution.

Kinetis Motor Suite User’s Guide

(KMS100UG)1

KMS API

Reference

Manual

The KMS API reference manual provides a comprehensive description of

the API of the Kinetis Motor Suite function blocks.

Kinetis Motor Suite API

Reference Manual

(KMS100RM)1

Chip Errata The chip mask set Errata provides additional or corrective information for

a particular device mask set.

Kinetis_V_0N36M

Package

drawing

Package dimensions are provided by the part number:

• MKV30F64VLF10P

• MKV30F64VLH10P

• MKV30F128VLH10

• MKV30F128VLF10

• MKV30F128VFM10

• MKV30F128VLF10P

•98ASH00962A

•98ASS23234W

•98ASH00962A

•98ARE10566D

•98ASH00962A

1. To find the associated resource, go to freescale.com and perform a search using Document ID

2Kinetis KV30F 64 KB/128 KB Flash, Rev. 4, 02/2016

Freescale Semiconductor, Inc.

Figure 1 shows the functional modules in the chip.

Memories and Memory Interfaces

Program

(Up to 128 KB)

RAM

CRC

Programmable

Analog Timers Communication InterfacesSecurity

and Integrity

Clocks

Frequency-

Core

Debug

interfaces DSP

Interrupt

controller

Comparator

16-bit

timer

Human-Machine

Interface (HMI)

Up to

System

DMA (4 ch)

Low-leakage

wakeup

locked loop

reference

Internal

clocks

delay block

timers

interrupt

Periodic

oscillators

Low/high

frequency

UART

Cortex™-M4ARM

FPU

voltage ref

Timers

x1 (6ch)

SAR ADC x2 SPI

High

performance

Flash access

control

low-power

46 GPIOs

(16 KB)

flash

Internal

watchdogs

and external

with 6-bit DAC

12-bit DAC

x2 (2ch)

16-bit

Figure 1. Functional block diagram

Kinetis KV30F 64 KB/128 KB Flash, Rev. 4, 02/2016 3

Freescale Semiconductor, Inc.

Table of Contents

1 Ratings....................................................................................5

1.1 Thermal handling ratings................................................. 5

1.2 Moisture handling ratings................................................ 5

1.3 ESD handling ratings.......................................................5

1.4 Voltage and current operating ratings............................. 5

2 General................................................................................... 6

2.1 AC electrical characteristics.............................................6

2.2 Nonswitching electrical specifications..............................6

2.2.1 Voltage and current operating requirements....... 6

2.2.2 LVD and POR operating requirements................7

2.2.3 Voltage and current operating behaviors.............8

2.2.4 Power mode transition operating behaviors........ 9

2.2.5 Power consumption operating behaviors............ 10

2.2.6 EMC radiated emissions operating behaviors.....16

2.2.7 Designing with radiated emissions in mind..........17

2.2.8 Capacitance attributes.........................................17

2.3 Switching specifications...................................................17

2.3.1 Device clock specifications..................................17

2.3.2 General switching specifications......................... 18

2.4 Thermal specifications.....................................................18

2.4.1 Thermal operating requirements......................... 19

2.4.2 Thermal attributes................................................19

3 Peripheral operating requirements and behaviors.................. 20

3.1 Core modules.................................................................. 20

3.1.1 SWD electricals .................................................. 20

3.1.2 JTAG electricals.................................................. 21

3.2 System modules.............................................................. 24

3.3 Clock modules................................................................. 24

3.3.1 MCG specifications..............................................24

3.3.2 IRC48M specifications.........................................26

3.3.3 Oscillator electrical specifications........................26

3.4 Memories and memory interfaces................................... 29

3.4.1 Flash electrical specifications..............................29

3.5 Security and integrity modules........................................ 30

3.6 Analog............................................................................. 30

3.6.1 ADC electrical specifications............................... 30

3.6.2 CMP and 6-bit DAC electrical specifications....... 34

3.6.3 12-bit DAC electrical characteristics....................37

3.6.4 Voltage reference electrical specifications.......... 40

3.7 Timers..............................................................................41

3.8 Communication interfaces............................................... 41

3.8.1 DSPI switching specifications (limited voltage

range).................................................................. 42

3.8.2 DSPI switching specifications (full voltage

range).................................................................. 43

3.8.3 Inter-Integrated Circuit Interface (I2C) timing...... 45

3.8.4 UART switching specifications............................ 47

3.9 Kinetis Motor Suite.......................................................... 47

4 Dimensions............................................................................. 47

4.1 Obtaining package dimensions....................................... 47

5 Pinout......................................................................................48

5.1 KV30F Signal Multiplexing and Pin Assignments............48

5.2 Recommended connection for unused analog and

digital pins........................................................................50

5.3 KV30F Pinouts.................................................................51

6 Part identification.....................................................................54

6.1 Description.......................................................................54

6.2 Format............................................................................. 54

6.3 Fields............................................................................... 55

6.4 Example...........................................................................55

7 Terminology and guidelines.................................................... 56

7.1 Definitions........................................................................56

7.2 Examples.........................................................................56

7.3 Typical-value conditions.................................................. 57

7.4 Relationship between ratings and operating

requirements....................................................................57

7.5 Guidelines for ratings and operating requirements..........58

8 Revision History...................................................................... 58

4Kinetis KV30F 64 KB/128 KB Flash, Rev. 4, 02/2016

Freescale Semiconductor, Inc.

1 Ratings

1.1 Thermal handling ratings

Symbol Description Min. Max. Unit Notes

TSTG Storage temperature –55 150 °C 1

TSDR Solder temperature, lead-free — 260 °C 2

1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.

2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic

Solid State Surface Mount Devices.

1.2 Moisture handling ratings

Symbol Description Min. Max. Unit Notes

MSL Moisture sensitivity level — 3 — 1

1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic

Solid State Surface Mount Devices.

1.3 ESD handling ratings

Symbol Description Min. Max. Unit Notes

VHBM Electrostatic discharge voltage, human body model -2000 +2000 V 1

VCDM Electrostatic discharge voltage, charged-device

model

-500 +500 V 2

ILAT Latch-up current at ambient temperature of 105°C -100 +100 mA 3

1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human

Body Model (HBM).

2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for

Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.

3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.

1.4 Voltage and current operating ratings

Ratings

Kinetis KV30F 64 KB/128 KB Flash, Rev. 4, 02/2016 5

Freescale Semiconductor, Inc.

Symbol Description Min. Max. Unit

VDD Digital supply voltage –0.3 3.8 V

IDD Digital supply current — 145 mA

VDIO Digital input voltage –0.3 VDD + 0.3 V

VAIO Analog1–0.3 VDD + 0.3 V

IDMaximum current single pin limit (applies to all digital pins) –25 25 mA

VDDA Analog supply voltage VDD – 0.3 VDD + 0.3 V

1. Analog pins are defined as pins that do not have an associated general purpose I/O port function.

2 General

2.1 AC electrical characteristics

Unless otherwise specified, propagation delays are measured from the 50% to the 50%

point, and rise and fall times are measured at the 20% and 80% points, as shown in the

following figure.

80%

20%

50%

VIL

Input Signal

VIH

Fall Time

High

Low

Rise Time

Midpoint1

The midpoint is VIL + (VIH - VIL) / 2

Figure 2. Input signal measurement reference

2.2 Nonswitching electrical specifications

2.2.1 Voltage and current operating requirements

Table 1. Voltage and current operating requirements

Symbol Description Min. Max. Unit Notes

VDD Supply voltage 1.71 3.6 V

Table continues on the next page...

General

6Kinetis KV30F 64 KB/128 KB Flash, Rev. 4, 02/2016

Freescale Semiconductor, Inc.

Table 1. Voltage and current operating requirements (continued)

Symbol Description Min. Max. Unit Notes

VDDA Analog supply voltage 1.71 3.6 V

VDD – VDDA VDD-to-VDDA differential voltage –0.1 0.1 V

VSS – VSSA VSS-to-VSSA differential voltage –0.1 0.1 V

VIH Input high voltage

• 2.7 V ≤ VDD ≤ 3.6 V

• 1.7 V ≤ VDD ≤ 2.7 V

0.7 × VDD

0.75 × VDD

—

VIL Input low voltage

• 2.7 V ≤ VDD ≤ 3.6 V

• 1.7 V ≤ VDD ≤ 2.7 V

—

0.35 × VDD

0.3 × VDD

VHYS Input hysteresis 0.06 × VDD — V

IICIO Analog and I/O pin DC injection current — single pin

• VIN < VSS-0.3V (Negative current injection) -3 — mA

IICcont Contiguous pin DC injection current —regional limit,

includes sum of negative injection currents or sum of

positive injection currents of 16 contiguous pins

• Negative current injection -25 — mA

VODPU Open drain pullup voltage level VDD VDD V2

VRAM VDD voltage required to retain RAM 1.2 — V

1. All analog and I/O pins are internally clamped to VSS through ESD protection diodes. If VIN is less than VIO_MIN or

greater than VIO_MAX, a current limiting resistor is required. The negative DC injection current limiting resistor is

calculated as R=(VIO_MIN-VIN)/|IICIO|.

2. Open drain outputs must be pulled to VDD.

2.2.2 LVD and POR operating requirements

Table 2. VDD supply LVD and POR operating requirements

Symbol Description Min. Typ. Max. Unit Notes

VPOR Falling VDD POR detect voltage 0.8 1.1 1.5 V

VLVDH Falling low-voltage detect threshold — high

range (LVDV=01)

2.48 2.56 2.64 V

VLVW1H

VLVW2H

VLVW3H

VLVW4H

Low-voltage warning thresholds — high range

• Level 1 falling (LVWV=00)

• Level 2 falling (LVWV=01)

• Level 3 falling (LVWV=10)

• Level 4 falling (LVWV=11)

2.62

2.72

2.82

2.92

2.70

2.80

2.90

3.00

2.78

2.88

2.98

3.08

Table continues on the next page...

General

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Table 2. VDD supply LVD and POR operating requirements (continued)

Symbol Description Min. Typ. Max. Unit Notes

VHYSH Low-voltage inhibit reset/recover hysteresis —

high range

— 80 — mV

VLVDL Falling low-voltage detect threshold — low

range (LVDV=00)

1.54 1.60 1.66 V

VLVW1L

VLVW2L

VLVW3L

VLVW4L

Low-voltage warning thresholds — low range

• Level 1 falling (LVWV=00)

• Level 2 falling (LVWV=01)

• Level 3 falling (LVWV=10)

• Level 4 falling (LVWV=11)

1.74

1.84

1.94

2.04

1.80

1.90

2.00

2.10

1.86

1.96

2.06

2.16

VHYSL Low-voltage inhibit reset/recover hysteresis —

low range

— 60 — mV

VBG Bandgap voltage reference 0.97 1.00 1.03 V

tLPO Internal low power oscillator period — factory

trimmed

900 1000 1100 μs

1. Rising threshold is the sum of falling threshold and hysteresis voltage

2.2.3 Voltage and current operating behaviors

Table 3. Voltage and current operating behaviors

Symbol Description Min. Typ. Max. Unit Notes

VOH Output high voltage — Normal drive pad except

RESET_B

2.7 V ≤ VDD ≤ 3.6 V, IOH = -5 mA VDD – 0.5 — — V 1

1.71 V ≤ VDD ≤ 2.7 V, IOH = -2.5 mA VDD – 0.5 — — V

VOH Output high voltage — High drive pad except

RESET_B

2.7 V ≤ VDD ≤ 3.6 V, IOH = -20 mA VDD – 0.5 — — V 1

1.71 V ≤ VDD ≤ 2.7 V, IOH = -10 mA VDD – 0.5 — — V

IOHT Output high current total for all ports — — 100 mA

VOL Output low voltage — Normal drive pad except

RESET_B

2.7 V ≤ VDD ≤ 3.6 V, IOL = 5 mA — — 0.5 V 1

1.71 V ≤ VDD ≤ 2.7 V, IOL = 2.5 mA — — 0.5 V

VOL Output low voltage — High drive pad except

RESET_B

2.7 V ≤ VDD ≤ 3.6 V, IOL = 20 mA — — 0.5 V 1

1.71 V ≤ VDD ≤ 2.7 V, IOL = 10 mA — — 0.5 V

VOL Output low voltage — RESET_B

Table continues on the next page...

General

8Kinetis KV30F 64 KB/128 KB Flash, Rev. 4, 02/2016

Freescale Semiconductor, Inc.

Table 3. Voltage and current operating behaviors (continued)

Symbol Description Min. Typ. Max. Unit Notes

2.7 V ≤ VDD ≤ 3.6 V, IOL = 3 mA — — 0.5 V

1.71 V ≤ VDD ≤ 2.7 V, IOL = 1.5 mA — — 0.5 V

IOLT Output low current total for all ports — — 100 mA

IIN Input leakage current (per pin) for full

temperature range

All pins other than high drive port pins — 0.002 0.5 μA 1, 2

High drive port pins — 0.004 0.5 μA

IIN Input leakage current (total all pins) for full

temperature range

— — 1.0 μA 2

RPU Internal pullup resistors 20 — 50 kΩ 3

RPD Internal pulldown resistors 20 — 50 kΩ 4

1. PTB0, PTB1, PTC3, PTC4, PTD4, PTD5, PTD6, and PTD7 I/O have both high drive and normal drive capability

selected by the associated PTx_PCRn[DSE] control bit. All other GPIOs are normal drive only.

2. Measured at VDD=3.6V

3. Measured at VDD supply voltage = VDD min and Vinput = VSS

4. Measured at VDD supply voltage = VDD min and Vinput = VDD

2.2.4 Power mode transition operating behaviors

All specifications except tPOR, and VLLSx→RUN recovery times in the following

table assume this clock configuration:

• CPU and system clocks = 72 MHz

• Bus clock = 36 MHz

• Flash clock = 24 MHz

• MCG mode: FEI

Table 4. Power mode transition operating behaviors

Symbol Description Min. Typ. Max. Unit Notes

tPOR After a POR event, amount of time from the

point VDD reaches 1.71 V to execution of the

first instruction across the operating

temperature range of the chip.

— — 300 μs 1

• VLLS0 → RUN

—

135

μs

• VLLS1 → RUN

—

135

μs

• VLLS2 → RUN

—

μs

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General

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Table 4. Power mode transition operating behaviors (continued)

Symbol Description Min. Typ. Max. Unit Notes

• VLLS3 → RUN

—

μs

• VLPS → RUN

—

5.7

μs

• STOP → RUN

—

5.7

μs

1. Normal boot (FTFA_OPT[LPBOOT]=1)

2.2.5 Power consumption operating behaviors

The current parameters in the table below are derived from code executing a while(1)

loop from flash, unless otherwise noted.

The IDD typical values represent the statistical mean at 25°C, and the IDD maximum

values for RUN, WAIT, VLPR, and VLPW represent data collected at 125°C junction

temperature unless otherwise noted. The maximum values represent characterized

results equivalent to the mean plus three times the standard deviation (mean + 3 sigma).

Table 5. Power consumption operating behaviors

Symbol Description Min. Typ. Max. Unit Notes

IDDA Analog supply current — — See note mA 1

IDD_HSRUN High Speed Run mode current - all peripheral

clocks disabled, CoreMark benchmark code

executing from flash

@ 1.8V — 18.70 19.37 mA 2, 3, 4

@ 3.0V — 18.71 19.38 mA

IDD_HSRUN High Speed Run mode current - all peripheral

clocks disabled, code executing from flash

@ 1.8V — 18.13 18.80 mA 4

@ 3.0V — 18.19 18.86 mA

IDD_HSRUN High Speed Run mode current — all peripheral

clocks enabled, code executing from flash

@ 1.8V — 22.2 22.87 mA 5

@ 3.0V — 22.4 23.07 mA

IDD_RUN Run mode current in Compute operation —

CoreMark benchmark code executing from flash

@ 1.8V — 12.74 13.41 mA 2, 3, 6

@ 3.0V — 12.82 13.49 mA

Table continues on the next page...

General

10 Kinetis KV30F 64 KB/128 KB Flash, Rev. 4, 02/2016

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Table 5. Power consumption operating behaviors (continued)

Symbol Description Min. Typ. Max. Unit Notes

IDD_RUN Run mode current in Compute operation —

code executing from flash

@ 1.8V — 12.10 13.10 mA 6

@ 3.0V — 12.20 13.37 mA

IDD_RUN Run mode current — all peripheral clocks

disabled, code executing from flash

@ 1.8V — 12.8 13.47 mA 7

@ 3.0V — 12.9 13.57 mA

IDD_RUN Run mode current — all peripheral clocks

enabled, code executing from flash

@ 1.8V — 14.8 15.47 mA 8

@ 3.0V

• @ 25°C — 14.9 15.57 mA

• @ 70°C — 14.9 15.57 mA

• @ 85°C — 14.9 15.57 mA

• @ 105°C — 15.5 16.20 mA

IDD_RUN Run mode current — Compute operation, code

executing from flash

@ 1.8V — 12.1 12.77 mA 9

@ 3.0V

• @ 25°C — 12.2 12.87 mA

• @ 70°C — 12.2 12.87 mA

• @ 85°C — 12.2 12.87 mA

• @ 105°C — 12.7 13.37 mA

IDD_WAIT Wait mode high frequency current at 3.0 V — all

peripheral clocks disabled

— 5.5 6.17 mA 7

IDD_WAIT Wait mode reduced frequency current at 3.0 V

— all peripheral clocks disabled

— 3.5 4.17 mA 10

IDD_VLPR Very-low-power run mode current in Compute

operation — CoreMark benchmark code

executing from flash

@ 1.8V — 0.58 0.86 mA 2, 11, 3

@ 3.0V — 0.59 0.87 mA

IDD_VLPR Very-low-power run mode current in Compute

operation, code executing from flash

@ 1.8V — 0.47 0.75 mA 11

@ 3.0V — 0.47 0.75 mA

IDD_VLPR Very-low-power run mode current at 3.0 V — all

peripheral clocks disabled

— 0.62 0.90 mA 12

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Table 5. Power consumption operating behaviors (continued)

Symbol Description Min. Typ. Max. Unit Notes

IDD_VLPR Very-low-power run mode current at 3.0 V — all

peripheral clocks enabled

— 0.76 1.04 mA 13

IDD_VLPW Very-low-power wait mode current at 3.0 V — all

peripheral clocks disabled

— 0.28 0.56 mA 14

IDD_STOP Stop mode current at 3.0 V

@ -40°C to 25°C — 0.26 0.33 mA

@ 70°C — 0.30 0.47 mA

@ 85°C — 0.35 0.52 mA

@ 105°C — 0.43 0.60 mA

IDD_VLPS Very-low-power stop mode current at 3.0 V

@ -40°C to 25°C — 2.80 8.30 µA

@ 70°C — 13.30 29.90 µA

@ 85°C — 26.90 46.45 µA

@ 105°C — 56.80 67.05 µA

IDD_VLLS3 Very low-leakage stop mode 3 current at 3.0 V

@ -40°C to 25°C — 1.3 1.71 µA

@ 70°C — 3.8 5.35 µA

@ 85°C — 7.6 8.50 µA

@ 105°C — 15.1 19.05 µA

IDD_VLLS2 Very low-leakage stop mode 2 current at 3.0 V

@ -40°C to 25°C — 1.3 1.55 µA

@ 70°C — 3.1 4.05 µA

@ 85°C — 7.2 8.60 µA

@ 105°C — 12.0 14.10 µA

IDD_VLLS1 Very low-leakage stop mode 1 current at 3.0 V

@ -40°C to 25°C — 0.63 0.87 µA

@ 70°C — 1.70 2.35 µA

@ 85°C — 2.8 3.40 µA

@ 105°C — 7.6 8.80 µA

IDD_VLLS0 Very low-leakage stop mode 0 current at 3.0 V

with POR detect circuit enabled

@ -40°C to 25°C — 0.35 0.46 µA

@ 70°C — 1.38 1.94 µA

@ 85°C — 2.4 2.95 µA

@ 105°C — 7.3 8.45 µA

IDD_VLLS0 Very low-leakage stop mode 0 current at 3.0 V

with POR detect circuit disabled

@ -40°C to 25°C — 0.07 0.16 µA

@ 70°C — 1.05 1.78 µA

@ 85°C — 2.1 2.80 µA

Table continues on the next page...

General

12 Kinetis KV30F 64 KB/128 KB Flash, Rev. 4, 02/2016

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Table 5. Power consumption operating behaviors (continued)

Symbol Description Min. Typ. Max. Unit Notes

@ 105°C — 6.9 8.25 µA

1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device.

See each module's specification for its supply current.

2. Cache on and prefetch on, low compiler optimization

3. CoreMark benchmark compiled using IAR 7.2 with optimization level low

4. 100 MHz core and system clock, 50 MHz bus clock, and 25 MHz flash clock. MCG configured for FEE mode. All

peripheral clocks disabled.

5. 100 MHz core and system clock, 50 MHz bus clock, and 25 MHz flash clock. MCG configured for FEI mode. All

peripheral clocks enabled.

6. 72 MHz core and system clock, 36 MHz bus clock and 24 MHz flash clock. MCG configured for FEE mode. All

peripheral clocks disabled. Compute operation.

7. 72 MHz core and system clock, 36 MHz bus clock, and 24 MHz flash clock. MCG configured for FEI mode. All

peripheral clocks disabled.

8. 72 MHz core and system clock, 36 MHz bus clock, and 24 MHz flash clock. MCG configured for FEI mode. All

peripheral clocks enabled.

9. 72MHz core and system clock, 36MHz bus clock, and 24MHz flash clock. MCG configured for FEI mode. Compute

operation.

10. 25 MHz core and system clock, 25 MHz bus clock, and 25 MHz flash clock. MCG configured for FEI mode.

11. 4 MHz core, system, and bus clock, and 1 MHz flash clock. MCG configured for BLPE mode. Compute operation.

Code executing from flash.

12. 4 MHz core, system, and bus clock, and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral clocks

disabled. Code executing from flash.

13. 4 MHz core, system, and bus clock, and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral clocks

enabled, but peripherals are not in active operation. Code executing from flash.

14. 4 MHz core, system, and bus clock, and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral clocks

disabled.

Table 6. Low power mode peripheral adders—typical value

Symbol Description Temperature (°C) Unit

-40 25 50 70 85 105

IIREFSTEN4MHz 4 MHz internal reference clock (IRC)

adder. Measured by entering STOP or

VLPS mode with 4 MHz IRC enabled.

56 56 56 56 56 56 µA

IIREFSTEN32KHz 32 kHz internal reference clock (IRC)

adder. Measured by entering STOP

mode with the 32 kHz IRC enabled.

52 52 52 52 52 52 µA

IEREFSTEN4MHz External 4 MHz crystal clock adder.

Measured by entering STOP or VLPS

mode with the crystal enabled.

206 228 237 245 251 258 uA

IEREFSTEN32KHz External 32 kHz crystal clock adder by

means of the OSC0_CR[EREFSTEN

and EREFSTEN] bits. Measured by

entering all modes with the crystal

enabled.

VLLS1

VLLS3

LLS

440

490

540

560

570

580

680

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General

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Table 6. Low power mode peripheral adders—typical value (continued)

Symbol Description Temperature (°C) Unit

-40 25 50 70 85 105

VLPS

STOP

510

560

610

680

I48MIRC 48 Mhz internal reference clock 350 350 350 350 350 350 µA

ICMP CMP peripheral adder measured by

placing the device in VLLS1 mode with

CMP enabled using the 6-bit DAC and

a single external input for compare.

Includes 6-bit DAC power

consumption.

22 22 22 22 22 22 µA

IUART UART peripheral adder measured by

placing the device in STOP or VLPS

mode with selected clock source

waiting for RX data at 115200 baud

rate. Includes selected clock source

power consumption.

MCGIRCLK (4 MHz internal reference

clock)

>OSCERCLK (4 MHz external crystal)

214

237

246

254

260

268

µA

IBG Bandgap adder when BGEN bit is set

and device is placed in VLPx, LLS, or

VLLSx mode.

45 45 45 45 45 45 µA

IADC ADC peripheral adder combining the

measured values at VDD and VDDA by

placing the device in STOP or VLPS

mode. ADC is configured for low power

mode using the internal clock and

continuous conversions.

42 42 42 42 42 42 µA

2.2.5.1 Diagram: Typical IDD_RUN operating behavior

The following data was measured under these conditions:

• MCG in FBE mode for 50 MHz and lower frequencies. MCG in FEE mode at

frequencies between 50 MHz and 100MHz.

• No GPIOs toggled

• Code execution from flash with cache enabled

• For the ALLOFF curve, all peripheral clocks are disabled except FTFA

General

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Figure 3. Run mode supply current vs. core frequency

General

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Figure 4. VLPR mode supply current vs. core frequency

2.2.6 EMC radiated emissions operating behaviors

Table 7. EMC radiated emissions operating behaviors for 64 LQFP package

Parame

ter

Conditions Clocks Frequency range Level

(Typ.)

Unit Notes

VEME Device configuration, test

conditions and EM

testing per standard IEC

61967-2.

Supply voltage: VDD =

3.3 V

Temp = 25°C

FSYS = 100 MHz

FBUS = 50 MHz

External crystal = 10 MHz

150 kHz–50 MHz 11 dBuV 1, 2, 3

50 MHz–150 MHz 12

150 MHz–500 MHz 11

500 MHz–1000 MHz 8

IEC level N 4

1. Measurements were made per IEC 61967-2 while the device was running typical application code.

2. Measurements were performed on the 64LQFP device, MKV30F128VLH10.

3. The reported emission level is the value of the maximum measured emission, rounded up to the next whole number,

from among the measured orientations in each frequency range.

General

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4. IEC Level Maximums: N ≤ 12dBmV, M ≤ 18dBmV, L ≤ 24dBmV, K ≤ 30dBmV, I ≤ 36dBmV .

2.2.7 Designing with radiated emissions in mind

To find application notes that provide guidance on designing your system to minimize

interference from radiated emissions:

1. Go to www.freescale.com.

2. Perform a keyword search for “EMC design.”

2.2.8 Capacitance attributes

Table 8. Capacitance attributes

Symbol Description Min. Max. Unit

CIN_A Input capacitance: analog pins — 7 pF

CIN_D Input capacitance: digital pins — 7 pF

2.3 Switching specifications

2.3.1 Device clock specifications

Table 9. Device clock specifications

Symbol Description Min. Max. Unit Notes

High Speed run mode

fSYS System and core clock — 100 MHz

fBUS Bus clock — 50 MHz

Normal run mode (and High Speed run mode unless otherwise specified above)

fSYS System and core clock — 72 MHz

fBUS Bus clock — 50 MHz

fFLASH Flash clock — 25 MHz

fLPTMR LPTMR clock — 25 MHz

VLPR mode1

fSYS System and core clock — 4 MHz

fBUS Bus clock — 4 MHz

fFLASH Flash clock — 1 MHz

fERCLK External reference clock — 16 MHz

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Table 9. Device clock specifications (continued)

Symbol Description Min. Max. Unit Notes

fLPTMR_pin LPTMR clock — 25 MHz

fLPTMR_ERCLK LPTMR external reference clock — 16 MHz

1. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for

any other module.

2.3.2 General switching specifications

These general purpose specifications apply to all signals configured for GPIO, UART,

and timers.

Table 10. General switching specifications

Symbol Description Min. Max. Unit Notes

GPIO pin interrupt pulse width (digital glitch filter

disabled) — Synchronous path

1.5 — Bus clock

cycles

1, 2

External RESET and NMI pin interrupt pulse width —

Asynchronous path

100 — ns 3

GPIO pin interrupt pulse width (digital glitch filter

disabled, passive filter disabled) — Asynchronous

path

50 — ns 4

Port rise and fall time

• Slew disabled

• 1.71 ≤ VDD ≤ 2.7V

• 2.7 ≤ VDD ≤ 3.6V

• Slew enabled

• 1.71 ≤ VDD ≤ 2.7V

• 2.7 ≤ VDD ≤ 3.6V

—

1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may

or may not be recognized. In Stop, VLPS, LLS, and VLLSx modes, the synchronizer is bypassed so shorter pulses can

be recognized in that case.

2. The greater of synchronous and asynchronous timing must be met.

3. These pins have a passive filter enabled on the inputs. This is the shortest pulse width that is guaranteed to be

recognized.

4. These pins do not have a passive filter on the inputs. This is the shortest pulse width that is guaranteed to be

recognized.

5. 25 pF load

2.4 Thermal specifications

General

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2.4.1 Thermal operating requirements

Table 11. Thermal operating requirements

Symbol Description Min. Max. Unit Notes

TJDie junction temperature –40 125 °C

TAAmbient temperature –40 105 °C 1

1. Maximum TA can be exceeded only if the user ensures that TJ does not exceed maximum TJ. The simplest method to

determine TJ is: TJ = TA + RΘJA × chip power dissipation.

2.4.2 Thermal attributes

Board type Symbol Descriptio

n64 LQFP 48 LQFP 32 QFN Unit Notes

Single-layer

(1s)

RθJA Thermal

resistance,

junction to

ambient

(natural

convection)

66 79 97 °C/W 1

Four-layer

(2s2p)

RθJA Thermal

resistance,

junction to

ambient

(natural

convection)

48 55 33 °C/W 1

Single-layer

(1s)

RθJMA Thermal

resistance,

junction to

ambient (200

ft./min. air

speed)

54 67 81 °C/W 1

Four-layer

(2s2p)

RθJMA Thermal

resistance,

junction to

ambient (200

ft./min. air

speed)

41 49 28 °C/W 1

— RθJB Thermal

resistance,

junction to

board

30 33 13 °C/W 2

— RθJC Thermal

resistance,

junction to

case

17 23 2.0 °C/W 3

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Board type Symbol Descriptio

n64 LQFP 48 LQFP 32 QFN Unit Notes

—ΨJT Thermal

characterizati

parameter,

junction to

package top

outside

center

(natural

convection)

3 5 6 °C/W 4

1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental

Conditions—Natural Convection (Still Air), or EIA/JEDEC Standard JESD51-6, Integrated Circuit Thermal Test Method

Environmental Conditions—Forced Convection (Moving Air).

2. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental

Conditions—Junction-to-Board.

3. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate

temperature used for the case temperature. The value includes the thermal resistance of the interface material between

the top of the package and the cold plate.

4. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental

Conditions—Natural Convection (Still Air).

3 Peripheral operating requirements and behaviors

3.1 Core modules

3.1.1 SWD electricals

Table 12. SWD full voltage range electricals

Symbol Description Min. Max. Unit

Operating voltage 1.71 3.6 V

S1 SWD_CLK frequency of operation

• Serial wire debug

MHz

S2 SWD_CLK cycle period 1/S1 — ns

S3 SWD_CLK clock pulse width

• Serial wire debug

—

S4 SWD_CLK rise and fall times — 3 ns

S9 SWD_DIO input data setup time to SWD_CLK rise 8 — ns

S10 SWD_DIO input data hold time after SWD_CLK rise 1.4 — ns

S11 SWD_CLK high to SWD_DIO data valid — 25 ns

S12 SWD_CLK high to SWD_DIO high-Z 5 — ns

Peripheral operating requirements and behaviors

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S3 S3

S4 S4

SWD_CLK (input)

Figure 5. Serial wire clock input timing

S11

S12

S11

S9 S10

Input data valid

Output data valid

SWD_CLK

SWD_DIO

Figure 6. Serial wire data timing

3.1.2 JTAG electricals

Table 13. JTAG limited voltage range electricals

Symbol Description Min. Max. Unit

Operating voltage 2.7 3.6 V

J1 TCLK frequency of operation

• Boundary Scan

• JTAG and CJTAG

MHz

J2 TCLK cycle period 1/J1 — ns

J3 TCLK clock pulse width

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Peripheral operating requirements and behaviors

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