FINAL
Publicati on# 11407 Rev: GAmendment/0
Issue Date: May 1998
Am27C2048
2 Megabit (128 K x 16-Bit) CMOS EPR OM
DISTINCTIVE CHARACTERISTICS
Fast access time
Speed options as fast as 55 ns
Low power consumptio n
100 µA maximum CMOS standby current
JEDEC-approved pinout
Plug-in upgrade of 1 Mbit EPR OM
40-pin DIP/PDIP
44-pin PLCC
Single +5 V power supply
±10% power supply tolerance standard
100% Flashrite programming
Typical programming time of 16 seconds
Latch-up protected to 100 mA from –1 V to
VCC + 1 V
Versatile features for simple interfacing
Both CMOS and TTL input/output compatibility
Two line control functions
High noise immunity
GENERAL DESCRIPTION
The Am27C2048 is a 2 Mbit, ultraviolet erasable pro-
grammab le read-only memory. It is organized as 128 K
words, operates from a single +5 V supply, has a static
standby mode, and features fast single address loca-
tion programming. The Am27C2048 is ideal for use in
16-bit microprocessor syste ms. The device is a v ai lab le
in windowed ceramic DIP packages, and plastic one
time programmable (OTP) PDIP and PLCC packages.
Data can be typically accessed in less than 55 ns, al-
lowing high-performance microprocessors to operate
without any WAIT states. The device offers separate
Output Enable (OE#) and Chip Enable (CE#) controls,
thus eliminating b us contention in a multiple b us micro-
proc esso r sys te m.
AMD’s CMOS process technology provides high
speed, low power, and high noise immunity. Typical
power consumption is only 125 mW in active mode,
and 100 µW in standby mode.
All signals are TTL levels, including programming sig-
nals. Bit locations may be programmed singly, in
blocks, or at random. The device supports AMD’s
Flashrite programming algorithm (100 µs pulses), re-
sulting in a typical programming time of 16 seconds.
BLOCK DIAGRAM
11407G-1
A0–A16
Address
Inputs
PGM#
CE#
OE#
VCC
VSS
VPP
Data Outputs
DQ0–DQ15
Output
Buffers
Y
Gating
2,097,152
Bit Cell
Matrix
X
Decoder
Y
Decoder
Output Enable
Chip Enable
and
Prog Logic
2 Am27C2048
PRODUCT SELECTOR GUIDE
CONNECTION DIAGRAMS
Top View
DIP PLCC
Notes:
1. JEDEC nomenclature is in parenthesis.
2. Don’t use (DU) for PLCC.
PIN DESIGNATIONS
A0–A16 = Address Inputs
CE# (E#) = Chip Enable Input
DQ0–DQ15 = Data Input/O utputs
OE# (G#) = Output Enable Input
PGM# (P#) = Program Enable Input
VCC =V
CC Supply Voltage
VPP = Program Voltage Input
VSS = Ground
LOGIC SYMBOL
Family Part Number Am27C2048
Speed Options VCC = 5.0 V ± 5% -55 -255
VCC = 5.0 V ± 10% -55 -70 -90 -120 -150 -200
Max Access Time (ns) 55 70 90 120 150 200 250
CE# (E#) Access (ns) 55 70 90 120 150 200 250
OE# (G#) Access (ns) 40 40 40 50 65 75 75
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
V
CC
PGM# (P#)
A16
A15
A14
A13
A12
A11
A10
A9
V
SS
A8
A7
A6
A5
A4
A3
A2
A1
A0
V
PP
CE# (E#)
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
V
SS
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
OE# (G#)
11407G-2
1 444342543264140
7
8
9
10
11
12
13
14
15
16
17
A13
A12
A11
A10
A9
V
SS
NC
A8
A7
A6
A5
DQ13
DQ14
DQ15
CE (E)
V
PP
DU (Note 2)
V
CC
PGM# (P#)
A16
A15
A14
39
38
37
36
35
34
33
32
31
30
29
DQ12
DQ11
DQ10
DQ9
DQ8
V
SS
NC
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
OE# (G#)
DU (Note 2)
A0
A1
A2
A3
A4
23 24 25 2619 20 21 2218 27 28
11407G-3
17
16
DQ0–DQ15
A0–A16
CE# (E#)
PMG (P#)
OE# (G#)
11407G-4
Am27C2048 3
ORDERING INFORMATION
UV EPROM Products
AMD standard products are a vailable in se veral packages and operating ranges. The order number (V alid Combination) is formed
by a combination of the following:
Valid Combinations
Valid Combinations list configurations planned to be sup-
ported in v olume for this device. Consult the local AMD sales
office to confirm av ailability of specific valid combinations and
to check on newly released combinations.
DEVICE NUMBER/DESCRIPTION
Am27C2048
2 Megabit (128 K x 16-Bit) CMOS UV EPROM
AM27C2048 -55 D C
OPTIONAL PROCESSING
Blank = Standard Processing
B = Burn-In
VOLTAGE TOLERANCE
5=V
CC ± 5%, 55 ns only
See Product Selector Guide and Valid Combinations
TEMPERATURE RANGE
C = Commerc ial (0°C to +70°C)
I=Industrial (–40°C to +85°C)
E = Extended (–55°C to +125°C)
PACKAGE TYPE
D = 40-Pin Ceramic DIP (CDV040)
SPEED OPTION
See Product Selector Guide and
Valid Combinations
B
5
Valid Combinations
AM27C2048-55
VCC = 5.0 V ± 5% DC5, DC5B, DI5, DI5B
AM27C2048-55
VCC = 5.0 V ± 10% DC, DCB, DI, DIB
AM27C2048-70
AM27C2048-90
AM27C2048-120
DC, DCB, DE, DEB, DI, DIBAM27C2048-150
AM27C2048-200
AM27C2048-255
VCC = 5.0 V ± 5% DC, DCB, DI, DIB
4 Am27C2048
ORDERING INFORMATION
OTP EPROM Products
AMD standard products are a vailable in se veral packages and operating ranges. The order number (V alid Combination) is formed
by a combination of the following:
Valid Combinations
Valid Combinations list configurations planned to be sup-
ported in v olume for this device. Consult the local AMD sales
office to confirm av ailability of specific valid combinations and
to check on newly released combinations.
DEVICE NUM BE R/ DES CR IP TIO N
Am27C2048
2 Megabit (128 K x 16-Bit) CMOS OTP EPROM
AM27C2048 -55 J C
OPTION AL PROCES SI NG
Blank = Standard Processing
VOLTAGE TOLERANCE
5=V
CC ± 5%, -55 ns only
See Product Selector Guide and
Valid Combin ati ons
TEMPER ATUR E RAN GE
C = Commercial (0°C to +70°C)
I=Industrial (–40°C to +85°C)
PACK AGE TYP E
P = 40-Pin Plastic DIP (PD 040)
J = 44-Pin Square Plastic Leaded Chip Carrier (PL 044)
SPEED OPTION
See Product Selector Guide and
Valid Combin ati ons
5
Valid Combinations
AM27C2048-55
VCC = 5.0 V ± 5% PC5, PI5, JC5, JI5
AM27C2048-55
VCC = 5.0 V ± 10%
PC, PI, JC, JI
AM27C2048-70
AM27C2048-90
AM27C2048-120
AM27C2048-150
AM27C2048-200
AM27C2048-255
VCC = 5.0 V ± 5%
Am27C2048 5
FUNCTIONAL DESCRIPTION
Device Erasure
In order to clear all locations of their programmed con-
tents , the de vice must be e xposed to an ultra violet light
source. A dosage of 15 W seconds/cm2 is required to
completely erase the device. This dosage can be ob-
tained by exposure to an ultraviolet lamp—wavelength
of 2537 Å—with intensity of 12,000 µW/cm2 for 15 to 20
minutes. The device should be directly under and about
one inch from the source, and all filters should be re-
moved from the UV light source prior to erasure.
Note that all UV erasable devices will erase with light
sources hav ing wav elengths shorter than 4000 Å, such
as fluorescent light and sunlight. Although the erasure
process happens over a much longer time period, ex-
posure to any light source should be prevented for
maximum system reliability. Simply cover the package
window with an opaque label or substance.
Device Programming
Upon delivery, or after each erasure, the device has
all of it s bits in the “ONE”, or HIGH stat e. “ZE ROs” are
loaded into the device through the programming pro-
cedure.
The device enters the programming mode when 12.75
V ± 0.25 V is applied to the VPP pin, and CE# and
PGM# are at VIL.
For programming, the data to be programmed is ap-
plied 16 bits in parallel to the data pins.
The flowchart in the Programming section (Section 5,
Figure 5-1) shows AMD’s Flashrite algorithm. The
Flashrite a lgor ithm reduc es programming time by using
a 100 µs programming pulse and by giving each address
only as many pulses to reliably program the data. After
each pulse is applied to a giv en address, the data in that
address is verified. If the data does not verify, additional
pulses are given until it verifies or the maximum pulses
allowed is reached. This process is repeated w hile se-
quencing through eac h address of the device. This part
of the algorithm is done at VCC = 6.25 V to assure that
each EPROM bit is programmed to a sufficiently high
threshold voltage. After the final address is completed,
the entire EPROM memory is verified at VCC = VPP =
5.25 V.
Please ref er to Section 5 f or additional programming in-
formation and specifications.
Program Inhibit
Programming different data to multiple devices in par-
allel is easily accomplished. Except for CE#, all like in-
puts of the devices may be common. A TTL low-level
program pulse applied to one device’s CE# input with
VPP = 12.75 V ± 0.25 V and PGM# LOW will program
that particular device. A high-level CE# input inhibits
the other devices from being programmed.
Program Verify
A v erificat ion should be performed on the prog r ammed
bits to determine that the y were correct ly programmed.
The verify should be perfor med with OE# and CE#, at
VIL, PGM# at VIH, an d VPP between 12.5 V and 13.0 V.
Autoselect Mode
The autoselect mode provides manufacturer and de-
vice identification through identifier codes on DQ0
DQ7. This mode is primarily intended for programming
equipment to automatically match a device to be pro-
grammed with its corresponding programming algo-
rithm. This mode is functional in the 25°C ± 5°C
ambient temperature range that is required when pro-
gra mming the device.
To activate this mode, the programming equipment
must force VH on address line A9. Two identifier bytes
may then be sequenced from the de vice outputs by tog-
gling address line A0 from VIL to VIH (that is, changing
the address from 00h to 01h). All other address lines
must be held at VIL during the autoselect mode.
Byte 0 (A0 = VIL) represents the manufacturer code,
and Byte 1 (A0 = VIH), the device identifier code. Both
codes have odd parity, with DQ7 as the parity bit.
Read Mode
To obtain data at the de vice outputs, Chip Enab le (CE#)
and Output Enab le (OE#) must be driv en low . CE# con-
trols the po wer to the de vice and is typically used t o se-
lect the device. OE# ena b les the de v ice t o out put data,
independent of device selection. Addresses must be
stable for at least tACC–tOE. Refer to the Switching
Waveforms section for the timing diag ram.
Standby Mode
The de vice enters the CMOS standby mode when CE#
is at VCC ± 0.3 V. Maximum VCC current is reduced to
100 µA. The device enters the TTL-standby mode
when CE# is at VIH. Maximum VCC current is reduced
to 1.0 mA. When in either standby mode, the device
places its outputs in a high-impedance state, indepen-
dent of the OE# input.
Output OR-Tieing
To accommodate multiple memory connections, a
two-line control function provides:
low memory power dissipation, and
assurance that output b us contention will not occur.
CE# should be decoded and used as the primary de-
vice-selecting funct ion, whi le OE# be made a common
connection to all devices in the array and connected to
6 Am27C2048
the READ line from the system control bus. This as-
sures that all deselected memor y devices are in their
low-power standby mode and that the output pins are
only activ e when data is desired fr om a particular mem-
ory device.
System Applications
During the switch between active and standby condi-
tions, transient current peaks are produced on the ris-
ing and f alling edges of Chip Enab le . The magnitude of
these transient current peaks is dependent on the out-
put capacitance loading of t he device. At a minim um, a
0.1 µF ceramic capacitor (high frequency, low inherent
inductance) should be used on each device between
VCC and VSS to minim ize transient effects. In addition,
to overcome the voltage drop caused by the inductive
effects of the printed circuit board traces on EPR OM ar-
rays, a 4.7 µF bulk electrolytic capacitor should be used
between V CC and VSS for each eight de vices. The loca-
tion of the capacitor should be close to where the
power supply is connected to the array.
MODE SELECT TABLE
Notes:
1. VH = 12.0 V
±
0.5 V.
2. X = Either VIH or VIL.
3. A1–A8 and A10–16 = VIL.
4. See DC Programming Characteristics for VPP voltage during programmin g.
Mode CE# OE# PGM# A0 A9 VPP Outputs
Read VIL VIL XXXXD
OUT
Output Disable VIL VIH X X X X High Z
Standby (TTL) VIH X X X X X High Z
Standby (CMOS) VCC ± 0.3 V X X X X X High Z
Program VIL XV
IL XXV
PP DIN
Program Verify VIL VIL VIH XXV
PP DOUT
Program Inhibit VIH XXXXV
PP High Z
Autoselect
(Note 3) Manufacturer Code VIL VIL XV
IL VHX01h
Device Code VIL VIL XV
IH VHX98h
Am27C2048 7
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
OTP Products . . . . . . . . . . . . . . . . . . –65°C to +125°C
All Other Products . . . . . . . . . . . . . . –65°C to +150°C
Ambient Temperature
with Power Applied. . . . . . . . . . . . . . –55°C to +125°C
Voltage with Respect to VSS
All pins except A9, VPP
, VCC . . –0.6 V to VCC + 0.6 V
A9 and VPP (Note 2) . . . . . . . . . . . . .–0.6 V to 13.5 V
VCC (Note 1). . . . . . . . . . . . . . . . . . . . .–0.6 V to 7.0 V
Notes:
1. Minimum DC vo ltage on inpu t or I/O pins – 0.5 V. D uring
voltage transitions, the input may ov ershoot VSS to –2.0 V
for periods of u p to 20 ns. Max imum DC voltage o n inp ut
and I/O pins is V
CC
+ 5 V. During voltage transitions, input
and I/O pins may ov ershoot to V
CC
+ 2.0 V for periods up
to 20 ns.
2. Minimum DC input voltage on A9 is –0.5 V. During voltage
transitions, A9 and VPP may over shoot V SS
to –2.0 V for
periods of up to 20 ns. A9 and VPP must not exceed+13.5
V at any time.
Stresse s above thos e listed unde r “Absolute Ma ximum Rat-
ings” may caus e per ma nent d amage to the device. This is a
stress ratin g on ly; fun ctio nal ope ration of t he d evice at the se
or any other conditions above those indicated in the opera-
tional sections of this specification is not implied. Exposure of
the device to absolute maximum ratings for extended periods
may affect device reliability.
OPERATING RANGES
Commercial (C) Devices
Ambient Temperature (TA) . . . . . . . . . . .0°C to +70°C
Industrial (I) De vices
Ambient Temperature (TA) . . . . . . . . .–40°C to +85°C
Extended (E) Devices
Ambient Temperature (TA) . . . . . . . . –55°C to +125°C
Supply Read Vol tages
VCC for ± 5% devices . . . . . . . . . . +4.75 V to +5.25 V
VCC for ± 10% devices . . . . . . . . . +4.50 V to +5.50 V
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
8 Am27C2048
DC CHARACTERISTICS OVER OPERATING RANGE
(unless otherwise specified)
Caution: The device must not be removed from (or inserted into) a socket when VCC or VPP is applied.
Notes:
1. VCC must be applied simultaneously or before VPP
, and removed simultaneously or after VPP
..
2. ICC1 is tested with OE# = VIH to simulate open outputs.
3. Minimum DC Input Voltage is –0.5 V. During transitions, the inputs may overshoot to –2.0 V for periods less than 20 ns.
Maximum DC Voltage on output pins is VCC + 0.5 V, which may overshoot to VCC + 2.0 V for periods less than 20 ns.
Figure 1. Typical Supply Current vs. Frequency
VCC = 5.5 V, T = 25°CFigure 2. Typical Supply Current vs. Temperature
VCC = 5.5 V, f = 5 MHz
Parameter
Symbol Parameter Description Test Conditions Min Max Unit
VOH Output HIGH Voltage IOH = –400 µA 2.4 V
VOL Output LOW Voltage IOL = 2.1 mA 0.45 V
VIH Input HIGH Voltage 2.0 VCC + 0.5 V
VIL Input LOW Voltage –0.5 +0.8 V
ILI Input Load Current VIN = 0 V to VCC C/I Devices 1.0 µA
E Devices 5.0
ILO Output Leakage Current VOUT = 0 V to VCC 5.0 µA
ICC1 VCC Active Current (Note 2) CE# = VIL, f = 5 MHz,
IOUT = 0 mA C/I Devices 50 mA
E Devices 60
ICC2 VCC TTL Standby Current CE# = VIH 1.0 mA
ICC3 VCC CMOS Standby Current CE# = VCC ± 0.3 V 100 µA
IPP1 VPP Supply Current (Read) CE# = OE# = VIL, VPP = VCC 100 µA
11407G-5
12345678910
35
30
25
20
15
Frequency in MHz
Supply Current
in mA
11407G-6
–75 –50 55 0 25 50 75 100 125 150
35
30
25
20
15
Temperature in °C
Supply Current
in mA
Am27C2048 9
TEST CONDITIONS
Table 1. Test Specifications
SWITCHING TEST WAVEFORM
KEY TO SWITCHING WAVEFORMS
2.7 k
CL6.2 k
5.0 V
Device
Under
Test
11407G-7
Figure 3. Test Setup
Note:
Diodes are IN3064 or equivalents.
Test Condition -55 All
others Unit
Output Load 1 TTL gate
Output Load Capacitance, CL
(including jig cap aci tan ce) 30 100 pF
Input Rise and Fall Times 20 ns
Input Pulse Levels 0.0–3.0 0.45–2.4 V
Input timing measurement
reference levels 1.5 0.8, 2.0 V
Output timing measurement
reference levels 1.5 0.8, 2.0 V
2.4 V
0.45 V Input Output
Test Points
2.0 V 2.0 V
0.8 V
0.8 V
11407G-8
3 V
0 V Input Output
1.5 V 1.5 V
Test Points
Note: For CL = 100 pF.Note: For CL = 30 pF.
KS000010-PAL
WAVEFORM INPUTS OUTPUTS
Steady
Changing from H to L
Changi ng from L to H
Don’t Care, Any Change Permitted Changing, State Unknown
Does Not Apply Center Line is High Impedance State (High Z)
10 Am27C2048
AC CHARACTERISTICS
Caution: Do not remove the device from (or insert it into) a socket or board that has VPP or VCC applied.
Notes:
1. VCC must be applied simultaneously or before VPP
, and removed simultaneously or after VPP
.
2. This parameter is sampled and not 100% tested.
3. Switching characteristics are over operating range, unless otherwise specified.
4. See Figure 3 and Table 1 for test specifications.
SWITCHING WAVEFORMS
Notes:
1. OE# may be delayed up to tACC – tOE after the falling edge of the addresses without impact on tACC.
2. tDF is specified from OE# or CE#, whichever occurs first.
PACKAGE CAPACITANCE
Notes:
1. This parameter is only sampled and not 100% tested.
2. TA = +25
°
C, f = 1 MHz.
Parameter Symbols
Description Test Setup
Am27C2048
UnitJEDEC Standard -55 -70 -90 -120 -150 -200 -255
tAVQV tACC Address to Output Delay CE#,
OE# = VIL Max 55 70 90 120 150 200 250 ns
tELQV tCE Chip Enable to Output Delay OE# = VIL Max 55 70 90 120 150 200 250 ns
tGLQV tOE Output Enable to Output Delay CE# = VIL Max40404050657575ns
t
EHQZ
tGHQZ
tDF
(Note 2)
Chip Enable High or Output
Enable High to Output High Z,
Whichever Occurs First Max25252530304060ns
t
AXQX tOH
Output Hold Time from
Addresses, CE# or OE#,
Whichever Occurs First Min0000000ns
Addresses
CE#
OE#
Output 11407G-9
Addresses Valid
High Z High Z
tCE
Valid Output
2.4
0.45
2.0
0.8 2.0
0.8
tACC
(Note 1)
tOE tDF (Note 2)
tOH
Parameter
Symbol Parameter
Description Test Conditions
CDV040 PD 040 PL 044
UnitTyp Max Typ Max Typ Max
CIN Input Capacitance VIN = 0 10 12 10 12 7 10 pF
COUT Output Capacitance VOUT = 0 121512151214pF
Am27C2048 11
PH YS ICAL DIMENSIONS *
CDV040—40-Pin Ceramic Dual In-Line Package, UV Lens (measured in inches)
* For reference only. BSC is an ANSI standard for Basic Space Centering.
PD 040—40-Pin Plastic Dual In-Line Package (measured in inches)
TOP VIEW
SIDE VIEW END VIEW
INDEX AND
TERMINAL NO. 1
I.D. AREA
.565
.605
2.035
2.080
.005 MIN .045
.065 .014
.026 .100 BSC
.015
.060
.160
.220
.125
.200
BASE PLANE
SEATING PLANE
.300 BSC .600
BSC .008
.018
94°
105°
.700
MAX
16-000038H-3
CDV040
DF11
3-30-95 ae
DATUM D
CENTER PLANE
DATUM D
CENTER PLANE
1
UV Lens
Pin 1 I.D.
2.040
2.080
.530
.580
.005 MIN
.045
.065
.090
.110
.140
.225
.120
.160 .014
.022
SEATING PLANE
.015
.060
16-038-SC_AF
PD 040
DG76
2-28-95 ae
40 21
20 .630
.700
0°
10°
.600
.625
.008
.015
12 Am27C2048
PH YS ICAL DIMENSIONS
PL 044—44-Pin Plastic Leaded Chip Carrier (measured in inches)
REVISION SUMMARY FOR AM27C2048
Revision G
Global
Changed for m atting to match current data sheets.
Connection Diagrams
Corrected designation for pin 38 on PDIP connection
diagram to A16.
Trademarks
Copyright © 1998 Advanced Micro Devices, Inc. All rights rese rved.
AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc.
Flashrite is a trademark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
TOP VIEW
SEATING PLANE
.685
.695 .650
.656
Pin 1 I.D.
.685
.695
.650
.656
.026
.032 .050 REF
.042
.056
.062
.083
.013
.021
.590
.630
.500
REF
.009
.015
.165
.180
.090
.120 16-038-SQ
PL 044
EC80
11.3.97 lv
SIDE VIEW