ASAHI KASEI [AKD5702-A]
<KM086501> 2007 / 04
- 1 -
GENERAL DESCRIPTION
AKD5702-A is an evaluation board for the portable digital audio 16bit A/D converter with MIC-AMP,
AK5702. AKD5702-A also has the digital audio interface and can achieve the interface with digital audio
systems via opt-connector.
Ordering guide
AKD5702-A --- AK5702 Evaluation Board
(Cable for connecting with printer port of IBM-AT compatible PC and control software
are packed with this. This control software does not support Windows NT.)
FUNCTION
• DIT with optical output
• BNC connector for an external clock input
• 10pin Header for serial control interface
AK4114
(DIT)
10pin Header
Control Data
10pin Header
DGND
Opt Out
AK5702
VDAVDD
DSP 2
DVDD AGND
MIC3/4/5
5V Regulator
3.0V
10pin Header
TDM
EXT_BCLK
LIN3/4/5
EXT_LRCK CLOCK
GEN
RIN3/4/5
MIC1/2/5
LIN1/2/5
RIN1/2/5
EXT_MCLK
Opt In
10pin Header
DSP 1
Figure 1. AKD5702-A Block Diagram
* Circuit diagram and PCB layout are attached at the end of this manual.
AK5702 Evaluation Board Rev.1
A
KD5702-
A
ASAHI KASEI [AKD5702-A]
<KM086501> 2007 / 04
- 2 -
Evaluation Board Manual
Operation sequence
1) Set up th e power supply lines.
1-1) When AVDD, D VDD and VD are supplied from the regulato r. ( De fault )
[REG] (Red) = 5V
[AVDD] (Orange) = open (3.0V, supply from regulator, for AVDD of AK5702)
[DVDD] (Orange) = open (3.0V, supply from regulator, for DVDD of AK5702)
[VD] (Orange) = 2.7 ∼ 3.6V (typ. 3.0V, for logic of digital part)
[AGND] (Black) = 0V (for analog ground)
[DGND] (Black) = 0V (for digital ground)
1-2) When AVDD, D VDD and VD are not suppl ied from the regulat or.
[REG] (Red) = open
[AVDD] (Orange) = 2.4 ∼ 3.6V (typ. 3.0V, for AVDD of AK5702)
[DVDD] (Orange) = 1.6 ∼ 3.6V (typ. 3.0V, fo r DV DD of AK5702)
[VD] (Orange) = 2.7 ∼ 3.6V (typ.3.0V, for logic of digital part)
[AGND] (Black) = 0V (for analog ground)
[DGND] (Black) = 0V (for digital ground)
Each supply line should be distributed from the power supply unit.
2) Set up the evaluation mode, jumper pins and DIP switches. (See the followings.)
3) Power on.
T he AK5702 and AK4114 should be reset once by bringing SW1, 2 “L” upon power-up.
Ev al u ation mode
In case of AK5702 evaluation using AK41 14, s ame aud io i n te rf ac e f ormat should b e set for both AK5702 and
AK4114. About AK5702’s audio interface format, refer to datasheet of AK5702. About AK4 114’s audio
interface format, refer to Table 2 in this manual.
Applicable Evaluation Mode
(1) PLL Master Mode (Default)
(2) PLL Slave Mode 1 (PLL Reference CLOC K: MCKI pin)
(3) PLL Slave Mode 2 (PLL Refere nce CLOC K: BCL K or LRCK pin)
(4) EXT Slave Mode
(5) EXT Master Mo de
ASAHI KASEI [AKD5702-A]
<KM086501> 2007 / 04
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(1) PLL Master Mode (Default)
* Connect PORT 4 ( DSP1) with DSP.
Figure below shows PORT4 pin assign.
PORT4
GND
GND
NC
NC
SDTOBVD
SDTO A
LRCK
BCLK
MCKO
a) Set up jumper pins of MCKI c lock
When using X’tal as MCKI clock, X’ tal of 11.2896MHz, 12MHz, 12.288MHz, 13MHz, 24MHz or 27MHz can
be set to X1. X’tal of 11.2896MHz (Default) is set on the AKD5702 -A.
When an external clock (11.2896MHz, 12MHz, 12.288MHz, 13MHz, 24MHz or 27MHz) is supplied through a
BNC connector J1 (EXT_MCKI), select EXT_MCLK on JP16 (XT I) and select EXT on J P 7 (M CLK_ SEL).
JP12 (EXT) and R19 should be properly selected in order to match th e output impedance of th e clock generator.
JP7
MCKI_SEL JP5
TDMMCLK_SEL JP8
MKFS
DIT EXT
256fs
512fs
JP1 6
XTI
EXT_MCLK
MCKO
1024fs
384/768fs
MCKO
EXT_MCLK
384fs-768
JP32
MCLK_SEL
MCKO EXT_MCLK
* The setting of JP8(MKFS) is invalid in thi s mode,but if JP8(MKFS) is open, the input of the buffer will be unstable. So
JP8( MKFS) should set up any.
b) Set up jumper pins of BCLK clock
Output frequency (32fs/64fs) of BCLK should be set by “BCKO1-0 bit” in the AK5702.
There is no necessity for set up JP9(BCLKFS).
JP10
BCLK_SEL
JP9
BCLKFS
64fs-384
32fs-384
64fs
32fs
DIT
BCLKFS
BNC_BCLK
JP2 8
M/S
M S
c) Set up jumper pins of LRCK clock
JP13
LRCK_SEL
JP11
LRC KFS
2fs-384
1fs-384
2fs
1fs
DIT
LRCKFS
BNC_LRCK
ASAHI KASEI [AKD5702-A]
<KM086501> 2007 / 04
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d) Set up jumper pins of SDTO
JP29
SDTOB
JP30
SDTO_SEL
BA
(2) PLL Slave Mode 1 (PLL Reference CLOC K: MCKI pin)
* Connect PORT 4 ( DSP1) with DSP.
Figure below shows PORT4 pin assign.
PORT4
GND
GND
NC
NC
SDTOBVD
SDTOA
LRCK
BCLK
MCKI
a) Set up jumper pins of MCKI c lock
X’tal of 11.2896MHz (Default) is set on the AKD5702-A. In this case, the AK 57 02 corresponds to P LL reference
clock of 11.2896MHz. In this evaluation mode, the output clock from MCKO pin of the AK 57 02 is supplied to a
divider (U3: 74VHC4040), EXT_BCLK and EXT_LRCK clocks are generated by the divider. Then “ MCKO bit” i n
the AK5702 should be set to “1”.
When an external clock is supplied through a BNC connector J1 (EX T_MCKI), select EXT_MCLK on JP16 (XTI)
and select EXT on JP7 (MCKI_SEL). JP12 (EXT) and R19 should be properly selecte d in order too match the output
impedance of the clock generator.
JP7
MCKI_SEL JP5
TDMMCLK_SEL JP8
MKFS
DIT EXT
256fs
512fs
JP1 6
XTI
EXT_MCLK
MCKO
1024fs
384/768fs
MCKO
EXT_MCLK
384fs-768
JP32
MCLK_SEL
MCKO EXT_MCLK
b) Set up jumper pins of BCLK clock
JP10
BCLK_SEL
JP9
BCLKFS
64fs-384
32fs-384
64fs
32fs
DIT
BCLKFS
BNC_BCLK
JP2 8
M/S
M S
ASAHI KASEI [AKD5702-A]
<KM086501> 2007 / 04
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c) Set up jumper pins of LRCK clock
JP13
LRCK_SEL
JP11
LRC KFS
2fs-384
1fs-384
2fs
1fs
DIT
LRCKFS
BNC_LRCK
d) Set up jumper pins of SDTO
JP29
SDTOB
JP30
SDTO_SEL
BA
(2-a) In the case of using AK4114.
* In this mo de, MCLK of AK5702 should be supplied from J1 (EXT_MCKI), and X1 should be open.
This mode is BCLK=64fs, LRCK=1fs only.
Set up jumper pins of M CKI clock
JP7
MCKI_SEL JP5
TDMMCLK_SEL JP8
MKFS
DIT EXT
256fs
512fs
JP1 6
XTI
EXT_MCLK
MCKO
1024fs
384/768fs
MCKO
EXT_MCLK
384fs-768
JP32
MCLK_SEL
MCKO EXT_MCLK
* The setting of JP8(MKFS) is invalid in this mode,but if JP8(MKFS) is open, the input of the buffer will be unstable. So
JP8( MKFS) should set up any.
Set up jum per pins of BCLK clock
JP10
BCLK_SEL
JP9
BCLKFS
64fs-384
32fs-384
64fs
32fs
DIT
BCLKFS
BNC_BCLK
JP2 8
M/S
M S
Set up jumper pins of LRCK clock
JP13
LRCK_SEL
JP11
LRC KFS
2fs-384
1fs-384
2fs
1fs
DIT
LRCKFS
BNC_LRCK
ASAHI KASEI [AKD5702-A]
<KM086501> 2007 / 04
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Set up jumper pins of SDTO
JP29
SDTOB
JP30
SDTO_SEL
BA
(3) PLL Slave Mode 2 (PLL Refere nce CLOC K: BC LK or LRCK pin)
* Connect PORT 4 ( DSP1) with DSP.
Figure below shows PORT4 pin assign.
PORT4
GND
GND
NC
NC
SDTOBVD
SDTOA
LRCK
BCLK
MCKI
a) Set up jumper pins of MCKI clock
JP7
MCKI_SEL JP5
TDMMCLK_SEL JP8
MKFS
DIT EXT
256fs
512fs
JP1 6
XTI
EXT_MCLK MCKO
1024fs
384/768fs
MCKO
EXT_MCLK
384fs-768
JP32
MCLK_SEL
MCKO EXT_MCLK
b) Set up jumper pins of BCLK clock
When an external clock is supplied through a BNC connector J2 (EXT/BCLK), J3 (EXT/LRCK), JP14 (EXT1)
and R20, JP15 (EXT2) and R21 should be properly selected in order to mu ch the output impedance of the clock
generator.
JP10
BCLK_SEL
JP9
BCLKFS
64fs-384
32fs-384
64fs
32fs
DIT
BCLKFS
BNC_BCLK
JP2 8
M/S
M S
ASAHI KASEI [AKD5702-A]
<KM086501> 2007 / 04
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c) Set up jumper pins of LRCK clock
JP13
LRCK_SEL
JP11
LRC KFS
2fs-384
1fs-384
2fs
1fs
DIT
LRCKFS
BNC_LRCK
d) Set up jumper pins of SDTO
JP29
SDTOB
JP30
SDTO_SEL
BA
(4) EXT Slave Mode
* Connect PORT 4 ( DSP1) with DSP.
Figure below shows PORT4 pin assign. In this mode, MCKI, BCLK and LRCK should be supplied from PORT4.
PORT4
GND
GND
NC
NC
SDTOBVD
SDTOA
LRCK
BCLK
MCKI
a) Set up jumper pins of MCKI clock
JP7
MCKI_SEL JP5
TDMMCLK_SEL JP8
MKFS
DIT EXT
256fs
512fs
JP1 6
XTI
EXT_MCLK
MCKO
1024fs
384/768fs
MCKO
EXT_MCLK
384fs-768
JP32
MCLK_SEL
MCKO EXT_MCLK
b) Set up jumper pins of BCLK clock
JP10
BCLK_SEL
JP9
BCLKFS
64fs-384
32fs-384
64fs
32fs
DIT
BCLKFS
BNC_BCLK
JP2 8
M/S
M S
ASAHI KASEI [AKD5702-A]
<KM086501> 2007 / 04
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c) Set up jumper pins of LRCK clock
JP13
LRCK_SEL
JP11
LRC KFS
2fs-384
1fs-384
2fs
1fs
DIT
LRCKFS
BNC_LRCK
d) Set up jumper pins of SDTO
JP29
SDTOB
JP30
SDTO_SEL
BA
(4-a) In the case of using AK4114.
*This mode is BCLK=64fs, LRCK=1fs only. The setting of JP16(XTI) is open, the clock of AK4114 use X’tal of X1.
The signal of MCKO, BCLK and LRCK outputted from AK4114 is inputted into AK5702 .
Set up jumper pins of MCKI clock
JP7
MCKI_SEL JP5
TDMMCLK_SEL JP8
MKFS
DIT EXT
256fs
512fs
JP1 6
XTI
EXT_MCLK
MCKO
1024fs
384/768fs
MCKO
EXT_MCLK
384fs-768
JP32
MCLK_SEL
MCKO EXT_MCLK
* The setting of JP8(MKFS) is invalid in thi s mode,but if JP8(MKFS) is open, the input of the buffer will be unstable. So
JP8( MKFS) should set up any.
Set up jumper pins of BCLK clock
JP10
BCLK_SEL
JP9
BCLKFS
64fs-384
32fs-384
64fs
32fs
DIT
BCLKFS
BNC_BCLK
JP2 8
M/S
M S
ASAHI KASEI [AKD5702-A]
<KM086501> 2007 / 04
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Set up jumper pins of LRCK clock
JP13
LRCK_SEL
JP11
LRC KFS
2fs-384
1fs-384
2fs
1fs
DIT
LRCKFS
BNC_LRCK
Set up jumper pins of SDTO
JP29
SDTOB
JP30
SDTO_SEL
BA
(5) EXT Master Mo de
* Connect PORT 4 ( DSP1) with DSP.
Figure bel ow show s PORT4 pin assign. In this mode, MCKI should be supplied from PORT4, but BCLK and LRC K
should not be supplied.
PORT4
GND
GND
NC
NC
SDTOBVD
SDTOA
LRCK
BCLK
MCKI
a) Set up jumper pins of MCKI clock
JP7
MCKI_SEL JP5
TDMMCLK_SEL JP8
MKFS
DIT EXT
256fs
512fs
JP1 6
XTI
EXT_MCLK
MCKO
1024fs
384/768fs
MCKO
EXT_MCLK
384fs-768
JP32
MCLK_SEL
MCKO EXT_MCLK
* The setting of JP8(MKFS) is invalid in thi s mode,but if JP8(MKFS) is open, the input of the buffer will be unstable. So
JP8( MKFS) should set up any.
b) Set up jumper pins of BCLK clock
JP10
BCLK_SEL
JP9
BCLKFS
64fs-384
32fs-384
64fs
32fs
DIT
BCLKFS
BNC_BCLK
JP2 8
M/S
M S
ASAHI KASEI [AKD5702-A]
<KM086501> 2007 / 04
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c) Set up jumper pins of LRCK clock
JP13
LRCK_SEL
JP11
LRC KFS
2fs-384
1fs-384
2fs
1fs
DIT
LRCKFS
BNC_LRCK
d) Set up jumper pins of SDTO
JP29
SDTOB
JP30
SDTO_SEL
BA
DIP Switch set up
[SW1] (M ODE): Mode Setting of AK4114
ON is “H”, OFF is “L”.
No. Name ON (“H”) OFF (“L”)
1 I2S
2 M/S AK4114 Audio Format Setting
See Table 2
3 OCKS0
4 OCKS1 Master Clock Frequency Select
See Table 3
5 CAD1
6 CAD0 Chip Address pin
7 TEST “L”
8 I2C µp Control Mode Select pin
“H”: I2C, “L”: 3-wire serial
Table 1. Mode Setting
Resistor for AK5702 Set up for AK4114 SW1
M/S DIF1 DIF0 DIF1 DIF0 DAUX
0 1 0 0 0 24bit, Left justified Master
0 1 1 0 1 24bit, I2S Master Default
1 1 0 1 0 24bit, Left justified Slave
1 1 1 1 1 24bit, I2S Slave
Tab le 2. Setting for AK5702 and AK4114 Audio Interface Format
No. OCKS1 OCKS0 MCKO1 X’tal
0 0 0 256fs 256fs
Default
2 1 0 512fs 512fs
Table 3. Master Clock Frequency Select for AK4114 (Stereo mode)
ASAHI KASEI [AKD5702-A]
<KM086501> 2007 / 04
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Other jumper pins set up
1. JP1, JP 3 (M PWRB) : Connect to MPWRB
OPEN : No connect <Default>
SHORT : Connect to MPWRB
2. JP2, JP4 (MPWRA) : Connect to MPWRA
OPEN : No connect <Default>
SHORT : Conne ct to MPWRA
3. JP17 (LIN125_SEL) : Select input pin from J4
LIN1 : Enable to input to LIN1 from J4 <Default>
LIN2 : Enable to input to LIN2 from J4
LIN5 : Enable to input to LIN5 from J4
4. JP18 (RIN125_SEL) : Select input pin from J6
RIN1 : Enable to input to RIN1 from J6 <Default>
RIN2 : Enable to input to RIN2 from J6
RIN5 : Enable to input to RIN5 from J6
5. JP19 (LIN5_SEL) : Select input connecter to LIN5
LIN125 : Enable to input to LIN5 from J4 <Default>
LIN345 : Enable to input to LIN5 from J7
6. JP20 (RIN5_SEL) : Select input connecter to RIN5
RIN125 : Enable to input to RIN5 from J6 <Default>
RIN345 : Enable to input to RIN5 from J9
7. JP21 (LIN345_SEL) : Select input pin from J7
LIN3 : Enable to input to LIN3 from J7 <Default>
LIN4 : Enable to input to LIN4 from J7
LIN5 : Enable to input to LIN5 from J7
8. JP22 (RIN345_SEL) : Select input pin from J9
RIN3 : Enable to input to RIN3 from J9 <Default>
RIN4 : Enable to input to RIN4 from J9
RIN5 : Enable to input to RIN5 from J9
9. JP35 (SDTOB_SEL) : Select input pin to TDMI N
PDOWN : Conne ct to GND <Default>
SDTOB : Connect to SDTOB
10. JP 36 (CTRL_SEL) : Select for µp Control Mode
3-WIRE : Select to 3-WIRE <Default>
I2C : Select to I2C
11. JP 37 (GND) : Analog ground and Digital ground
OPEN : Separated. <Default>
SHORT : Common. (The connecto r “DGN D” should b e open.)
12. JP38 (AVDD_SEL) : AVDD of the AK5702
REG : AVDD is supplied from the regulator (“AVDD” jack should be open). < Default >
AVDD : AVDD is supplie d fr om “AVDD ” jack.
ASAHI KASEI [AKD5702-A]
<KM086501> 2007 / 04
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13. JP39 (DVDD_SEL) : DVDD of the AK5702
AVDD : DVDD is supplied fr om “AVDD”. < Default >
DVDD : DVDD is supplied from “DVDD ” jack.
14. JP40 (LVC_SEL) : Supply line selection of Logic block of LVC.
DVDD : Logic b l oc k o f LVC is supplied fr om “DVDD”. < Default >
VD : Logic block of LVC is supplied from “VD ” jack.
The fu nction of the toggl e SW
[SW2] (PD N): Power control of AK5702 . Keep “H” during normal operation.
[SW3] (DI T): Power control of AK4114. Keep “H” during normal operation.
Keep “L” when AK4114 is not used.
Indication for LED
[LED1] (ERF): Monitor INT0 pin of the AK4114. LED turns on when some error has occurred to AK4114 .
Serial Control
The AK5702 can be controlled via the printer port (parallel port) of IBM-AT compatible PC. Connect PORT3
(CTRL) with PC by 10-wire flat cable pa cked with the AKD5702-A
10pin Header
CSN
10 Wir e Flat Cable
CCLK
CDTI
10pin Connector
PC
Connect
AKD5702-A
Figure 2. Connect of 10 wire flat cable
ASAHI KASEI [AKD5702-A]
<KM086501> 2007 / 04
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Analog Input / Output Circuits
(1) Input Circuits
a) LIN, RIN, MIC Input Circuit
LIN1
LIN5
RIN5
RIN1
RIN1
RIN2
RIN2
RIN5
LIN125
LIN5
LIN3
RIN5
RIN4
RIN3
RIN3
RIN4
LIN345 LIN4
JP20
RIN5_SEL
JP21
LIN345_SEL
JP22
RIN345_SEL
LIN3
LIN4
RIN345
LIN2
6
4
3
J8
MIC345
2
3
1
J7
MR-552LS
2
3
1
J9
MR-552LS
R26
(Open)
R27
(Open)
JP19
LIN5_SEL
JP17
LIN125_SEL
JP18
RIN125_SEL
LIN2
LIN1
RIN125
6
4
3
J5
MIC125
2
3
1
J4
MR-552LS
2
3
1
J6
MR-552LS
R24
(Open)
R25
(Open) LIN5
Figure 3. LIN, RIN, MI C Input Circuit
∗ AKM assumes no responsibility for the trouble when using the above circuit examples.
ASAHI KASEI [AKD5702-A]
<KM086501> 2007 / 04
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2. Control Software Manual
Set - up of evaluatio n boa r d and co nt r ol s of twar e
1. Set up the AKD5702-A according to previous term.
2. Connect IBM-A T compatible PC w it h A KD5702-A by 10-l ine type flat cable (packed w ith A KD5702-A). Take care
of the direction of 10pin header. (Please install the driver in the CD-ROM when this control software is used on
Window s 2000/XP. Please refer “Instal lation Manu al of Control Software Driver by A KM devi ce c on trol software”.
In case of Windows95/98/ME, this installation is not needed. This control software does not operate on Windows
NT.)
3. Insert the CD-ROM labeled “AK5702 Ev aluation Kit” into the CD-ROM drive.
4. Access the CD-ROM drive and double-click the icon of “akd5702-a.exe” to set up the control program.
Operation flow
Keep the following flow.
1. S et u p th e control program accordin g to explan ation above.
2. Click “Port Reset” button.
3. Click “Write default” button
Explanation of each buttons
1 . [Port Reset]: Set up the USB interface board (AKDUSBIF-A) when using the board.
2. [Write default]: Initialize the register of AK5702.
3. [All Write]: Write all registers that is currently displayed .
4. [Function1]: Dialog to write data by keyboard operation.
5. [Function2]: Dialog to write data by keyboard operation.
6. [Function3]: T he sequence of register setting can be set and executed.
7. [Function4]: T he sequence that is created on [Function3] can be assigned to buttons and executed.
8. [Function5]: The register setting that is created by [SAVE] function on main window can be assigned to
buttons and executed.
9. [SAVE]: Save the current register setting.
10. [OPEN]: Write the saved values to all register.
11. [Write]: Dialog to write data by mouse operation.
Indication of data
Input data is indicated on the register map. Red letter indicate s “ H” or “1” and blue one indicat es “L” or “0”. Blank is the
part that is not defined in the datasheet.
ASAHI KASEI [AKD5702-A]
<KM086501> 2007 / 04
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Explanation of each dialog
1. [Write Dialog]: Dialog to write data by mouse operation
There are dialogs corresponding to each regis ter.
Click t he [Write] button correspon ding to each regist er to set up the dialog. If y ou check th e check box, data becom es
“H” or “1 ”. If not, “L” or “0”.
If you want to write the input data to AK5702, click [OK] button. If not, click [Cancel] button.
2. [Function1 Dialog] : Dialog to write data by keyboard operation
Address Box: Input registers address in 2 figures of hexadecimal.
Data Box: Input registers data in 2 figures of hexadecimal.
If you want to write the input data to AK5702, click [OK] button. If not, click [Cancel] button.
3. [Function2 Dialog] : Di alo g to eva lu ate I VOL
There are dialogs corresponding to register of 18h and 19h.
Addre ss Box: Inp ut re gisters address in 2 figures o f hexadecimal.
Start Data Box: Input starts data in 2 figures of hexadecimal.
End Data Box: I nput end data in 2 figures of hexadecimal.
Interval Box: Data is written to AK5702 by this interval.
Step Box: Data changes by this step .
Mode Select Box:
If you check this check box, data reaches end data, and returns to start data.
[Example] St art Data = 00, End Da ta = 09
Data flow: 00 01 02 03 04 05 06 07 08 09 09 08 07 06 05 04 03 02 01 00
If you do not check this check box, data reaches end data, but does not return to start data.
[Example] St art Data = 00, End Da ta = 09
Data flow: 00 01 02 03 04 05 06 07 08 09
If you want to write the input data to AK5702, click [OK] button. If not, click [Cancel] button.
ASAHI KASEI [AKD5702-A]
<KM086501> 2007 / 04
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4. [SAVE] and [OPEN]
4-1. [SAVE]
All of current register setting values displayed on the main window are saved to the file. The extension of file name is
“akr”.
<Operation flow>
(1) Click [SAVE] Button.
(2) Set the file name and click [SAVE] Button. The extension of file name is “akr”.
4-2. [OPEN]
The register setting values saved by [SAVE] are written to the AK5702. The file type is the same as [SAVE].
<Operation flow>
(1) Click [OPEN] Button.
(2) Select the file (*.akr) and Click [OPEN] Button.
ASAHI KASEI [AKD5702-A]
<KM086501> 2007 / 04
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5. [Function3 Dialog]
The sequence of register setting can be set and executed.
(1) Clic k [F3] Button. The following is displayed.
(2) Set the control sequence.
Set the address, Data and Interval time. Set “-1” to the address of the step where the sequence should be paused.
(3) Click [START] button. Then this sequence is executed.
The sequence is paused at the step of Interval="-1". Click [START] button, the sequence restarts from the paused step.
This sequence can be saved and opened by [SAVE] and [OPEN] button on th e Fun cti on3 w in dow. The extens ion of file
name is “aks”.
Figure 1. [F3] window
ASAHI KASEI [AKD5702-A]
<KM086501> 2007 / 04
- 18 -
6. [Function4 Dialog]
The sequence file (*.aks) saved by [F unction3] can be listed up to 10 files, assigned to buttons and then executed.
When [F4] button is clicked, the window as shown in Figure 2 opens.
Figure 2. [F4] window
ASAHI KASEI [AKD5702-A]
<KM086501> 2007 / 04
- 19 -
6-1. [OPEN] buttons on left side and [START] buttons
(1) Click [OPEN] button and select the sequence file (*.aks) saved by [Function3].
The sequence file name is displayed as shown in Figure 3. ( In case that the selected sequence file name is
“DAC_Stereo_ON.aks”)
Figure 3. [F4] window (2)
(2) Click [START] button, then the sequence is executed.
6-2. [SAVE] and [OPEN] buttons on righ t side
[SA VE] : The nam e assign of sequence f ile displayed on [Fu nction4] w indow can be saved to the fi le. The file n ame is
“*.ak4”.
[OPEN] : The name assign of sequence file(*.ak4) saved by [SAVE] is loaded.
6-3. Note
(1) This function doesn't support the pause function of sequence function.
(2) All files used by [SAVE] and [OPEN] function on right side need to be in the same folder.
(3) When the sequence is changed in [Function3], the sequence file (* .ak s ) shou ld be loaded again in order to reflect the
change.
ASAHI KASEI [AKD5702-A]
<KM086501> 2007 / 04
- 20 -
7. [Function5 Dialog]
The register setting file(*.akr) saved by [SAVE] function on main window can be listed up to 10 files, assigned to
buttons and then executed. When [F5] button is clicked, the window as shown in Figure 4 opens.
Figure 4. [F5] window
7-1. [OPEN] buttons on left side and [WR ITE] button
(1) Click [OPEN] button and select the register setting file (*.akr).
T he register setting file name is displayed as shown in Figure 5. (In case that the selected file name is
“DAC_Output.akr”)
(2) Click [WRITE] button, then the register setting is executed.
ASAHI KASEI [AKD5702-A]
<KM086501> 2007 / 04
- 21 -
Figure 5. [F5] window (2)
7-2. [SAVE] and [OPEN] buttons on righ t side
[SAVE] : The name assi gn of registe r se tti ng file displayed on [Function5] window can be saved to the file. The file
name is “*.ak5”.
[OP E N] : The name assign of regist e r se tt ing file(*.ak5) saved by [SAVE] is loaded.
7-3. Note
(1) All files used by [SAVE] and [OPEN] function on right side need to be in the same folder.
(2) When the register sett in g is cha nged by [SAVE] Button on the m ain w i ndow , the reg ister setti ng file (* .akr) should be
loaded again in order to reflect the change.
ASAHI KASEI [AKD5702-A]
<KM086501> 2007 / 04
- 22 -
Revision History
Date Manual
Revision Board
Revision Reason Contents
2006/11/28 KM086500 0 First Edition
Er ror Correct P2.
Operation Sequence
1) Set up the power supply lines
1-1) Add (default) to the end of senten ce.
AVDD: open Æ open (3.0V, supply from regulator, for AVDD of
AK5702)
DVDD: open Æ open (3.0V, supply from regulator, for DVDD of
AK5702)
VD : for logic Æ (typ 3.0V, for logic of digital part)
1-2) “REG” jack should be open Æ open
AVDD: for AVDD of AK5702 (typ.3.0V)Æ (typ.3.0V, for
AVDD of AK5702)
DVDD: for DVDD of AK5702 (typ.3.0V)Æ (typ.3.0V, for
DVDD of AK5702)
VD : for logic Æ (typ 3.0V, for logic of digital part)
P2.
Evalua tion M ode
Applicable Evaluation Mode
(1) Evaluation of PLL, Master Mode Æ PLL Ma ster M ode
(2) Evaluati on of PLL, Sla ve Mode Æ PLL Sla ve M ode 1
(3) Evaluati on of PLL, Sla ve Mode Æ PLL Sla ve M ode 2
(4) Evaluation of EXT, Slave Mode Æ EXT Slave Mode
(5) EXT, Master Mode Æ EXT Ma ster Mode
P3-P10
(1) Evalua tion of PLL, Mas ter Mod e Æ PLL Master Mode
a) Set up jumper pin s of MC KI clock
(J1: EXT_MCKI) Æ J1 (EXT_MCKI)
JP8 Æ JP8 (MKFS)
b) Set up jumper pins of BCLK clock
JP9 Æ JP9 (BCLKFS)
(2) Evalua tion of PLL, Slave Mode Æ PLL Slave Mode 1
a) Set up jumper pin s of MC KI clock
(J1: MCLK_SEL) Æ J1 (EXT_MCKI)
(2-a) In the case of using AK4114
J1 Æ J1 (EXT_MCLK)
JP8 Æ JP8 (MKFS)
(3) Evalua tion of PLL, Slave Mode Æ PLL Slave Mode 2
(4) Evalua tion of EX T, Sla v e M o de Æ EXT Slave Mode
Connect PORT4 (DSP1) with DSP
In this mode, BCLK and LRCK should be supplied from PORT4,
but MCKI should not be supplied. Æ In this mode, MCKI, BCLK
an d LR CK shou ld be supplied from POR T4.
(4-a) In the case of using AK4114
JP16 Æ JP16 (XTI)
JP8 Æ JP8 (MKFS)
(5) EXT, Ma ster Mode Æ EXT Master Mode
a) Set up jumper pin s of MC KI clock
JP8 Æ JP8 (MKFS)
b) Set up jumper pins of BCLK clock
The directi on of jumper setup of JP2 8 (M/ S): S (Slave) Æ
M (Master)
P11.
Other jumper pins set up
12. JP38 (AVDD_SEL)
OPENÆREG
SHORTÆAVDD
2007/04/09 KM086501 1
Circuit Change Resistance value, Capacitance Value Change:
MCKI: R13: 51ÆR100:100, C100: OpenÆ22p
BICK: R101: ShortÆ100, C101: Ope nÆ22p
LRCK: R102: ShortÆ100, C102: OpenÆ22p
ASAHI KASEI [AKD5702-A]
<KM086501> 2007 / 04
- 23 -
IMP ORTA NT NOTICE
• Thes e products and their specifications are s ubject to change without notice. Before considering
any use or application, consult the Asahi Kasei Microsystem s Co., Ltd. ( AKM) sales off ice or
authorized distributor concerning t heir curr ent status.
• AKM assum es no liability for infringem ent of any patent, intellectual pr operty, or other right in the
application or use of any information contained herein.
• Any export of these products, or devices or systems containing them, may require an export license
or other o fficial app roval under t he law and regu lations of t he country of ex port pertaining to
customs and tar iff s, curr ency exchange, or strat egic m aterials.
• AKM products are neither intended nor aut horized for use as critical c omponents in any safety, life
support, or other hazard related device or s ystem , and AKM as sume s no respon sibility relating to
any such use, except with the express written cons ent of the Representat ive Director of AKM. As
used here:
(a) A hazard related device or system is one designed or intended for life support or maintenance of
safety or f or applications in m edicine, aerospac e, nuclear ener gy, or oth er f ields, in which its
failure to func tion or perf orm may reas onably be expect ed to res ult in loss of lif e or in s ignific ant
injury or damage to person or pr operty.
(b) A critical component is one whose failure to function or perform may reasonably be expected to
result, whether directly or indirectly, in the loss of the safety or eff ectiveness of the device or
system cont aining it, and which m ust ther efore m eet very high standards of perf orm ance a nd
reliability.
• It is the responsibility of the buyer or distributor of a n AKM product who dis tributes, disposes of , or
otherwise places the prod uct with a thir d party to notify that party in advance of the above content
and conditions, and the buyer or distributor agrees to assume any and all respons ibility and liability
for and hold AKM harmles s from any and all claims arising f rom the use of said pro duct in the
absence of such not ification.
A
A
B
B
C
C
D
D
E
E
E E
D D
C C
B B
A A
LIN2
RIN2
PDN
DVDD
CAD0
RIN3
LIN3
RIN4
LIN4
RIN5
LIN5
RIN1
LIN1
TEST
5702_TDMIN
CDTI/SDA
CCLK/SCL
CSN/CAD1
5702_MCKO
I2C
5702_MCKI
AVDD
5702_SDTOA
5702_SDTOB
5702_LRCK
5702_BCLK
Title
Size Document Number Rev
Date: Sheet of
AK5702
1
AKD5702-A
A3
16Monday, April 09, 2007
Title
Size Document Number Rev
Date: Sheet of
AK5702
1
AKD5702-A
A3
16Monday, April 09, 2007
Title
Size Document Number Rev
Date: Sheet of
AK5702
1
AKD5702-A
A3
16Monday, April 09, 2007
R10 51R10 51
12
+C15
10u
+C15
10u
R4 2.2kR4 2.2k
1 2
+
C7
1u
+
C7
1u
C16
0.1u
C16
0.1u
R101 100R101 100
1
2
3
4
5
6
7
8
CN1
32pin_1
CN1
32pin_1
C14
4.7n
C14
4.7n
R9 51R9 51
R6 2.2kR6 2.2k
1 2
+
C10 1u
+
C10 1u
R11
10k
R11
10k
9
10
11
12
13
14
15
16
CN2
32pin_2
CN2
32pin_2
R8 (open)R8 (open)
1 2
+
C4
1u
+
C4
1u
1 2
+
C1
1u
+
C1
1u
JP4 MPWARJP4 MPWAR
1 2
+
C11
2.2u
+
C11
2.2u
R7 (open)R7 (open)
R14
51
R14
51
JP3 MPWBRJP3 MPWBR
1 2
+
C6
1u
+
C6
1u
JP1 MPWBRJP1 MPWBR
C100 22pC100 22p
1 2
+
C2
1u
+
C2
1u
R18
51
R18
51
C101 22pC101 22p
R5 2.2kR5 2.2k
R15
51
R15
51
R102 100R102 100
R2 (open)R2 (open)
R17
51
R17
51
R3 2.2kR3 2.2k
R12 51R12 51
1 2
+
C8
1u
+
C8
1u
JP2 MPWARJP2 MPWAR
R1 (open)R1 (open)
12
+
C18
10u +
C18
10u
1 2
+
C5
1u
+
C5
1u
17
18
19
20
21
22
23
24
CN3
32pin_3
CN3
32pin_3
R100 100R100 100
1 2
+
C9 1u
+
C9 1u
MPWRB
1
VCOM
2
PDN
3
CAD0
4
DVDD
5
VSS2
6
LRCK
7
SDTOB
9
SDTOA
10
MCKO
11
TEST
12
TDMIN
13
CDTI
14
CCLK
15
MCKI 17
I2C 18
VSS1 19
AVDD 20
VCOC 21
MPWRA 22
LIN2 23
RIN1 26
LIN5 27
RIN5 28
LIN4 29
RIN4 30
LIN3 31
RIN3 32
BCLK
8
CSN
16
RIN2 24
LIN1 25
U1
AK5702
U1
AK5702
C102 22pC102 22p
C17
0.1u
C17
0.1u
C13 (open)C13 (open)
C12
0.1u
C12
0.1u
25
26
27
28
29
30
31
32
CN4
32pin_4
CN4
32pin_4
1 2
+
C3
1u
+
C3
1u
R16
(short)
R16
(short)
A
A
B
B
C
C
D
D
E
E
E E
D D
C C
B B
A A
EXT_BCLK
MCKO
4114_MCKO
EXT_LRCK
EXT_MCLK
VD
4114_LRCK
4114_BICK
Title
Size Document Number Rev
Date: Sheet of
CLOCK
1
AKD5702-A
A3
26Monday, April 09, 2007
Title
Size Document Number Rev
Date: Sheet of
CLOCK
1
AKD5702-A
A3
26Monday, April 09, 2007
Title
Size Document Number Rev
Date: Sheet of
CLOCK
1
AKD5702-A
A3
26Monday, April 09, 2007
1024fs 32fs-384
512fs
256fs
64fs
32fs
1fs
MCKO
2fs
384/768fs
64fs-384
1fs-384
2fs-384
DIT
EXT BNC_BCLK
BNC_LRCK
DIT
DIT
BCLKFS
LRCKFS
256fs
128fs
384fs-768
EXT_MCLK
JP7
MCKI_SEL
JP7
MCKI_SEL
1PR
41CK
31D
21CLR
12PR
10 2CK
11 2D
12 2CLR
13
VCC
14 GND
7
1Q 5
1Q 6
2Q 9
2Q 8
U2
74AC74
U2
74AC74
12
3
4
5
J3
EXT_LRCK
J3
EXT_LRCK
JP10
BCLK_SEL
JP10
BCLK_SEL
12
3
4
5
J2
EXT_BCLK
J2
EXT_BCLK
C20
0.1u
C20
0.1u
JP9
BCLKFS
JP9
BCLKFS
JP8
MKFS
JP8
MKFS
C19
0.1u
C19
0.1u
R19
51
R19
51
A
3
QA 14
B
4
QB 13
C
5
QC 12
D
6
QD 11
RCO 15
ENP
7ENT
10
CLK
2
LOAD
9CLR
1
VCC
16 GND
8
U4
74AC163
U4
74AC163
C21
0.1u
C21
0.1u
R21
51
R21
51
JP6
TDMBCLK_SEL
JP6
TDMBCLK_SEL
JP12
EXT
JP12
EXT
R20
51
R20
51
JP13
LRCK_SEL
JP13
LRCK_SEL
CLK
10
RST
11 Q1 9
Q2 7
Q3 6
Q4 5
Q5 3
Q6 2
Q7 4
Q8 13
Q9 12
Q10 14
Q11 15
Q12 1
VDD
16
VSS
8
U3
74HC4040
U3
74HC4040
C22
0.1u
C22
0.1u
JP15
EXT
JP15
EXT
JP5
TDMMCLK_SEL
JP5
TDMMCLK_SEL
JP11
LRCKFS
JP11
LRCKFS
JP14
EXT
JP14
EXT
12
3
4
5
J1
EXT_MCKI
J1
EXT_MCKI
GND
7
1A
1
3A
5
5A
11 5Y 10
3Y 6
1Y 2
2Y 4
4Y 8
6Y 12
6A
13
4A
92A
3
VCC
14
U5
74HCU04
U5
74HCU04
A
A
B
B
C
C
D
D
E
E
E E
D D
C C
B B
A A
DAUX
VD
VD
VD
OCKS0
OCKS1
VD
VD
INT0
VD
OCKS1
OCKS0
4114_MCKO
EXT_MCLK
MCKO
4114_BICK
4114_LRCK
CAD0
TEST
I2C
DVDD
CAD1
VD
4114_PDN
Title
Size Document Number Rev
Date: Sheet of
DIT
1
AKD5702-A
A3
36Monday, April 09, 2007
Title
Size Document Number Rev
Date: Sheet of
DIT
1
AKD5702-A
A3
36Monday, April 09, 2007
Title
Size Document Number Rev
Date: Sheet of
DIT
1
AKD5702-A
A3
36Monday, April 09, 2007
I2S
OCKS1
M/S
OCKS0
I2C
CAD0
TEST
CAD1
R22
470
R22
470
1 2
+
C32
10u
+
C32
10u
OUT 1
VCC 3
GND 2
PORT1
TORX141
PORT1
TORX141
C25
0.1u
C25
0.1u
C26
0.47u
C26
0.47u
IPS0
1
NC
2
DIF0
3
TEST2
4
DIF1
5
NC
6
DIF2
7
IPS1
8
P/SN
9
XTL0
10
XTL1
11
TVDD
13
DVSS
14
TX0
15
TX1
16
BOUT
17
COUT
18
UOUT
19
VOUT
20
DVDD
21
DVSS
22
MCKO1
23
BICK 26
MCKO2 27
DAUX 28
XTO 29
XTI 30
PDN 31
CM0 32
CM1 33
OCKS1 34
OCKS0 35
INT0 36
AVDD 38
R39
VCOM 40
AVSS 41
RX0 42
NC 43
RX1 44
TEST1 45
RX2 46
NC 47
RX3 48
VIN
12
LRCK
24
SDTO 25
INT1 37
U6
AK4114
U6
AK4114
C28
5p
C28
5p
1 2
+
C31
10u
+
C31
10u
GND 1
VCC 2
IN 3
PORT2
TOTX141
PORT2
TOTX141
C30
0.1u
C30
0.1u
12
+
C24
10u
+
C24
10u
C29
0.1u
C29
0.1u
1 2
L1
(short)
L1
(short)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SW1
SW DIP-8
SW1
SW DIP-8
1
2
3
4
5
6
7
8
9
RP1
47k
RP1
47k
JP16 XTIJP16 XTI
C27
5p
C27
5p
C33
0.1u
C33
0.1u
12
X1
11.2896MHz
X1
11.2896MHz
R23
18k
R23
18k
C23
0.1u
C23
0.1u
A
A
B
B
C
C
D
D
E
E
E E
D D
C C
B B
A A
LIN1
LIN2
LIN5
RIN1
RIN2
RIN5
LIN3
RIN3
RIN4
LIN4
Title
Size Document Number Rev
Date: Sheet of
Input
1
AKD5702-A
A3
46Monday, April 09, 2007
Title
Size Document Number Rev
Date: Sheet of
Input
1
AKD5702-A
A3
46Monday, April 09, 2007
Title
Size Document Number Rev
Date: Sheet of
Input
1
AKD5702-A
A3
46Monday, April 09, 2007
LIN125
LIN1
LIN2
RIN125
LIN5
RIN5
RIN1
RIN2
LIN5
RIN5
RIN3
RIN4
LIN345
LIN3
LIN4
RIN345
2
3
1
J9
MR-552LS
J9
MR-552LS
JP20
RIN5_SEL
JP20
RIN5_SEL
JP18
RIN125_SEL
JP18
RIN125_SEL
2
3
1
J4
MR-552LS
J4
MR-552LS
R24
(Open)
R24
(Open)
JP21
LIN345_SEL
JP21
LIN345_SEL
R27
(Open)
R27
(Open)
R26
(Open)
R26
(Open)
R25
(Open)
R25
(Open)
2
3
1
J6
MR-552LS
J6
MR-552LS
6
4
3
J8
MIC345
J8
MIC345
JP19
LIN5_SEL
JP19
LIN5_SEL
JP22
RIN345_SEL
JP22
RIN345_SEL
6
4
3
J5
MIC125
J5
MIC125
2
3
1
J7
MR-552LS
J7
MR-552LS
JP17
LIN125_SEL
JP17
LIN125_SEL
A
A
B
B
C
C
D
D
E
E
E E
D D
C C
B B
A A
VD
VD
5702_MCKI
CSN/CAD1
CCLK/SCL
PDN
DAUX
EXT_MCLK
EXT_LRCK
CAD1
LVC
VD
VD
VDINT0
4114_PDN
VD
EXT_BCLK
VD LVC
5702_TDMIN
5702_BCLK
5702_LRCK
VD LVC
LVCVD
5702_SDTOB
5702_MCKOMCKO
5702_SDTOA
VD
VD
CDTI/SDA
Title
Size Document Number Rev
Date: Sheet of
LOGIC
1
AKD5702-A
A2
56Monday, April 09, 2007
Title
Size Document Number Rev
Date: Sheet of
LOGIC
1
AKD5702-A
A2
56Monday, April 09, 2007
Title
Size Document Number Rev
Date: Sheet of
LOGIC
1
AKD5702-A
A2
56Monday, April 09, 2007
CCLK/SCI
CDTI/SDA
CSN/CAD1
LH
MCKI
BCLK
LRCK
VD
SDTOA SDTOB
CDTO/SDA(ACK)
I2C
3-WIRE
SDTO
MCKO
BCLK
LRCK
VCC
HL
PDN
MCKI
BCLK
LRCK
TDMIN
VD
SDTOB
P_DOWN TDMIN
C43
0.1u
C43
0.1u
C36
0.1u
C36
0.1u
21
3
SW3
4114_PDN
SW3
4114_PDN
GND
7
1A
1
3A
5
5A
11 5Y 10
3Y 6
1Y 2
2Y 4
4Y 8
6Y 12
6A
13
4A
9
2A
3
VCC
14
U12
74HC14
U12
74HC14
1
2
3
4
5 6
7
8
9
10
PORT6
CTRL
PORT6
CTRL
R37
100k
R37
100k
JP36
CTRL_SEL
JP36
CTRL_SEL
JP32
MCLK_SEL
JP32
MCLK_SEL
C41
0.1u
C41
0.1u
R29 10kR29 10k
KA
D2
HSU119
D2
HSU119
JP28
M/S
JP28
M/S
C34
0.1u
C34
0.1u
R38 (short)R38 (short)
R36 470R36 470
C35
0.1u
C35
0.1u
C40
0.1u
C40
0.1u
1
2
3
4
5 6
7
8
9
10
PORT5
TDM
PORT5
TDM
R28
(open)
R28
(open)
21
3
SW2
PDN
SW2
PDN
6
5
4
3
2
1
7
RP3
R-PACK6R
RP3
R-PACK6R
R34 470R34 470
R31 10kR31 10k
A1
3
A2
4
A4
6
A5
7
A6
8
A7
9
A8
10
OE 22
B1 21
B2 20
B3 19
B4 18
B5 17
B6 16
B7 15
B8 14
VCCB 24
GND 13
A3
5
DIR
2VCCB 23
VCCA
1
GND
11
GND
12
U7
74AVC8T245
U7
74AVC8T245
1
2
3
4
5 6
7
8
9
10
PORT3
DSP2
PORT3
DSP2
K A
LED1
ERF
LED1
ERF
R33 10kR33 10k
A1
3
A2
4
A4
6
A5
7
A6
8
A7
9
A8
10
OE 22
B1 21
B2 20
B3 19
B4 18
B5 17
B6 16
B7 15
B8 14
VCCB 24
GND 13
A3
5
DIR
2VCCB 23
VCCA
1
GND
11
GND
12
U9
74AVC8T245
U9
74AVC8T245
JP30
SDTO_SEL
JP30
SDTO_SEL
A1
3
A2
4
A4
6
A5
7
A6
8
A7
9
A8
10
OE 22
B1 21
B2 20
B3 19
B4 18
B5 17
B6 16
B7 15
B8 14
VCCB 24
GND 13
A3
5
DIR
2VCCB 23
VCCA
1
GND
11
GND
12
U10
74AVC8T245
U10
74AVC8T245
6
5
4
3
2
1
7
RP2
R-PACK6R
RP2
R-PACK6R
R35 10kR35 10k
R42
1k
R42
1k
R39
10k
R39
10k
KA
D1
HSU119
D1
HSU119
C44
0.1u
C44
0.1u
1A
1
1B
2
1Y
3
2A
4
2B
5
2Y
6
4B 13
4A 12
4Y 11
3B 10
3A 9
3Y 8
VCC 14
GND 7
U8
74LVC32
U8
74LVC32
JP35
SDTOB_SEL
JP35
SDTOB_SEL
1
2
3
4
5 6
7
8
9
10
PORT4
DSP1
PORT4
DSP1
1A
11Y 2
VCC
14
GND
7
2A
33A
54A
95A
11 6A
13
2Y 4
3Y 6
4Y 8
5Y 10
6Y 12
U11
74LVC07
U11
74LVC07
R32 470R32 470
R40
1k
R40
1k
C39
0.1u
C39
0.1u
JP29
SDTOB
JP29
SDTOB
C38
0.1u
C38
0.1u
C420.1u C420.1u
R30 (open)R30 (open)
R41
10k
R41
10k
C37
0.1u
C37
0.1u
A
A
B
B
C
C
D
D
E
E
E E
D D
C C
B B
A A
AVDD1
REG_IN
VD1
DVDD1
VD1REG_IN AVDD1 DVDD1
AVDD
LVC
VD
AVDD
DVDD
Title
Size Document Number Rev
Date: Sheet of
POWER
1
AKD5702-A
A3
66Monday, April 09, 2007
Title
Size Document Number Rev
Date: Sheet of
POWER
1
AKD5702-A
A3
66Monday, April 09, 2007
Title
Size Document Number Rev
Date: Sheet of
POWER
1
AKD5702-A
A3
66Monday, April 09, 2007
REG
DVDD
VD
DVDD
AVDD
AVDD1
1
AVDD1
T45_O
AVDD1
T45_O
TP1_AGND1TP1_AGND1
1
VD1
T45_O
VD1
T45_O
JP38
AVDD_SEL
JP38
AVDD_SEL
12
+
C48
47u +
C48
47u
JP40
LVC_SEL
JP40
LVC_SEL
IN OUT
GND
T1
TA48M03F
T1
TA48M03F
12
+
C46
47u
+
C46
47u
TP3_AGND1TP3_AGND1
12
+
C49
47u +
C49
47u
TP2_DGND1TP2_DGND1
1 2
L2
(short)
L2
(short)
C47
0.1u
C47
0.1u
1
DGND1
T45_BK
DGND1
T45_BK
TP3_DGND1TP3_DGND1
1
DVDD1
T45_O
DVDD1
T45_O
1 2
L3
(short)
L3
(short)
JP37
GND
JP37
GND
R43
5.1
R43
5.1
1 2
L4
(short)
L4
(short)
1
AGND1
T45_BK
AGND1
T45_BK
TP2_AGND1TP2_AGND1
JP39
DVDD_SEL
JP39
DVDD_SEL
1
REG1
T45_R
REG1
T45_R
12
+
C50
47u +
C50
47u
TP1_DGND1TP1_DGND1
C45
0.1u
C45
0.1u
