LT3753
1
Rev. C
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TYPICAL APPLICATION
FEATURES DESCRIPTION
Active Clamp Synchronous
Forward Controller
The LT
®
3753 is a current mode PWM controller optimized
for an active clamp forward converter topology, allowing
up to 100V input operation.
A programmable volt-second clamp allows primary switch
duty cycles above 50% for high switch, transformer and
rectifier utilization. Active clamp control reduces switch
voltage stress and increases efficiency. A synchronous
output is available for controlling secondary side syn-
chronous rectification.
The LT3753 is available in a 38-lead plastic TSSOP pack-
age with missing pins for high voltage spacings.
36V to 72V, 5V/20A Active Clamp Isolated Forward Converter
APPLICATIONS
n Input Voltage Range: 8.5V to 100V
n Programmable Volt-Second Clamp
n High Efficiency Control: Active Clamp,
Synchronous Rectification, Programmable Delays
n Short-Circuit (Hiccup Mode) Overcurrent Protection
n Programmable Soft-Start/Stop
n Programmable OVLO and UVLO with Hysteresis
n Programmable Frequency (100kHz to 500kHz)
n Synchronizable to an External Clock
n Industrial, Automotive and Military Systems
n 48V Telecommunication Isolated Power Supplies
All registered trademarks and trademarks are the property of their respective owners.
44.2k
1.87k
14.7k
57.6k
30.1k
100k
100k
V+
GND-F
GND-S
COLL
3.3nF 34.8k
REF
LT1431
1k 0.012Ω
10k
100Ω PS2801-1
1k
2.2nF
250V
1µF
22nF
4.7µF
25V
1µF
10V
22µF
10V
1k
VOUT
47µF
10V
VOUT
5V
20A
560µF
10V
3753 TA01
1µF
TAO
TAS
TOS
TBLNK
IVSEC
RT
SS1
SS2
FB
COMP
INTVCC
SOUT
ISENSEN
ISENSEP
OUTVIN AOUT
OC
1.96k
105k
UVLO_VSEC
LT3753
SYNC
100nF IRF6217
9:2
68nF
250V
BSC0902NSI
BSC0902NSI
BSC190N15NS3
3.3µH
137k
137k
+
••
4.7µF
100V
×3
VIN
36V TO 72V
GND
OVLO
100Ω
4.7nF
250V
0.22µF 200Ω 5Ω
5Ω
LT3753
2
Rev. C
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TABLE OF CONTENTS
Features ..................................................... 1
Applications ................................................ 1
Typical Application ........................................ 1
Description.................................................. 1
Table of Contents .......................................... 2
Absolute Maximum Ratings .............................. 3
Order Information .......................................... 3
Pin Configuration .......................................... 3
Electrical Characteristics ................................. 4
Typical Performance Characteristics ................... 7
Pin Functions .............................................. 10
Block Diagram ............................................. 11
Timing Diagrams .........................................12
Operation................................................... 14
Introduction ....................................................... 14
Part Start-Up ......................................................14
Applications Information ................................ 15
Programming System Input Undervoltage
Lockout (UVLO) Threshold and Hysteresis ......... 15
Soft-Stop Shutdown ........................................... 15
Micropower Shutdown ....................................... 15
Programming System Input Overvoltage
Lockout (OVLO) Threshold ................................. 15
Programming Switching Frequency .................... 16
Synchronizing to an External Clock .................... 16
INTVCC Regulator Bypassing and Operation ......16
Adaptive Leading Edge Blanking Plus
Programmable Extended Blanking...................... 17
Current Sensing and Programmable Slope
Compensation .................................................... 18
Overcurrent: Hiccup Mode .................................. 18
Programming Maximum Duty Cycle Clamp:
DVSEC (Volt-Second Clamp) ................................ 18
DVSEC Open Loop Control: No Opto-Coupler,
Error Amplifier or Reference ............................... 19
RIVSEC: Open Pin Detection Provides Safety ....... 19
Transformer Reset: Active Clamp Technique .....20
LO Side Active Clamp Topology (LT3753)...........20
HI Side Active Clamp Topology (LT3752-1) .........22
Active Clamp Capacitor Value and Voltage
Ripple .................................................................22
Active Clamp MOSFET Selection ........................23
Programming Active Clamp Switch Timing:
AOUT to OUT (tAO) and OUT to AOUT (tOA)
Delays ................................................................. 24
Programming Synchronous Rectifier Timing:
SOUT to OUT (tSO) and OUT to SOUT (tOS)
Delays ................................................................. 24
Soft-Start (SS1, SS2) .........................................25
Soft-Stop (SS1) ..................................................25
Hard-Stop (SS1, SS2) .........................................26
OUT, AOUT, SOUT Pulse-Skipping Mode ............ 27
AOUT Timeout ....................................................27
Main Transformer Selection ...............................27
Generating Auxiliary Supplies .............................28
Primary-Side Auxiliary Supply ............................29
Secondary-Side Auxiliary Supply .......................29
Primary-Side Power MOSFET Selection .............30
Synchronous Control (SOUT) .............................31
Output Inductor Value .........................................32
Output Capacitor Selection ................................. 32
Input Capacitor Selection ...................................32
PCB Layout/Thermal Guidelines ........................ 33
Package Description ..................................... 35
Revision History .......................................... 35
Typical Application ....................................... 36
Related Parts .............................................. 36
LT3753
3
Rev. C
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PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS
VIN ..........................................................................100V
UVLO_VSEC, OVLO ....................................................20V
INTVCC, SS2..............................................................16V
FB, SYNC ....................................................................6V
SS1, COMP, TEST1, RT ...............................................3V
ISENSEP, ISENSEN, OC, TEST2 ..................................0.35V
IVSEC .................................................................. –250µA
Operating Junction Temperature Range (Notes 2, 3)
LT3753EFE ......................................... –40°C to 125°C
LT3753IFE .......................................... –40°C to 125°C
LT3753HFE ........................................–40°C to 150°C
LT3753MPFE ..................................... –55°C to 150°C
Storage Temperature Range .................. –65°C to 150°C
Lead Temperature (Soldering, 10 Sec) ..................300°C
(Note 1)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
TOP VIEW
FE PACKAGE
VARIATION: FE38(31)
38-LEAD PLASTIC TSSOP
38
37
36
34
32
30
28
26
24
22
21
20
TEST1
NC
RT
FB
COMP
SYNC
SS1
IVSEC
UVLO_VSEC
OVLO
TAO
TAS
TOS
TBLNK
NC
NC
SS2
GND
PGND
PGND
NC
TEST2
NC
AOUT
SOUT
VIN
INTVCC
OUT
OC
ISENSEP
ISENSEN
39
PGND
GND
JA = 25°C/W
EXPOSED PAD (PIN 39) IS PGND AND GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LT3753EFE#PBF LT3753EFE#TRPBF LT3753FE 38-Lead Plastic TSSOP –40°C to 125°C
LT3753IFE#PBF LT3753IFE#TRPBF LT3753FE 38-Lead Plastic TSSOP –40°C to 125°C
LT3753HFE#PBF LT3753HFE#TRPBF LT3753FE 38-Lead Plastic TSSOP –40°C to 150°C
LT3753MPFE#PBF LT3753MPFE#TRPBF LT3753FE 38-Lead Plastic TSSOP –55°C to 150°C
Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
LT3753
4
Rev. C
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ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, UVLO_VSEC = 2.5V.
PARAMETER CONDITIONS MIN TYP MAX UNITS
Operational Input Voltage l8.5 100 V
VIN(ON) l7.75 8.4 V
VIN(OFF) 7.42 V
VIN(ON/OFF) Hysteresis l0.11 0.33 0.55 V
VIN Quiescent Current FB = 1.5V (Not Switching) 5.9 7.5 mA
UVLO_VSEC Micropower Threshold (VSD) IVIN < 20µA l0.2 0.4 0.6 V
VIN Shutdown Current (Micropower) UVLO_VSEC = 0.2V 20 40 µA
UVLO_VSEC Threshold (VSYS_UV)l1.180 1.250 1.320 V
VIN Shutdown Current (After Soft-Stop) UVLO_VSEC = 1V 165 220 µA
UVLO_VSEC (ON) Current UVLO_VSEC = VSYS_UV + 50mV 0 µA
UVLO_VSEC (OFF) Current
Hysteresis Current
With One-Shot Communication Current
UVLO_VSEC = VSYS_UV – 50mV
(Note 13)
l
4.0
5
25
6.0
µA
µA
OVLO (Rising) (No Switching, Reset SS1) l1.220 1.250 1.280 V
OVLO (Falling) (Restart SS1) 1.215 V
OVLO Hysteresis l23 35 47 mV
OVLO Pin Current (Note 8) OVLO = 0V
OVLO = 1.5V (SS1 = 2.7V)
OVLO = 1.5V (SS1 = 1.0V)
5
0.9
5
100
100
nA
mA
nA
Oscillator
Frequency: fOSC = 100kHz RT = 82.5k 94 100 106 kHz
Frequency: fOSC = 300kHz RT = 24.9k l279 300 321 kHz
Frequency: fOSC = 500kHz RT = 14k 470 500 530 kHz
fOSC Line Regulation RT = 24.9k, 8.5V < VIN < 100V 0.05 0.1 %/V
Frequency and DVSEC Foldback Ratio (Fold) SS1 = VSSACT + 25mV, SS2 = 2.7V 4
SYNC Input High Threshold (Note 4) l1.2 1.8 V
SYNC Input Low Threshold (Note 4) l0.6 1.025 V
SYNC Pin Current SYNC = 6V 75 µA
SYNC Frequency/Programmed fOSC 1.0 1.25 kHz/kHz
Linear Regulator (INTVCC)
INTVCC Regulation Voltage 9.4 10 10.4 V
Dropout (VIN-INTVCC) VIN = 8.75V, IINTVCC = 10mA 0.6 V
INTVCC UVLO(+) (Start Switching) 7 7.4 V
INTVCC UVLO(–) (Stop Switching) 6.8 7.2 V
INTVCC UVLO Hysteresis 0.1 0.2 0.3 V
INTVCC OVLO(+) (Stop Switching) 15.9 16.5 17.2 V
INTVCC OVLO(–) (Start Switching) 15.4 16 16.7 V
INTVCC OVLO Hysteresis 0.38 0.5 0.67 V
INTVCC Current Limit INTVCC = 0V
INTVCC = 8.75V
l
9.5
19 13
27 17
32 mA
mA
LT3753
5
Rev. C
For more information www.analog.com
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, UVLO_VSEC = 2.5V.
PARAMETER CONDITIONS MIN TYP MAX UNITS
Error Amplifier
FB Reference Voltage l1.220 1.250 1.275 V
FB Line Reg 8.5V < VIN < 100V 0.1 0.3 mV/V
FB Load Reg COMP_SW – 0.1V < COMP < COMP_VOH – 0.1V 0.1 0.3 mV/V
FB Input Bias Current (Note 8) 50 200 nA
Open-Loop Voltage Gain 85 dB
Unity-Gain Bandwidth (Note 6) 2.5 MHz
COMP Source Current FB = 1V, COMP = 1.75V (Note 8) 6 11 mA
COMP Sink Current FB = 1.5V, COMP = 1.75V 6.5 11.5 mA
COMP Output High Clamp FB = 1V 2.6 V
COMP Switching Threshold 1.25 V
Current Sense
ISENSEP Maximum Threshold FB = 1V, OC = 0V 180 220 260 mV
COMP Current Mode Gain ∆VCOMP/∆VISENSEP 6.1 V/V
ISENSEP Input Current (D = 0%) (Note 8) 2 µA
ISENSEP Input Current (D = 80%) (Note 8) 33 µA
ISENSEN Input Current FB = 1.5V (COMP Open) (Note 8)
FB = 1V (COMP Open) (Note 8) 20
90 30
135 µA
µA
OC Overcurrent Threshold l82.5 96 107.5 mV
OC Input Current 200 500 nA
AOUT Driver (Active Clamp Switch Control)
AOUT Rise Time CL = 1nF (Note 5), INTVCC = 12V 23 ns
AOUT Fall Time CL = 1nF (Note 5), INTVCC = 12V 19 ns
AOUT Low Level 0.1 V
AOUT High Level INTVCC = 12V 11.9 V
AOUT High Level in Shutdown UVLO_VSEC = 0V, INTVCC = 8V, IAOUT = 1mA Out
of the Pin 7.8 V
AOUT Edge to OUT (Rise): (tAO) CSOUT = 1nF, COUT = 3.3nF, INTVCC = 12V
RTAO = 44.2k
RTAO = 73.2k (Note 9)
168
253
218
328
268
403
ns
ns
OUT (Fall) to AOUT Edge: (tOA) CSOUT = 1nF, COUT = 3.3nF, INTVCC = 12V
RTAO = 44.2k
RTAO = 73.2k (Note 10)
150
214
196
295
250
376
ns
ns
SOUT Driver (Synchronous Rectification Control)
SOUT Rise Time COUT = 1nF, INTVCC = 12V (Note 5) 21 ns
SOUT Fall Time COUT = 1nF, INTVCC = 12V (Note 5) 19 ns
SOUT Low Level 0.1 V
SOUT High Level INTVCC = 12V 11.9 V
SOUT High Level in Shutdown UVLO_VSEC = 0V, INTVCC = 8V, ISOUT = 1mA Out
of the Pin 7.8 V
AOUT Edge to SOUT (Fall): (tAS) CAOUT = CSOUT = 1nF, INTVCC = 12V
RTAS = 44.2k (Note 11)
RTAS = 73.2k
168
253
218
328
268
403
ns
ns
SOUT (Fall) to OUT (Rise): (tSO = tAO – tAS) CSOUT = 1nF, COUT = 3.3nF, INTVCC = 12V
RTAO = 73.2k, RTAS = 44.2k (Notes 9, 11)
RTAO = 44.2k, RTAS = 73.2k
70
–70
110
–110
132
–132
ns
ns
LT3753
6
Rev. C
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ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, UVLO_VSEC = 2.5V.
PARAMETER CONDITIONS MIN TYP MAX UNITS
OUT (Fall) to SOUT (Rise): (tOS) CSOUT = 1nF, COUT = 3.3nF, INTVCC = 12V
RTOS = 14.7k
RTOS = 44.2k (Note 12)
52
102
68
133
84
164
ns
ns
OUT Driver (Main Power Switch Control)
OUT Rise Time COUT = 3.3nF, INTVCC = 12V (Note 5) 19 ns
OUT Fall Time COUT = 3.3nF, INTVCC = 12V (Note 5) 20 ns
OUT Low Level 0.1 V
OUT High Level INTVCC = 12V 11.9 V
OUT Low Level in Shutdown UVLO_VSEC = 0V, INTVCC = 8V, IOUT = 1mA Into
the Pin 0.25 V
OUT (Volt-Sec) Max Duty Cycle Clamp
DVSEC (1 • System Input (Min)) × 100
DVSEC (2 • System Input (Min)) × 100
DVSEC (4 • System Input (Min)) × 100
RT = 22.6k, RIVSEC = 51.1k, FB = 1V, SS1 = 2.7V
UVLO_VSEC = 1.25V
UVLO_VSEC = 2.50V
UVLO_VSEC = 5.00V
68.5
34.3
17.5
72.5
36.5
18.6
76.2
38.7
19.7
%
%
%
OUT Minimum ON Time COUT = 3.3nF, INTVCC = 12V (Note 7)
RTBLNK = 14.7k
RTBLNK = 73.2k (Note 14)
325
454
ns
ns
SS1 Pin (Soft-Start: Frequency and DVSEC) (Soft-Stop: COMP Pin, Frequency and DVSEC)
SS1 Reset Threshold (VSS1(RTH)) 150 mV
SS1 Active Threshold (VSS1(ACT)) (Allow Switching) 1.25 V
SS1 Charge Current (Soft-Start) SS1 = 1.5V (Note 8) 7 11.5 16 µA
SS1 Discharge Current (Soft-Stop) SS1 = 1V, UVLO_VSEC = VSYS_UV – 50mV 6.4 10.5 14.6 µA
SS1 Discharge Current (Hard Stop)
OC > OC Threshold
INTVCC < INTVCC UVLO(–)
OVLO > OVLO(+)
SS1 = 1V
0.9
0.9
0.9
mA
mA
mA
SS2 Pin (Soft-Start: Comp Pin)
SS2 Discharge Current SS1 < VSS(ACT), SS2 = 2.5V 2.8 mA
SS2 Charge Current SS1 > VSS(ACT), SS2 = 1.5V 11 21 28 µA
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LT3753EFE is guaranteed to meet performance specifications
from 0°C to 125°C junction temperature. Specifications over the –40°C
to 125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LT3753IFE is guaranteed to meet performance specifications from –40°C
to 125°C junction temperature. The LT3753HFE is guaranteed to meet
performance specifications from –40°C to 150°C junction temperature.
The LT3753MPFE is tested and guaranteed to meet performance
specifications from –55°C to 150°C junction temperature.
Note 3: For maximum operating ambient temperature, see the Thermal
Calculations section in the Applications Information section.
Note 4: SYNC minimum and maximum thresholds are guaranteed by
SYNC frequency range test using a clock input with guard banded SYNC
levels of 0.7V low level and 1.7V high level.
Note 5: Rise and fall times are measured between 10% and 90% of gate
driver supply voltage.
Note 6: Guaranteed by design.
Note 7: ON times are measured between rising and falling edges at 50% of
gate driver supply voltage.
Note 8: Current flows out of pin.
Note 9: Guaranteed by correlation to RTAS = 73.2k test.
Note 10: tOA timing guaranteed by design based on correlation to
measured tAO timing.
Note 11: Guaranteed by correlation to RTAO = 44.2k test.
Note 12: Guaranteed by correlation to RTOS = 14.7k test.
Note 13: A 2µs one-shot of 20µA from the UVLO_VSEC pin allows
communication between ICs to begin shutdown (useful when stacking
supplies for more power ( = inputs in parallel/outputs in series)). The
current is tested in a static test mode. The 2µs one-shot is guaranteed by
design.
Note 14: Guaranteed by correlation to RTBLNK = 14.7k test.
LT3753
7
Rev. C
For more information www.analog.com
VIN Shutdown Current
vs Junction Temperature
VIN(ON), VIN(OFF) Thresholds
vs Junction Temperature
VIN Quiescent Current vs Junction
Temperature
UVLO_VSEC Turn-On Threshold
vs Junction Temperature
UVLO_VSEC Hysteresis Current
vs Junction Temperature
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
JUNCTION TEMPERATURE (°C)
–75
INTVCC (V)
10.0
9.5
9.0
8.5
7.5
8.0
5.5
7.0
6.5
6.0
5.0 25 150–25 100
3753 G06
1750 125–50 50 75
ILOAD = 0mA
ILOAD = 10mA
ILOAD = 15mA
ILOAD = 20mA
VIN = 12V
JUNCTION TEMPERATURE (°C)
–75
INTVCC UVLO THRESHOLDS (V)
7.20
7.15
7.10
7.05
6.65
7.00
6.95
6.90
6.85
6.80
6.75
6.70
6.60 25 150–25 100
3753 G07
1750 125–50 50 75
INTVCC < UVLO (–): DISABLE FORWARD
CONVERTER SWITCHING
INTVCC > UVLO (+): ENABLE FORWARD
CONVERTER SWITCHING
JUNCTION TEMPERATURE (°C)
–75
INTVCC (V)
10.00
9.95
9.90
9.85
9.80
9.65
9.75
9.70
9.40
9.60
9.55
9.50
9.45
25 150–25 100
3753 G08
1750 125–50 50 75
ILOAD = 0mA
ILOAD = 10mA
ILOAD = 20mA
ILOAD = 30mA
VIN = 12V
INTVCC in Dropout at VIN = 8.75V
vs Current, Junction Temperature
INTVCC UVLO Thresholds vs
Junction Temperature
INTVCC Regulation Voltage vs
Current, Junction Temperature
SS1 Soft-Start/Soft-Stop Pin
Currents vs Junction Temperature
JUNCTION TEMPERATURE (°C)
–75
SS1 CURRENTS (µA)
14.0
13.5
13.0
12.5
8.5
12.0
11.5
11.0
10.5
10.0
9.5
9.0
8.0 25 150–25 100
3753 G09
1750 125–50 50 75
SS1 SOFT-START: CHARGE CURRENT* (–1)
SS1 SOFT-STOP: DISCHARGE CURRENT
JUNCTION TEMPERATURE (°C)
–75
VIN CURRENT (µA)
40
30
20
10
025 150–25 100
3753 G01
1750 125–50 50 75
VIN = 12V, UVLO_VSEC = 0.2V
JUNCTION TEMPERATURE (°C)
–75
VIN ON/OFF THRESHOLDS (V)
9.0
8.5
8.0
7.5
7.0
6.5
6.0 25 150–25 100
3753 G02
1750 125–50 50 75
VIN_ON
VIN_OFF
JUNCTION TEMPERATURE (°C)
–75
VIN IQ (mA)
8
7
6
5
425 150–25 100
3753 G03
1750 125–50 50 75
VIN = 12V, NO SWITCHING
JUNCTION TEMPERATURE (°C)
–75
UVLO_VSEC THRESHOLD (V)
1.275
1.270
1.265
1.260
1.255
1.250
1.245
1.240
1.235
1.230
1.225 25 150–25 100
3753 G04
1750 125–50 50 75
JUNCTION TEMPERATURE (°C)
–75
UVLO_VSEC HYSTERESIS CURRENT (µA)
6.0
5.5
5.0
4.5
4.0 25 150–25 100
3753 G05
1750 125–50 50 75
LT3753
8
Rev. C
For more information www.analog.com
SS1 High, Active and Reset
Levels vs Junction Temperature
SS2 Soft-Start Charge Current
vs Junction Temperature
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
Switching Frequency
vs SS1 Pin Voltage
Switching Frequency
vs Junction Temperature
FB Reference Voltage
vs Junction Temperature
JUNCTION TEMPERATURE (°C)
–75
SS1 HIGH, ACTIVE AND RESET LEVELS (V)
3.00
2.75
2.50
2.25
0.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
025 150–25 100
3753 G10
1750 125–50 50 75
SS1 ACTIVE LEVEL
(ALLOW FORWARD CONVERTER SWITCHING)
SS1 HIGH LEVEL
SS1 RESET LEVEL (RESET SS1 LATCH)
JUNCTION TEMPERATURE (°C)
–75
SS2 SOFT-START CHARGE CURRENT (µA)
25
24
23
16
22
21
20
19
18
17
15 25 150–25 100
3753 G11
1750 125–50 50 75
SS2 PIN CURRENT* (–1)
JUNCTION TEMPERATURE (°C)
–75
SWITCHING FREQUENCY (kHz)
325
320
315
280
310
305
300
295
290
285
275 25 150–25 100
3753 G13
1750 125–50 50 75
RT = 24.9k
JUNCTION TEMPERATURE (°C)
–75
FB REFERENCE VOLTAGE (V)
1.30
1.29
1.28
1.21
1.27
1.26
1.25
1.24
1.23
1.22
1.20 25 150–25 100
3753 G14
1750 125–50 50 75
COMP (V)
1.2
ISENSEP THRESHOLD (mV)
240
220
200
20
180
160
140
120
60
100
80
40
02.42.2
3753 G15
2.61.61.4 1.8 2
OC THRESHOLD
DUTY CYCLE (%)
0
ISENSEP MAXIMUM THRESHOLD - VSLOPE (V)
240
220
200
180
160
140 9080
3753 G16
1002010 30 40 50 60 70
RISLP = 0Ω
VSLP = I(ISENSEP) • RISLP
RISLP = 1.5kΩ
RISLP = 2kΩ
JUNCTION TEMPERATURE (°C)
–75
OC OVERCURRENT THRESHOLD (mV)
110
105
100
85
95
90
80 25 150–25 100
3753 G17
1750 125–50 50 75
ISENSEP Maximum Threshold
vs COMP
ISENSEP Maximum Threshold – VSLP
vs Duty Cycle (Programming Slope
Compensation)
OC Overcurrent
(Hiccup Mode) Threshold
vs Junction Temperature
SS1 (V)
0
SWITCHING FREQUENCY (kHz)
350
325
300
275
25
250
225
200
175
150
100
75
125
50
012.25 2.50.5 1.75
3753 G12
2.750.75 20.25 1.25 1.5
RT = 24.9k
LT3753
9
Rev. C
For more information www.analog.com
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
SOUT (Fall) to OUT (Rise) Delay
(tSO = tAO – tAS) vs Junction
Temperature
OUT (Fall) to SOUT (Rise) Delay
(tOS) vs Junction Temperature
Extended Blanking Duration
vs Junction Temperature
AOUT to SOUT Delay (tAS)
vs Junction Temperature
AOUT to OUT Delay (tAO) and OUT
to AOUT Delay (tOA) vs Junction
Temperature
Required RIVSEC vs Switching
Frequency (for DVSEC × 100 = 72.5%,
UVLO_VSEC = 1.25V)
OUT Pin Rise/Fall Times
vs OUT Pin Load Capacitance
OUT Maximum Duty Cycle Clamp
(DVSEC) vs UVLO_VSEC
JUNCTION TEMPERATURE (°C)
–75
EXTENDED BLANKING DURATION (ns)
220
200
180
100
80
160
140
120
60 25 150–25 100
3753 G18
1750 125–50 50 75
RTBLNK = 73.2k
RTBLNK = 14.7k
JUNCTION TEMPERATURE (°C)
–75
tAO AND tCA (ns)
340
300
320
280
200
180
160
260
240
220
140 25 150–25 100
3753 G19
1750 125–50 50 75
RTAO = 73.2k
tAO
RTAO = 44.2k
tOA
tAO
tOA
JUNCTION TEMPERATURE (°C)
–75
tAS (ns)
340
300
320
280
200
180
160
260
240
220
140 25 150–25 100
3753 G20
1750 125–50 50 75
RTAS = 73.2k
RTAS = 44.2k
JUNCTION TEMPERATURE (°C)
–75
tSO (ns)
120
80
100
60
–20
–40
–60
–80
–100
40
20
0
–120 25 150–25 100
3753 G21
1750 125–50 50 75
RTAO = 73.2k, RTAS = 44.2k
RTAO = 44.2k, RTAS = 73.2k
JUNCTION TEMPERATURE (°C)
–75
tSO (ns)
160
140
80
60
40
120
100
20 25 150–25 100
3753 G22
1750 125–50 50 75
RTOS = 44.2k
RTOS = 14.7k
RTOS = 7.32k
UVLO_VSEC (V)
0
IDVSEC × 100 (%)
80
70
40
30
20
10
60
50
03.75 8.757.5
3753 G23
102.51.25 5 6.25
VIN = 12V
RT = 24.9k (300kHz)
RIVSEC = 51.1k
SWITCHING FREQUENCY (kHz)
100
PROGRAMMED RIVSEC (k)
160
140
80
60
40
20
120
100
0250 450400
3753 G24
500200150 300 350
OUT PIN LOAD CAPACITANCE (nF)
0
OUT PIN RISE/FALL TIMES (ns)
60
50
30
20
10
40
03 8 97
3753 G25
1021 4 65
INTVCC = 12V
LT3753
10
Rev. C
For more information www.analog.com
PIN FUNCTIONS
TEST1 (Pin 1): Connect to GND.
NC (Pins 2, 15, 16, 34, 37): No Connect Pins. These
pins are not connected inside the IC. These pins should
be left open.
RT (Pin 3): A resistor to ground programs switching
frequency.
FB (Pin 4): Error Amplifier Inverting Input.
COMP (Pin 5): Error Amplifier Output. Allows various
compensation networks for nonisolated applications.
SYNC (Pin 6): Allows synchronization of internal oscillator
to an external clock. fSYNC equal to fOSC allowed.
SS1 (Pin 7): Capacitor controls soft-start/stop of switch-
ing frequency and volt-second clamp. During soft-stop it
also controls the COMP pin.
IVSEC (Pin 8): Resistor Programs OUT Pin Maximum
Duty Cycle Clamp (DVSEC). This clamp moves inversely
proportional to system input voltage to provide a volt-
second clamp.
UVLO_VSEC (Pin 9): A resistor divider from system in-
put allows switch maximum duty cycle to vary inversely
proportional with system input. This volt-second clamp
prevents transformer saturation for duty cycles above
50%. Resistor divider ratio programs undervoltage lockout
(UVLO) threshold. A 5µA pin current hysteresis allows
programming of UVLO hysteresis. Pin below 0.4V reduces
VIN currents to microamps.
OVLO (Pin 10): A resistor divider from system input
programs overvoltage lockout (OVLO) threshold. Fixed
hysteresis included.
TAO (Pin 11): A resistor programs nonoverlap timing
between AOUT rise and OUT rise control signals.
TAS (Pin 12): Resistors at TAO and TAS define delay between
SOUT fall and OUT rise (= tAO – tAS).
TOS (Pin 13): Resistor programs delay between OUT fall
and SOUT rise.
TBLNK (Pin 14): Resistor programs extended blanking of
ISENSEP and OC signals during MOSFET turn-on.
SS2 (Pin 17): Capacitor controls soft-start of COMP pin.
Alternatively can connect to OPTO to communicate start of
switching to secondary side. If unused, leave the pin open.
GND (Pin 18): Analog Signal Ground. Electrical connection
exists inside the IC to the exposed pad (Pin 39).
PGND (Pins 19, 38, 39): The Power Grounds for the IC.
The package has an exposed pad (Pin 39) underneath the
IC which is the best path for heat out of the package. Pin 39
should be soldered to a continuous copper ground plane
under the device to reduce die temperature and increase
the power capability of the LT3753.
ISENSEN (Pin 20): Negative input for the current sense
comparator. Kelvin connect to the sense resistor in the
source of the power MOSFET.
ISENSEP (Pin 21): Positive input for the current sense
comparator. Kelvin connect to the sense resistor in the
source of the power MOSFET. A resistor in series with
ISENSEP programs slope compensation.
OC (Pin 22): An accurate 96mV threshold, independent
of duty cycle, for detection of primary side MOSFET over-
current and trigger of hiccup mode. Connect directly to
sense resistor in the source of the primary side MOSFET.
Missing Pins 23, 25, 27, 29, 31, 33, 35: Pins removed
for high voltage spacings and improved reliability.
OUT (Pin 24): Drives the gate of an N-channel MOSFET
between 0V and INTVCC. Active pull-off exists in shutdown.
INTVCC (Pin 26): A linear regulator supply generated from
VIN. Supplies 10V for AOUT, SOUT and OUT gate drivers.
INTVCC must be bypassed with a 4.7µF capacitor to power
ground. Can be externally driven by the housekeeping
supply to remove power from within the IC.
VIN (Pin 28): Input Supply Pin. Bypass with 1µF to ground.
SOUT (Pin 30): Sync signal for secondary side synchro-
nous rectifier controller.
AOUT (Pin 32): Control signal for external active clamp
switch.
TEST2 (Pin 36): Connect to GND.
LT3753
11
Rev. C
For more information www.analog.com
BLOCK DIAGRAM
+–
1.25V
+–
+–
+–
+–
1.25V (+)
1.215V (–)
EN_SS1
UVLO_VSEC
OUT
0.4V
5µA
SS1 > 1.25V
HARD STOP
0.9mA 7.75V(+)
7.42V(–)
VIN
SOFT STOP
SS1 < 150mV
20µA (1 SHOT)
UVLO_VSEC
9
VIN
OVLO
10
IVSEC
8
SYNC
100k
6
RT
3
SS2
17
SS1
FB
7
4
COMP
5
TAO
11
TAS
12
TOS
13
TBLNK GND
(+ EXPOSED
PAD PIN 39)
(+ EXPOSED
PAD PIN 39)
14 18
PGND (19, 38)
+
–
+
–
1.25V
REF
+
–
±0.4A
±0.4A
±2A
1.25V
OSC
FOLD
BACK
ISLP
1.25V
150mV
HARD
STOP
SOFT
START
SS2
1.25V
SS1
EN_SS1
(0→220)mV
SOFT
STOP
SS1 > 2.2V
VSEC
CLAMP
TIMING
LOGIC
S
R
Q
S
Q
SS1 < 1.25V
TJ > 170°C
INTVCC_OV
INTVCC_UV
R
+
–
+
–
+
–
+
–
28
INTVCC 26
AOUT
OFF
ON
96mV
OFF
FG CG
ON
ACTIVE CLAMP CONTROL
SYNCHRONOUS CONTROL
MAIN SWITCH
32
SOUT 30
OUT 24
OC 22
ISENSEP 21
ISENSEN
3753 BD
20
EA
BLANK
ISLP
HICCUP
CONTROL
LT3753
12
Rev. C
For more information www.analog.com
TIMING DIAGRAMS
Figure 1. Timing Diagram
Figure 2. Timing Reference Circuit
tOA
tAO
tSO
tAS tOS
0V
AOUT
OUT
SWP
SOUT
CG
FG
FSW
CSW
T
(1/fOSC)
tAO PROGRAMMED BY RTAO, tAS PROGRAMMED BY RTAS
tOS PROGRAMMED BY RTOS, tOA = 0.9 • tAO, tSO = tAO – tAS
0V
0V
0V
0V
0V
VOUT/(1 – DUTY CYCLE)
VIN/(1 – DUTY CYCLE)
0V
0V
3753 F01
VIN
TAO TAS
AOUT
M1 M4FG CG
SYNC
M3
SWP
LTXXXX
CSW
FSW
GND
SOUT
• •
• •
M2
–VIN
VIN
–VOUT
3753 F02
VOUT
LT3753
OUT
TOS
LT3753
13
Rev. C
For more information www.analog.com
TIMING DIAGRAMS
Figure 3. Start-Up and Shutdown Timing Diagram
SYSTEM INPUT (MIN)
+VHYST
1.25V
10V(REG)
2.6V
2.6V
2.6V
7V UVLO(+)
0V
0V
0V
0V
0V
0V
0Hz
150mV
1.25V
COMPLETED SOFT-STOP
SHUTDOWN:
0.6V < UVLO_VSEC < 1.25V
AND SS1 < 150mV
SS1
SOFT
STARTS
fOSC AND
DVSEC
SS2
SOFT
STARTS
COMP
SS1
SOFT
STOPS
fOSC, DVSEC
AND COMP
SYSTEM INPUT (MIN)SYSTEM INPUT
(VIN PIN)
UVLO_VSEC
(RESISTOR DIVIDER
FROM SYSTEM INPUT)
SS1
COMP
SS2
fOSC
(SWITCHING
FREQUENCY)
INTVCC
TRIGGER
SOFT STOP
COMP
SWITCHING
THRESHOLD
1.25V
FULL-SCALE fOSC
3753 F03
SWITCHING
FULL-SCALE fOSC/4
LT3753
14
Rev. C
For more information www.analog.com
OPERATION
Introduction
The LT3753 is a primary side, current mode, PWM control-
ler optimized for use in a synchronous forward converter
with active clamp reset. The LT3753 allows VIN pin opera-
tion between 8.5V and 100V. The LT3753 based forward
converter is targeted for power levels up to 400W and is
not intended for battery charger applications. For higher
power levels the converter outputs can be stacked in series.
Connecting UVLO_VSEC pins, OVLO pins, SS1 pins and
SS2 pins together allows blocks to react simultaneously
to all fault modes and conditions.
The IC contains an accurate programmable volt-second
clamp. When set above the natural duty cycle of the con-
verter, it provides a duty cycle guardrail to limit primary
switch reset voltage and prevent transformer saturation
during load transients. The accuracy and excellent line
regulation of the volt-second clamp provides VOUT regu-
lation for open-loop conditions such as no opto-coupler,
reference or error amplifier on the secondary side.
For applications not requiring isolation but requiring high
step-down ratios, each IC contains a voltage error ampli-
fier to allow a very simple nonisolated, fully regulated
synchronous forward converter.
A range of protection features include programmable
overcurrent (OC) hiccup mode, programmable system
input undervoltage lockout (UVLO), programmable
system input overvoltage lockout (OVLO) and built-in
thermal shutdown. Programmable slope compensation
and switching frequency allow the use of a wide range of
output inductor values and transformer sizes.
Part Start-Up
LT3753 start-up is best described by referring to the Block
Diagram and to the start-up waveforms in Figure3. For
part start-up, system input voltage must be high enough
to drive the UVLO_VSEC pin above 1.25V and the VIN pin
must be greater than 8.5V. An internal linear regulator is
activated and provides a 10V INTVCC supply for all gate
drivers. The SS1 pin of the forward controller is allowed
to start charging when INTVCC reaches its 7V UVLO(+)
threshold. When SS1 reaches 1.25V, the SS2 pin begins
to charge, controlling COMP pin rise and the soft-start of
output inductor peak current. The SS1 pin independently
soft starts switching frequency and a volt-second clamp
from 22% of their full-scale programmed values.
If secondary side control already exists for soft starting
the converter output voltage then the SS2 pin can still be
used to control initial inductor peak current rise. Simply
programming the primary side SS2 soft-start faster than
the secondary side allows the secondary side to take over.
If SS2 is not needed for soft-start control, its pull-down
strength and voltage rating also allow it to drive the input
of an opto-coupler connected to INTVCC. This allows
the option of communicating to the secondary side that
switching has begun.
LT3753
15
Rev. C
For more information www.analog.com
Figure 4. Programming Undervoltage Lockout (UVLO)
APPLICATIONS INFORMATION
Programming System Input Undervoltage Lockout
(UVLO) Threshold and Hysteresis
The LT3753 has an accurate 1.25V shutdown threshold
at the UVLO_VSEC pin. This threshold can be used in
conjunction with an external resistor divider to define
the falling undervoltage lockout threshold (UVLO(–)) for
the converter’s system input voltage (VS) (Figure 4). A
pin hysteresis current of 5µA allows programming of the
UVLO(+) threshold.
VS (UVLO(–)) [begin SOFT-STOP then shut down]
= 1.25 1+ R1
R2+R3
⎛
⎝
⎜⎞
⎠
⎟
⎡
⎣
⎢
⎤
⎦
⎥
VS (UVLO(+)) [begin SOFT-START]
= VS (UVLO(–)) + (5µA • R1)
It is important to note that the part enters soft-stop when
the UVLO_VSEC pin falls back below 1.25V. During soft-stop
the converter continues to switch as it folds back switching
frequency, volt-second clamp and COMP pin voltage. See
Soft-Stop in the Applications Information section. When
the SS2 pin is finally discharged below its 150mV reset
threshold the forward converter is shut down.
Soft-Stop Shutdown
Soft-stop shutdown (similar to system undervoltage) can
be commanded by an external control signal. A MOSFET
with a diode (or diodes) in series with the drain should be
used to pull down the UVLO_VSEC pin below 1.25V but not
below the micropower shutdown threshold of 0.6V(max).
Typical VIN quiescent current after soft-stop is 165µA.
Micropower Shutdown
If a micropower shutdown is required using an external
control signal, an open-drain transistor can be directly
connected to the UVLO_VSEC pin. The LT3753 has a
micropower shutdown threshold of typically 0.4V at the
UVLO_VSEC pin. VIN quiescent current in micropower
shutdown is 20µA.
Programming System Input Overvoltage Lockout
(OVLO) Threshold
The LT3753 has an accurate 1.25V overvoltage shutdown
threshold at the OVLO pin. This threshold can be used in
conjunction with an external resistor divider to define the
rising overvoltage lockout threshold (OVLO(+)) for the
converter’s system input voltage (VS) (Figure 5). When
OVLO(+) is reached, the part stops switching immediately
and a hard stop discharges the SS1 and SS2 pins. The
falling threshold OVLO(–) is fixed internally at 1.215V and
allows the part to restart in soft-start mode. A single resis-
tor divider can be used from system input supply (VS) to
define both the undervoltage and overvoltage thresholds
for the system. Minimum value for R3 is 1k. If OVLO is
unused, place a 10k resistor from OVLO pin to ground.
VS OVLO(+) [stop switching; HARD STOP]
= 1.25 1+ R1+R2
R3
⎛
⎝
⎜⎞
⎠
⎟
⎡
⎣
⎢
⎤
⎦
⎥
VS OVLO(–) [begin SOFT-START]
= VSOVLO +
( )
•
1.215
1.25
1.250V
3753 F04
R1
R2
TO
OVLO PIN
R3
SYSTEM
INPUT (VS)
UVLO_VSEC
LT3753
5µA
–
+
LT3753
16
Rev. C
For more information www.analog.com
APPLICATIONS INFORMATION
Figure 5. Programming Overvoltage Lockout (OVLO)
Programming Switching Frequency
The switching frequency for the LT3753 is programmed
using a resistor, RT, connected from analog ground (Pin
18) to the RT pin. Table 1 shows typical fOSC vs RT resistor
values. The value for RT is given by:
RT = 8.39 • X • (1 + Y)
where,
X = (109/fOSC) – 365
Y = (300kHz – fOSC)/107 (fOSC < 300kHz)
Y = (fOSC – 300kHz)/107 (fOSC > 300kHz)
Example: For fOSC = 200kHz,
RT = 8.39 • 4635 • (1 + 0.01) = 39.28k (choose 39.2k)
The LT3753 includes frequency foldback at start-up (see
Figure 3). In order to make sure that a SYNC input does
not override frequency foldback during start-up, the SYNC
function is ignored until SS1 pin reaches 2.2V.
Table 1. RT vs Switching Frequency (fOSC)
SWITCHING FREQUENCY (kHz) RT (kΩ)
100 82.5
150 53.6
200 39.2
250 30.9
300 24.9
350 21
400 18.2
450 15.8
500 14
Synchronizing to an External Clock
The LT3753 internal oscillator can be synchronized to
an external clock at the SYNC pin. SYNC pin high level
should exceed 1.8V for at least 100ns and SYNC pin
low level should fall below 0.6V for at least 100ns. The
SYNC pin frequency should be set equal to or higher
than the typical frequency programmed by the RT pin.
An fSYNC/fOSC ratio of x (1.0 < x < 1.25) will reduce the
externally programmed slope compensation by a factor
of 1.2x. If required, the external resistor RISLP can be
reprogrammed higher by a factor of 1.2x. (see Current
Sensing and Programmable Slope Compensation).
The part injection locks the internal oscillator to every ris-
ing edge of the SYNC pin. If the SYNC input is removed
at any time during normal operation the part will simply
change switching frequency back to the oscillator frequency
programmed by the RT resistor. This injection lock method
avoids the possible issues from a PLL method which can
potentially cause a large drop in frequency if SYNC input
is removed.
During soft-start the SYNC input is ignored until SS1 ex-
ceeds 2.2V. During soft-stop the SYNC input is completely
ignored. If the SYNC input is to be used, recall that the
programmable duty cycle clamp DVSEC is dependent on the
switching frequency of the part (see section Programming
Duty Cycle Clamp). RIVSEC should be reprogrammed by
1/x for an fSYNC/fOSC ratio of x.
INTVCC Regulator Bypassing and Operation
The INTVCC pin is the output of an internal linear regulator
driven from VIN and provides a 10V supply for onboard gate
drivers AOUT, SOUT and OUT. INTVCC should be bypassed
with a 4.7µF low ESR, X7R or X5R ceramic capacitor to
power ground to ensure stability and to provide enough
charge for the gate drivers.
The INTVCC regulator has a minimum 19mA output cur-
rent limit. This current limit should be considered when
choosing the switching frequency and capacitance loading
on each gate driver. Average current load on the INTVCC
pin for a single gate driver driving an external MOSFET
is given as :
IINTVCC = fOSC • QG
1.250V(+)
1.215V(–)
3753 F05
R1
R2 OVLO
TO
UVLO_VSEC
PIN
R3
SYSTEM
INPUT (VS)LT3753
OVLO –
+
LT3753
17
Rev. C
For more information www.analog.com
APPLICATIONS INFORMATION
where:
fOSC = controller switching frequency
QG = gate charge (VGS = INTVCC)
While the INTVCC 19mA output current limit is sufficient
for LT3753 applications, efficiency and internal power
dissipation should also be considered. INTVCC can be
externally overdriven by an auxiliary supply (see Gener-
ating Auxiliary Supplies in the Applications Information
section) to improve efficiency, remove power dissipation
from within the IC and provide more than 19mA output
current capability. Any overdrive level should exceed the
regulated INTVCC level but not exceed 16V.
In the case of a short-circuit fault from INTVCC to ground,
the IC reduces the INTVCC output current limit to typically
13mA. The INTVCC regulator has an undervoltage lockout
rising threshold, UVLO(+), which prevents gate driver
switching until INTVCC reaches 7V and maintains switch-
ing until INTVCC falls below a UVLO(–) threshold of 6.8V.
For VIN levels close to or below the INTVCC regulated level,
the INTVCC linear regulator may enter dropout. The result-
ing lower INTVCC level will still allow gate driver switching
as long as INTVCC remains above INTVCC UVLO(–) levels.
See the Typical Performance Characteristics section for
INTVCC performance vs VIN and load current.
Adaptive Leading Edge Blanking Plus Programmable
Extended Blanking
The LT3753 provides a ±2A gate driver at the OUT pin to
control an external N-channel MOSFET for main power
delivery in the forward converter (Figure 7). During gate
rise time and sometime thereafter, noise can be generated
in the current sensing resistor connected to the source of
the MOSFET. This noise can potentially cause a false trip of
sensing comparators resulting in early switch turn off and
in some cases re-soft-start of the system. To prevent this,
LT3753 provides adaptive leading edge blanking of both
OC and ISENSEP signals to allow a wide range of MOSFET
QG ratings. In addition, a resistor RTBLNK connected from
TBLNK pin to analog ground (Pin18) programs an extended
blanking duration (Figure 6).
Adaptive leading edge blanking occurs from the start of
OUT rise and completes when OUT reaches within 1V of
its maximum level. An extended blanking then occurs
which is programmable using the RTBLNK resistor given by:
tBLNK = 50ns + 2.2ns
k• RTBLNK
⎛
⎝
⎜⎞
⎠
⎟,
7.32k < RTBLNK < 249k
Adaptive leading edge blanking minimizes the value re-
quired for RTBLNK. Increasing RTBLNK further than required
increases M1 minimum on time (Figure 7).
In addition, the critical volt-second clamp (DVSEC) is not
blanked. Therefore, if DVSEC decreases far enough (in soft
start foldback and at maximum input voltage) M1 may turn
off before blanking has completed. Since OC and ISENSEP
signals are only seen when M1 is on (and after blanking
has completed), RTBLNK value should be limited by:
(2.2ns/k)RTBLNK < TVSEC(MIN) – tADAPTIVE – 50ns
(ADAPTIVE)
LEADING
EDGE
BLANKING
(PROGRAMMABLE)
EXTENDED
BLANKING
7.32k ≤ RTBLNK ≤ 249k
tBLNK = 50ns + (2.2ns • RTBLNK)
CURRENT
SENSE
DELAY
220ns
k
3753 F06
OUT
Figure 6. Adaptive Leading Edge Blanking Plus
Programmable Extended Blanking
VIN
VIN
INTVCC
VOUT
M1
RSENSE
3753 F07
RISLP
••
LTC3753
INTVCC
COMP
OUT
OC
ISENSEP
FROM
REGULATION
LOOP
ISENSEN
GND
Figure 7. Current Sensing and Programmable Slope
Compensation
LT3753
18
Rev. C
For more information www.analog.com
APPLICATIONS INFORMATION
where,
TVSEC(MIN) = 109(DVSEC (MAX) /(fold.fosc))
• (Input(MIN)/Input(MAX))
fold = fOSC and DVSEC foldback ratio (for OUT pin)
tADAPTIVE = OUT pin rise time to INTVCC – 1V
Example: For Figure 22 circuit, DVSEC(MAX) = 0.77,
Input(MIN)/(MAX) = 17.4V/74V, fold = 4, tADAPTIVE = 23ns
and fOSC = 240kHz,
TVSEC(MIN) = 109(0.77/(4 • 2.4 • 105)) • 17.4/74 = 188ns
(2.2ns/1k)RTBLNK < 188 – 23 – 50
RTBLNK < 52.5k (Actual Circuit Uses 34k)
Current Sensing and Programmable Slope
Compensation
The LT3753 commands cycle-by-cycle peak current in
the external switch and primary winding of the forward
transformer by sensing voltage across a resistor connected
in the source of the external n-channel MOSFET (Figure 7).
The sense voltage across RSENSE is compared to a sense
threshold at the ISENSEP pin, controlled by COMP pin level.
Two sense inputs, ISENSEP and ISENSEN, are provided to
allow a Kelvin connection to RSENSE. For operation in con-
tinuous mode and above 50% duty cycle, required slope
compensation can be programmed by adding a resistor,
RISLP, in series with the ISENSEP pin. A ramped current
always flows out of the ISENSE pin. The current starts from
2µA at 0% duty cycle and linearly ramps to 33µA at 80%
duty cycle. A good starting value for RISLP is 1.5kΩ which
gives a 41mV total drop in current comparator threshold
at 65% duty cycle.
The COMP pin commands an ISENSEP threshold between
0mV and 220mV. The 220mV allows a large slope com-
pensation voltage drop to exist in RISLP without effecting
the programming of RSENSE to set maximum operational
currents in M1. An fSYNC/fOSC ratio of x (1.0 < x < 1.25)
will reduce the externally programmed slope compensa-
tion by a factor of 1.2x. If required, the external resistor
RISLP can be reprogrammed higher by a factor of 1.2x.
Overcurrent: Hiccup Mode
The LT3753 uses a precise 96mV sense threshold at the
OC pin to detect excessive peak switch current (Figure 7).
During an overload condition switching stops imme-
diately and the SS1/SS2 pins are rapidly discharged.
The absence of switching reduces the sense voltage
at the OC pin, allowing SS1/SS2 pins to recharge and
eventually attempt switching again. The part exists in
this hiccup mode as long as the overcurrent condition
exists. This protects the converter and reduces power
dissipation in the components (see Hard Stop in the
Applications Information section). The 96mV peak switch
current threshold is independent of the voltage drop in
RISLP used for slope compensation.
Output DC load current to trigger hiccup mode:
= I
LOAD(OVERCURRENT)
=NP
NS
•96mV
RISENSE
⎛
⎝
⎜
⎞
⎠
⎟– 1/2 IRIPPLE(P-P)
( )
where:
NP = forward transformer primary turns
NS = forward transformer secondary turns
IRIPPLE(P-P) = Output inductor peak-to-peak ripple
current
RISENSE should be programmed to allow maximum DC load
current for the application plus enough margin during load
transients to avoid overcurrent hiccup mode.
Programming Maximum Duty Cycle Clamp: DVSEC
(Volt-Second Clamp)
Unlike other converters which only provide a fixed
maximum duty cycle clamp, the LT3753 provides an
accurate programmable maximum duty cycle clamp
(DVSEC) on the OUT pin which moves inversely with
system input. DVSEC provides a duty cycle guardrail
to limit the volt-seconds-on product over the entire
LT3753
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natural duty cycle range (Figures 8 and 9). This limits the
drain voltage required for complete transformer reset.
A resistor RIVSEC from the IVSEC pin to analog ground
(Pin 18) programs DVSEC.
DVSEC (OUT pin duty cycle clamp)
= 0.725 •
R
IVSEC
51.1k •
f
OSC
300 •
1.25
UVLO_V
SEC
where:
RIVSEC = programming resistor at IVSEC pin
fOSC = switching frequency (kHz)
UVLO_VSEC = resistor divided system input voltage
RIVSEC can program any DVSEC required at minimum
system input. DVSEC will then follow natural duty cycle
as VIN varies. Maximum programmable DVSEC is typi-
cally 0.75 but may be further limited by the transformer
design and voltage ratings of components connected to
the drain of the primary side power MOSFET (SWP). See
voltage calculations in the LO side and HI side active clamp
topologies sections.
If system input voltage falls below it's UVLO threshold
the part will enter soft-stop with continued switching. The
LT3753 includes an intelligent circuit which prevents DVSEC
from continuing to rise as system input voltage falls (see
Soft-Stop). Without this, too large a DVSEC would require
extremely high reset voltages on the SWP node to prop-
erly reset the transformer. The UVLO_VSEC pin maximum
operational level is the lesser of VIN – 2V or 12.5V.
The LT3753 volt-second clamp architecture is superior
to an external RC network connected from system input
to trip an internal comparator threshold. The RC method
suffers from external capacitor error, part-to-part mismatch
between the RC time constant and the IC’s switching
period, the error of the internal comparator threshold
and the nonlinearity of charging at low input voltages.
The LT3753 uses the RIVSEC resistor to define the charge
current for an internal timer capacitor to set an OUT pin
maximum on-time, tON(VSEC). The voltage across RIVSEC
follows UVLO_VSEC pin voltage (divided down from system
input voltage). Hence, RIVSEC current varies linearly with
input supply. The LT3753 also trims out internal timing
capacitor and comparator threshold errors to optimize
part-to-part matching between tON(VSEC) and T.
DVSEC Open Loop Control: No Opto-Coupler, Error
Amplifier or Reference
The accuracy of the programmable volt-second clamp
(DVSEC) safely controls VOUT if open loop conditions exist
such as no opto-coupler, error amplifier or reference on the
secondary side. DVSEC controls the output of the converter
by controlling duty cycle inversely proportional to system
input. If DVSEC duty cycle guardrail is programmed X%
above natural duty cycle, VOUT will only increase by X%
if a closed loop system breaks open. This volt-second
clamp is operational over a 10:1 system input voltage
range. See DVSEC versus UVLO_VSEC pin voltage in the
Typical Performance Characteristics section.
RIVSEC: Open Pin Detection Provides Safety
The LT3753 provides an open-detection safety feature
for the RIVSEC pin. If the RIVSEC resistor goes open circuit
the part immediately stops switching. This prevents the
part from running without the volt-second clamp in place.
tON_VSEC
tON
OUT
t
D = tON/t
3753 F08
(PROGRAMMED
BY RIVSEC)
DVSEC = tON_VSEC/t
DVSEC = “DUTY CYCLE GUARDRAIL”
3753 F09
R1
R2
UVLO_VSEC
TO
OVLO
PIN
R3
RIVSEC
SYSTEM
INPUT
LT3753
IVSEC RT
RT
Figure 8. Volt-Second (DVSEC) Clamp
Figure 9. Programming DVSEC
LT3753
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Transformer Reset: Active Clamp Technique
The LT3753 includes a ±0.4A gate driver at the AOUT
pin to allow the use of an active clamp transformer reset
technique (Figures 10, 14). The active clamp method
improves efficiency and reduces voltage stress on the
main power switch, M1. By switching in the active clamp
capacitor only when needed, the capacitor does not lose
its charge during M1 on-time. By allowing the active clamp
capacitor, CCL, to store the average voltage required to
reset the transformer, the main power switch sees lower
drain voltage.
In addition, the active clamp drain waveform on M1
(Figure 11) allows a self-driven architecture, whereby
the drains of M3 and M4 drive the gates of M4 and M3
respectively, removing the need for a secondary-side
synchronous MOSFET driver (Figure 21). In a self-driven
architecture, the reset voltage level on M1, VOUT level
and duty cycle range (governed by system input range)
must be considered to ensure the maximum VGS rating of
synchronous MOSFETs M3, M4 are not exceeded.
An imbalance of volt-seconds will cause magnetizing cur-
rent to walk upwards or downwards until the active clamp
capacitor is charged to the optimal voltage for proper
transformer reset. The voltage rating of the capacitor will
depend on whether the active clamp capacitor is actively
switched to ground (Figure 10) or actively switched to
system input (Figure 14). In an active clamp reset topol-
ogy, volt-second balance requires:
VIN • D = (SWP – VIN) • (1 – D)
where:
VIN = Transformer input supply
D = (VOUT/VIN) • N = switch M1 duty cycle
VOUT = Output voltage (including the voltage drop
contribution of M4 catch diode during M1 off)
N = Transformer turns ratio = NP/NS
SWP = M1 drain voltage
LO Side Active Clamp Topology (LT3753)
The steady-state active clamp capacitor voltage, VCCL,
required to reset the transformer in a LO side active clamp
topology (Figure 10) can be approximated as the drain-to-
source voltage (VDS) of switch M1, given by:
VCCL (LO side):
(a) Steady state: VCCL = SWP = VDS
=1
1– D
⎛
⎝
⎜⎞
⎠
⎟• VIN =VIN2
VIN – VOUT • N
( )
( )
(b) Transient:
During load transients, duty cycle and hence VCCL may
increase. Replace D with DVSEC in the equation above to
calculate transient VCCL values. See the previous section
Programming Duty Cycle Clamp–DVSEC. The DVSEC guard-
rail can be programmed as close as 5% higher than D but
may require a larger margin to improve transient response.
Figure 10. LO Side Active Clamp Topology
CCL
LLEAK
LLEAK
LMAG
FSW
CSW
• •
VD
D1R1
C1
M2 M4M3
M1
SWP
OUT
VIN
–VIN
VOUT
–VOUT
AOUT
LT3753
FG
LTXXXX
CG
3753 F10
LT3753
21
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As shown in Figure 12, the maximum steady-state value
for VCCL may occur at minimum or maximum input volt-
age. Hence VCCL should be calculated at both input voltage
levels and the largest of the two calculations used. M1
drain should be rated for a voltage greater than the above
steady-state VDS calculation due to tolerances in duty
cycle, load transients, voltage ripple on CCL and leakage
inductance spikes. CCL should be rated higher due to the
effect of voltage coefficient on capacitance value. A typical
choice for CCL is a good quality X7R capacitor. M2 should
have a VDS rating greater than VCCL since the bottom plate
of CCL is –VCCL during M1 on and M2 off. For high input
voltage applications, the limited VDS rating of available
P-channel MOSFETs might require changing from a LO
side to HI side active clamp topology.
For the lo side active clamp topology in steady state, during
M1 on time, magnetizing current (IMAG) increases from a
negative value to a positive value (Figure 11). When M1
turns off, magnetizing current charges SWP until it reaches
VCCL plus the voltage drop of the M2 body diode. At this
Figure 12. LO Side VCCL vs Duty Cycle
(Normalized to 50% Duty Cycle)
Figure 11. Active Clamp Reset: Magnetizing
Current and M1 Drain Voltage
20µs/DIV
IMAG
1A/DIV
SWP
50V/DIV
3753 F11
DUTY CYCLE (%)
20
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9 50 70
3753 F12
30 40 60 80
ACTIVE CLAMP CAPACITOR VOLTAGE
NORMALIZED TO 50% DUTY CYCLE
LO SIDE ACTIVE CLAMP TOPOLOGY
Figure 13. HI Side VCCL vs Duty Cycle
(Normalized to 50% Duty Cycle)
Figure 14. HI Side Active Clamp Topology (Using LT3752-1)
DUTY CYCLE (%)
20
ACTIVE CLAMP CAPACITOR VOLTAGE
NORMALIZED TO 50% DUTY CYCLE
1.5
3753 F13
1.0
0.5 40 60
30 50 70
2.0
2.5
1.3
0.8
1.8
2.3
80
HI SIDE ACTIVE CLAMP TOPOLOGY
CCL
LLEAK
LLEAK
SWP
LMAG
FSW
CSW
• •
• • VD
D1
–VIN
C2
T4
C1
M2
M4
M1
M3
R1
OUT
VIN
–VIN
VOUT
–VOUT
AOUT
LT3752-1
FG
LTXXXX
CG
3753 F14
LT3753
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moment the active clamp capacitor is passively switched
in to ground (due to the forward conduction of M2 body
diode) and the drain voltage increases at a slower rate
due to the loading of CCL. SWP above VIN causes IMAG
to reduce from a positive value towards zero (dVSWP/dT
= 0). As IMAG becomes negative it begins to discharge
the SWP node. Switching in M2 before IMAG reverses,
actively connects the bottom plate of CCL to ground and
allows SWP to be discharged slowly. The resulting SWP
waveform during M1 off-time appears as a square wave
with a superimposed sinusoidal peak representing ripple
voltage on CCL.
The switch M2 experiences near zero voltage switching
(ZVS) since only the body diode voltage drop appears
across it at switch turn on.
HI Side Active Clamp Topology (LT3752-1)
For high input voltage applications the VDS rating of avail-
able P-channel MOSFETs might not be high enough to
be used as the active clamp switch in the LO side active
clamp topology (Figure 10). An N-channel approach using
the HI side active clamp topology (Figure 14) should be
used. (The LT3752-1 is ideal for the HI side active clamp
topology). This topology requires a gate drive transformer
or a simple gate drive opto-coupler to drive the N-channel
MOSFET (M2) for switching in the active clamp capacitor
from SWP to VIN. The M1 drain voltage calculation is the
same as in the LO side active clamp case and M1 should
be rated in a similar manner. The voltage across the clamp
capacitor in the HI side architecture, however, is lower by
VIN since it is referenced to VIN.
The steady-state active clamp capacitor voltage VCCL to
reset the transformer in a HI side active clamp topology
can be approximated by:
VCCL (HI side):
(a) Steady state: VCCL = VRESET = VDS – VIN
=D
1– D
⎛
⎝
⎜⎞
⎠
⎟• VIN = VIN • VOUT •N
VIN – V
OUT
• N
( )
(b) Transient:
During load transients, duty cycle and hence VCCL may
increase. Replace D with DVSEC in the equation above to
calculate transient VCCL values. DVSEC guardrail can be
programmed as close as 6% higher than D but may require
a larger margin to improve transient response. See the
previous section Programming Duty Cycle Clamp–DVSEC.
CCL should be rated for a voltage higher than the above
steady-state calculation due to tolerances in duty cycle,
load transients, voltage ripple on CCL and the effect of
voltage coefficient on capacitance value. A typical choice
for CCL is a good quality (X7R) capacitor. When using a
gate drive transformer to provide control of the active
clamp switch (M2), the external components C1, C2, R1,
D1 and T4 are required. T4 size will increase for lower
programmed switching frequencies due to a minimum
volt-second requirement. Alternatively, a simple gate driver
opto-coupler can be used as a switch to control M2, for a
smaller solution size.
Active Clamp Capacitor Value and Voltage Ripple
The active clamp capacitor value should be chosen based
on the amount of voltage ripple which can be tolerated
by components attached to SWP. Lower CCL values will
create larger voltage ripple (increased drain voltage for the
primary side power MOSFET) but will require less swing
in magnetizing current to move the active clamp capacitor
during duty cycle changes. Choosing too high a value for
the active clamp capacitor (beyond what is needed to keep
ripple voltage to an acceptable level) will require unneces-
sary additional flux swing during transient conditions. For
systems with flux swing detection, too high a value for the
active clamp capacitor will trigger the detection system
early and degrade transient response.
Another factor to consider is the resonance between CCL and
the magnetizing inductance (LMAG) of the main transformer.
An RC snubber (RS, CS) in parallel with CCL will dampen
LT3753
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the sinusoidal ringing and limit the peak voltages at the
primary side MOSFET drain during input/load transients.
Check circuit performance to determine if the snubber
is required. Component values can be approximated as:
CCL (active clamp capacitance) = 10
L
MAG
•(1– DMIN)
2 • π • f
OSC
⎛
⎝
⎜⎞
⎠
⎟
2
where,
DMIN = (VOUT/VIN(MAX)) • NP/NS
and (if needed),
CS (snubber capacitance) = 6 • CCL
RS (snubber resistance) = (1/(1-DMAX)) • √(LMAG/CCL)
where,
DMAX = ( VOUT/VIN(MIN)) • NP/NS
Check the voltage ripple on SWP during steady-state
operation.
CCL voltage ripple can be estimated as:
VCCL(RIPPLE) = VCCL • (1-D)2/(8 • CCL • LMAG • fOSC2)
where,
D = (VOUT/VIN) • (NP/NS)
VCCL = VIN/(1-D) (Lo side active clamp topology)
VCCL = D • VIN/(1-D) (Hi side active clamp topology)
Example : For VIN = 36V, VOUT = 12V, NP/NS = 2, VCCL =
108V (Lo side active clamp topology), CCL = 22nF, LMAG
= 100µH, fOSC = 250kHz, VCCL(RIPPLE) = 108(0.33)2/(8(22
• 10–9)(10–4)(2.5 • 105)2) = 10.7V
The transformer is typically chosen to operate at a maximum
flux density that is low enough to avoid excessive core
losses. This also allows enough headroom during input
and load transients to move the active clamp capacitor at
a fast enough rate to keep up with duty cycle changes.
Active Clamp MOSFET Selection
The selection of active clamp MOSFET is determined by
the maximum levels expected for the drain voltage and
drain current. The active clamp switch (M2) in a either a lo
side or hi side active clamp topology has the same BVdss
requirements as the main N-channel power MOSFET. The
current requirements are divided into two categories :
(A) Drain Current
This is typically less than the main N-channel power
MOSFET because the active clamp MOSFET sees only
magnetizing current, estimated as :
Peak IMAG (steady state) = (1/2) • (NP/NS) • (VOUT/
LMAG) • (1/fOSC)
where,
LMAG = main transformer’s magnetizing inductance
Example (LT3752) : For VOUT =12V, NP/NS = 2, fOSC =
250kHz and LMAG = 100µH, Peak IMAG = 0.48A.
This value should be doubled for safety margin due to
variations in LMAG, fOSC and transient conditions.
(B) Body Diode Current
The body diode will see reflected output current as a pulse
every time the main N-channel power MOSFET turns off.
This is due to residual energy stored in the transformer's
leakage inductance. The body diode of the active clamp
MOSFET should be rated to withstand a forward pulsed
current of:
ID(MAX) = (NS/NP) (IOUT(MAX) + (IL(RIPPLE)(P-P)/2))
where,
IL(RIPPLE)(P-P) = output inductor ripple current = (VOUT/
(LOUT • fOSC)) • (1–(VOUT/VIN)(NP/NS))
IOUT(MAX) = maximum output load current
LT3753
24
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Programming Active Clamp Switch Timing: AOUT to
OUT (tAO) and OUT to AOUT (tOA) Delays
The timings tAO and tOA represent the delays between AOUT
and OUT edges (Figures 1 and 2) and are programmed
by a single resistor, RTAO, connected from analog ground
(Pin 18) to the TAO pin. Once tAO is programmed for the
reasons given below, tOA will be automatically generated.
Front-end timing tAO (M2 off, M1 on)
= AOUT(edge)-to-OUT(rising)
= 50ns + 3.8ns • RTAO
1k
⎛
⎝
⎜⎞
⎠
⎟,14.7 < RTAO < 125k
In order to minimize turn-on transition loss in M1 the drain
of M1 should be as low as possible before M1 turns on.
To achieve this, AOUT should turn M2 off a delay of tAO
before OUT turns M1 on. This allows the main transformer’s
magnetizing current to discharge M1 drain voltage quickly
towards VIN before M1 turns on.
As SWP falls below VIN, however, the rectifying diodes on
the secondary side are typically active and clamp the SWP
node close to VIN. If enough leakage inductance exists,
however, the clamping action on SWP by the secondary
side will be delayed—potentially allowing the drain of
M1 to be fully discharged to ground just before M1 turns
on. Even with this delay due to the leakage inductance,
LMAG needs to be low enough to allow IMAG to be negative
enough to slew SWP down to ground before M1 turns on.
If achievable, M1 will experience zero voltage switching
(ZVS) for highest efficiency. As will be seen in a later sec-
tion entitled Primary-Side Power MOSFET Selection, M1
transition loss is a significant contributor to M1 losses.
Back-end timing tOA (M1 off, M2 on) is automatically
generated
= OUT(falling)-to-AOUT(edge) = 0.9 • tAO
tOA should be checked to ensure M2 is not turned on until
M1 and M3 are turned off.
Programming Synchronous Rectifier Timing: SOUT to
OUT (tSO) and OUT to SOUT (tOS) Delays
The LT3753 includes a ±0.4A gate driver at the SOUT pin
to send a control signal via a pulse transformer to the
secondary side of the forward converter for synchronous
rectification (see Figures 1 and 2). For the highest efficiency,
M4 should be turned on whenever M1 is turned off. This
suggests that SOUT should be a non-overlapping signal
with OUT with very small non-overlap times. Inherent tim-
ing delays, however, which can vary from application to
application, can exist between OUT to CSW and between
SOUT to CG. Possible shoot-through can occur if both M1
and M4 are on at the same time, resulting in transformer
and/or switch damage.
Front-end timing: tSO (M4 off, M1 on)
= SOUT(falling)-to-OUT(rising) delay
= tSO = tAO – tAS
= 3.8ns • (RTAS – RTAO)
where:
tAS = 50ns + (3.8ns • RTAS/1k) , 14.7k < RTAS < 125k,
tAO = 50ns + (3.8ns • RTAO/1k), 14.7k < RTAO < 125k,
tSO is defined by resistors RTAS and RTAO connected from
analog ground (Pin 18) to their respective pins TAS and
TAO. Each of these resistor defines a delay referenced
to the AOUT edge at the start of each cycle. RTAO was
already programmed based on requirements defined in
the previous section Programming AOUT to OUT Delay.
RTAS is then programmed as a delay from AOUT to SOUT
to fulfill the equation above for tSO. By choosing RTAS less
than or greater than RTAO, the delay between SOUT falling
and OUT rising can be programmed as positive or nega-
tive. While a positive delay can always be programmed
for tSO, the ability to program a negative delay allows for
improved efficiency if OUT(rising)-to-CSW(rising) delay
is larger than SOUT(falling)-to-CG(rising) delay.
Back-end timing: tOS (M1 off, M4 on)
= OUT (falling)-to-SOUT (rising) delay
= tOS = 35ns + (2.2ns • RTOS/1k), 7.32k < RTOS < 249k
LT3753
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The timing resistor, RTOS, defines the OUT (falling)-to-
SOUT (rising) delay. This pin allows programming of a
positive delay, for applications which might have a large
inherent delay from OUT fall to SW2 fall.
Soft-Start (SS1, SS2)
The LT3753 uses SS1 and SS2 pins for soft starting
various parameters (Figures 3 and 15). SS1 soft starts
internal oscillator frequency and DVSEC (maximum duty
cycle clamp). SS2 soft starts COMP pin voltage to control
output inductor peak current. Using separate SS1 and SS2
pins allows the soft-start ramp of oscillator frequency and
DVSEC to be independent of COMP pin soft-start. Typically
SS1 capacitor (CSS1) is chosen as 0.47µF and SS2 capaci-
tor (CSS2) is chosen as 0.1µF. Soft-start charge currents
are 11.5µA for SS1 and 21µA for SS2.
SS1 is allowed to start charging (soft-start) if all of the
following conditions exist (typical values) :
(1) UVLO_VSEC > 1.25V: System input not in UVLO
(2) OVLO < 1.215V: System input not in OVLO
(3) OC < 96mV: No over current condition
(4) 7V < INTVCC < 16V: INTVCC valid
(5) TJ < 165°C: Junction temperature valid
(6) VIN > 7.75V: VIN pin valid
SS1 = 0V to 1.25V (no switching). This is the SS1 range
for no switching for the forward converter. SS2 = 0V.
SS1 > 1.25V allows SS2 to begin charging from 0V.
SS1 = 1.25V to 2.45V (soft-start fOSC, DVSEC). This is the
SS1 range for soft-starting fOSC and DVSEC folded back
from 22% to 100% of their programmed levels. Fold back
of fOSC and DVSEC reduces effective minimum duty cycle
for the primary side MOSFET. This allows inductor current
to be controlled at low output voltages during start-up.
SS1 ramp rate is chosen slow enough to ensure fOSC and
DVSEC foldback lasts long enough for the converter to take
control of inductor current at low output voltages. In ad-
dition, slower SS1 ramp rate increases the non-switching
period during an output short to ground fault (over current
hiccup mode) to reduce average power dissipation (see
Hard-Stop).
SS2 = 0V to 1.6V (soft-start COMP pin). This is the SS2
range for soft-starting COMP pin from approximately 1V
to 2.6V.
SS2 ramp rate is chosen fast enough to allow a (slower)
soft-start control of COMP pin from a secondary side
opto-coupler controller.
SS1 soft-start non-switching period (0V to 1.25V)
= 1.25V • CSS1/11.5µA
SS1 soft-start fOSC, DVSEC period (1.25V to 2.45V)
= 1.2V • CSS1/11.5µA
SS2 soft-start COMP period (0V to 1.6V) = 1.6V • CSS2/21µA
Soft-Stop (SS1)
The LT3753 gradually discharges the SS1 pin (soft-stop)
when a system input UVLO occurs or when an external
soft-stop shutdown command occurs (0.4V < UVLO_VSEC
< 1.25V). During SS1 soft-stop the converter continues
to switch, folding back fOSC, DVSEC and COMP pin voltage
(Figures 3 and 15). Soft-stop discharge current is 10.5µA
for SS1. Soft-stop provides:
(1) Active control of the secondary winding during output
discharge for clean shutdown in self-driven applications.
(2) Controlled discharge of the active clamp capacitor
to minimize magnetizing current swing during restart.
SS1: 2.45V to 1.25V (soft-stop fOSC, DVSEC, COMP). This
is the SS1 range for soft-stop folding back of:
(1) fOSC and DVSEC from 100% to 22% of their
programmed levels.
(2) COMP pin (100% to 0% of commanded peak
current).
SS1 soft-stop fOSC , DVSEC, COMP period (2.45V to 1.25V)
= 1.2V • CSS1/10.5µA
LT3753
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SS1 < 1.25V. Forward converter stops switching and SS2
pin is discharged to 0V using 2.8mA.
SS1 = 1.25V to 0V: When SS1 falls below 0.15V the internal
SS1 latch is reset. If all faults are removed, SS1 begins
charging again. If faults still remain, SS1 discharges to 0V.
SS1 soft-stop non-switching period (1.25V to 0V)
= 1.25V • CSS1/10.5µA
DVSEC rises as system input voltage falls in order to provide
a maximum duty cycle guardrail (volt-second clamp). When
system input falls below it's UVLO threshold, however,
this triggers a soft-stop with the converter continuing
to switch. It is important that DVSEC no longer increases
even though system input voltage may still be falling. The
LT3753 achieves an upper clamp on DVSEC by clamping
the minimum level for the IVSEC pin to 1.25V. As SS1 pin
discharges during soft-stop it folds back DVSEC. As DVSEC
falls below the natural duty cycle of the converter, the
converter loop follows DVSEC. If the system input voltage
rises (IVSEC pin rises) during soft-stop the volt-second
clamp circuit further reduces DVSEC. The I.C. chooses the
lowest DVSEC commanded by either the IVSEC pin or the
SS1 soft-stop function.
Hard-Stop (SS1, SS2)
Switching immediately stops and both SS1 and SS2 pins
are rapidly discharged (Figure 15. Hard-Stop) if any of the
following faults occur (typical values):
(1) UVLO_VSEC < 0.4V: Micropower shutdown
(2) OVLO > 1.250V: System input OVLO
(3) OC > 96mV: Over current condition
(4) INTVCC < 6.8V(UVLO), > 16.5V (OVLO)
(5) TJ > 170°C: Thermal shutdown
(6) VIN < 7.42: VIN pin UVLO
Figure 15. SS1, SS2 and COMP Pin Voltages During Faults, Soft-Start and Soft-Stop
COMP
RANGE
2.6V
2.6V
0V
0V
1.25V
0.15V
0.25V
COMP 1.25V
SWITCHING THRESHOLD
SS2 SOFT STARTS
COMP
0V 1V
COMP
SS2
SS1
2.6V
HARD
STOP
SOFT-START
(WHEN ALL CONDITIONS SATISFIED)
(1) UVLO_VSEC > 1.25V
(2) OVLO < 1.215V
(3) OC < 96mV
(4) 7V < INTVCC < 16V
(5) TJ < 165°C
(6) VIN > 7.75V
SOFT-STOP
(0.4V < UVLO_VSEC < 1.25)
(1) EXTERNAL SOFT-STOP SHUTDOWN
(2) SYSTEM INPUT UVLO
HARD STOP
(FAULTS)
(1) UVLO_VSEC < 0.4V
(2) OVLO > 1.25V
(3) OC > 96mV
(4) INTVCC < 6.8V, > 16.5V
(5) TJ > 170°C
(6) VIN < 7.42V
3753 F15
SS1 SOFT STOPS
fOSC, DVSEC AND COMP
SS1 SOFT STARTS
fOSC AND DVSEC
SS1 LATCH
RESET THRESHOLD
LT3753
27
Rev. C
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Switching stops immediately for any of the faults listed
above. When SS1 discharges below 0.15V it begins charg-
ing again if all faults have been removed. For an over cur-
rent fault triggered by OC > 96mV, the disable of switching
will cause the OC pin voltage to fall back below 96mV.
This will allow SS1 and SS2 to recharge and eventually
attempt switching again. If the over current condition still
exists, OC pin will exceed 96mV again and the discharge/
charge cycle of SS1 and SS2 will repeat in a hiccup mode.
The non-switching dead time period during hiccup mode
reduces the average power seen by the converter in an
over current fault condition. The dead time is dominated
by SS1 recharging from 0.15V to 1.25V.
Non-switching period in over current (hiccup mode):
= 1.1V • CSS1/11.5µA
OUT, AOUT, SOUT Pulse-Skipping Mode
During load steps, initial soft-start, end of soft-stop or
light load operation (if the forward converter is designed
to operate in DCM), the loop may require pulse skipping on
the OUT pin. This occurs when the COMP pin falls below
its switching threshold. If the COMP pin falls below it's
switching threshold while OUT is turned on, the LT3753
will immediately turn OUT off ; both AOUT and SOUT will
complete their normal signal timings referenced from
the OUT falling edge. If the COMP pin remains below it's
switching threshold at the start of the next switching cycle,
the LT3753 will skip the next OUT pulse and therefore
also skip AOUT and SOUT pulses. For AOUT control, this
prevents the active clamp capacitor from being accidentally
discharged during missing OUT pulses and/or causing
reverse saturation of the transformer. For SOUT control,
this prevents the secondary side synchronous rectifier
controller from incorrectly switching between forward FET
and synchronous FET conduction. The LT3753 correctly
re-establishes the required AOUT, SOUT control signals
if the OUT signal is required for the next cycle.
AOUT Timeout
During converter start-up in soft-start, the switching fre-
quency and maximum duty cycle clamp DVSEC are both
folded back. While this correctly reduces the effective
minimum on time of the OUT pin (to allow control of induc-
tor current for very low output voltages during start-up),
this means the AOUT pin on time duration can be large.
In order to ensure the active clamp switch controlled by
AOUT does not stay on too long, the LT3753 has an internal
15µs timeout to turn off the AOUT signal. This prevents
the active clamp capacitor from being connected across
the transformer primary winding long enough to create
reverse saturation.
Main Transformer Selection
The selection of the main transformer will depend on the
applications requirements : isolation voltage, power level,
maximum volt-seconds, turns ratio, component size, power
losses and switching frequency.
Transformer construction using the planar winding technol-
ogy is typically chosen for minimizing leakage inductance
and reducing component height. Transformer core type is
usually a ferrite material for high frequency applications.
Find a family of transformers that meet both the isolation
and power level requirements of the application. The next
step is to find a transformer within that family which is
suitable for the application. The subsequent thought pro-
cess for the transformer design will include :
(1) Secondary turns (NS), core losses, temperature
rise, flux density, switching frequency
(2) Primary turns (NP), maximum duty cycle and reset
voltages
(3) Copper losses
The expression for secondary turns (NS) is given by,
NS = 108 VOUT/(fOSC • AC • BM)
LT3753
28
Rev. C
For more information www.analog.com
where,
AC = cross-sectional area of the core in cm2
BM = maximum AC flux density desired
For flux density, choose a level which achieves an accept-
able level of core loss/temperature rise at a given switching
frequency. The transformer data sheet will provide curves
of core loss versus flux density at various switching fre-
quencies. The data sheet will also provide temperature rise
versus core loss. While choosing a value for BM to avoid
excessive core losses will usually allow enough headroom
for flux swing during input / load transients, still make
sure to stay well below the saturation flux density of the
transformer core. If needed, increasing NS will reduce flux
density. After calculating NS, the number of primary turns
(NP) can be calculated from,
NP = NS • DMAX VIN(MIN)/VOUT
where,
VIN(MIN) = minimum system input voltage
DMAX = maximum switch duty cycle at VIN(MIN) (typically
chosen between 0.6 and 0.7)
At minimum input voltage the converter will run at a maxi-
mum duty cycle DMAX. A higher transformer turns ratio
(NP/NS) will create a higher DMAX but it will also require
higher voltages at the drain of the primary side switch to
reset the transformer (see previous sections Lo side Active
Clamp Topology and Hi side Active Clamp Topology). DMAX
values are typically chosen between 0.6 and 0.7. Even for
a given DMAX value, the loop must also provide protection
against duty cycles that may excessively exceed DMAX
during transients or faults. While most converters only
provide a fixed duty cycle clamp, the LT3753 provides
a programmable maximum duty cycle clamp DVSEC that
also moves inversely with input voltage.
The resulting function is that of a programmable volt-
second clamp. This allows the user to choose a transformer
turns ratio for DMAX and then customize a maximum duty
cycle clamp DVSEC above DMAX for safety. DVSEC then
follows the natural duty cycle of the converter as a safety
guardrail (see previous section Programming Duty Cycle
Clamp).
After deciding on the particular transformer and turns ratio,
the copper losses can then be approximated by,
PCU = D • I(Load)(MAX)2 (RSEC + (NS/NP)2 RPRI)
where,
D = switch duty cycle (choose nominal 0.5)
I(Load)(MAX) = maximum load current
RPRI = primary winding resistance
RSEC = secondary winding resistance
If there is a large difference between the core losses and
the copper losses then the number of secondary turns
can be adjusted to achieve a more suitable balance. The
number of primary turns should then be recalculated to
maintain the desired turns ratio.
Generating Auxiliary Supplies
In many isolated forward converter applications, an aux-
iliary bias may be required for the primary-side circuitry
and/or the secondary-side circuitry. This bias is required
for various reasons: to limit voltages seen by an IC, to
improve efficiency, to remove power dissipation from
inside an IC and/or to power an IC before target output
voltage regulation is achieved ((eg) during VOUT start-up).
The best method for generating an auxiliary supply, that
is available even for VOUT = 0V, is to have a housekeeping
controller integrated into the primary-side IC (Figure 16).
This gives the highest efficiency, most cost effective
APPLICATIONS INFORMATION
Figure 16. LT3752 Forward Controller with Additional Integrated
Housekeeping Controller for Primary-Side and Secondary-Side Bias
VIN
RHISLP
RHSENSE
VIN VAUX2
SECONDARY-SIDE BIAS
VAUX1
PRIMARY-SIDE BIAS
(CONNECT TO INTVCC PIN)
3753 F16
•
•
•
LT3752
HOUT
HISENSE
HFBGND
R2 R1
LT3753
29
Rev. C
For more information www.analog.com
solution without the need for custom magnetics (limiting
selection) or the need for an additional flyback controller
IC. The LT3752 is a primary-side forward controller IC
with an integrated housekeeping controller and can be
easily substituted for the LT3753.
For isolated solutions without a housekeeping controller,
there are alternative methods for generating an auxiliary
supply for primary-side and secondary-side circuitry. Each
method, however, will have trade-offs from the recom-
mended housekeeping controller solution.
Primary-Side Auxiliary Supply
The LT3753 can operate without a primary-side auxiliary
supply since the VIN pin has a wide operational range. The
current required for all of the gate drivers (OUT, AOUT
and SOUT) is supplied by an internal linear regulator
connected between VIN and INTVCC. If the efficiency loss
and/or power dissipation and/or current drive capability
of that internal linear regulator is a limiting factor in the
forward converter design, then a primary-side bias (VAUX1)
can be generated to overdrive the INTVCC pin (Figure 17).
VAUX1 is generated using an extra winding (NAUX) from
the main power transformer in combination with an induc-
tor (L1) and two Schottky diodes (D1, D2) to generate a
buck-derived supply. A 1mH inductor will usually suffice
and should be chosen to handle the maximum supply
current required by INTVCC. See also the section INTVCC
Regulator Bypassing and Operation in the Applications
Information Section.
Secondary-Side Auxiliary Supply
There are various methods for generating an auxiliary
supply to power secondary-side circuitry. The LT8311
synchronous rectifier controller and opto coupler driver
IC can be powered in several ways including connection
directly to VOUT. While this is the easiest method, there are
various guidelines described in the LT8311 data sheet for
APPLICATIONS INFORMATION
VIN
VIN
LTC3753
INTVCC D2
D1
C1
NP
VAUX1
NAUX
OUT
OC
ISENSEP
ISENSEN
GND
3753 F17
••
L1
Figure 17. Primary-Side Bias VAUX1 (NAUX, L1, D1, D2)
LT3753
30
Rev. C
For more information www.analog.com
powering it’s VIN pin. In most cases a an auxiliary supply is
the best approach. The following methods can be used to
generate a bias (VAUX2) to power secondary-side circuitry :
(1) Use a primary-side forward controller with integrated
housekeeping controller to generate a secondary-side
bias (Figure 16).
(2) Use a buck-derived bias using an extra winding from
the main power transformer (similar method as
Figure 17, applied to secondary-side circuitry)
(3) Use a custom output inductor with overwinding
(Figure 18).
(4) Use a peak-charge circuit (Figures 19 (a), (b), (c)).
Whichever method is used to create the auxiliary supply
for secondary-side circuitry, the forward converter should
APPLICATIONS INFORMATION
Figure 18. Output Inductor with Overwinding Supply
Figure 19. Peak Charge Supply: (a) Directly from SW, (b) For Low VOUT Applications, (c) For High VOUT Applications
be tested to ensure the auxiliary supply is acceptable for
voltage range, supply current requirements and behavior
during converter power-up/down.
Primary-Side Power MOSFET Selection
The selection of the primary-side N-channel power MOSFET
M1 is determined by the maximum levels expected for the
drain voltage and drain current. In addition, the power
losses due to conduction losses, gate driver losses and
transition losses will lead to a fine tuning of the MOSFET
selection. If power losses are high enough to cause an
unacceptable temperature rise in the MOSFET then several
MOSFETs may be required to be connected in parallel.
The maximum drain voltage expected for the MOSFET M1
follows from the equations previously stated in the active
clamp topology sections:
VDS (M1) = VIN2/(VIN – (VOUT • N))
The MOSFET should be selected with a BVDSS rating ap-
proximately 20% greater than the above steady state VDS
calculation due to tolerances in duty cycle, load transients,
voltage ripple on CCL and leakage inductance spikes. A
MOSFET with the lowest possible voltage rating for the
application should be selected to minimize switch on re-
sistance for improved efficiency. In addition, the MOSFET
should be selected with the lowest gate charge to further
minimize losses.
3753 F18
NS
MAIN
XFMR
VOUT
COUT
SW
NP
••
•
•
VAUX2
NL2
NL1
3753 F19
NS
MAIN
XFMR SW
(a) (b) (c)
VAUX2
NP
••
NS
MAIN
XFMR
SW
VAUX2
NP
••
NAUX
•
NS
MAIN
XFMR
SW
VAUX2
NP
••
NAUX
•
LT3753
31
Rev. C
For more information www.analog.com
MOSFET M1 losses at maximum output current can be
approximated as :
PM1 = PCONDUCTION + PGATEDRIVER + PTRANSITION
(i) PCONDUCTION = (NP/NS) • (VOUT/VIN) • (NS/NP •
IOUT(MAX))2 • RDS(ON)
Note: The on resistance of the MOSFET, RDS(ON), in-
creases with the MOSFET’s junction temperature. RDS(ON)
should therefore be recalculated once junction tem-
perature is known. A final value for RDS(ON) and therefore
PCONDUCTION can be achieved from a few iterations.
(ii) PGATEDRIVER = (QG • INTVCC • fOSC)
where,
QG = gate charge (VGS = INTVCC)
(iii) PTRANSITION = PTURN_OFF + PTURN_ON (≈ 0 if ZVS)
(a) PTURN_OFF = (1/2)IOUT(MAX)(NS/NP)(VIN/1-D)
(QGD/IGATE) • fOSC
where,
QGD = gate to drain charge
IGATE = 2A source/sink for OUT pin gate driver
(b) PTURN_ON = (1/2)IOUT(MAX)(NS/NP)(VDS)(QGD/IGATE)
• fOSC
where,
VDS = M1 drain voltage at the beginning of M1 turn on
VDS typically sits between VIN and 0V (ZVS)
During programmable timing tAO, negative IMAG discharges
M1 drain SWP towards VIN (Figure 1). ZVS is achieved if
enough leakage inductance exists—to delay the second-
ary side from clamping M1 drain to VIN—and if enough
energy is stored in LMAG to discharge SWP to 0V during
that delay. (see Programming Active Clamp Switch Timing:
AOUT to OUT (tAO)).
Synchronous Control (SOUT)
The LT3753 uses the SOUT pin to communicate syn-
chronous control information to the secondary side
synchronous rectifier controller (Figure 20). The isolating
transformer (TSYNC), coupling capacitor (CSYNC) and resis-
tive load (RSYNC) allow the ground referenced SOUT signal
to generate positive and negative signals required at the
SYNC input of the secondary side synchronous rectifier
controller. For the typical LT3753 applications operating
with an LT8311, CSYNC is 220pF, RSYNC is 560Ω and TSYNC
is typically a PULSE PE-68386NL.
Figure 20. SOUT Pulse Transformer
APPLICATIONS INFORMATION
3753 F20
CSYNC
220pF
RSYNC
560Ω
SYNC
(SECONDARY SIDE
CONTROLLER)
TSYNC
SOUT
(LT3753) 2
1
3
5
6
4
•
•
•
•
Typically choose CSYNC between 220pF and 1nF. RSYNC
should then be chosen to obey :
(1) SOUTMAX/100mA ≤ RSYNC ≤ √(LMAG/CSYNC)
where,
SOUTMAX = INTVCC
LMAG = TSYNC’S magnetizing inductance
100mA = SOUT gate driver minimum source current
and
(2) RSYNC • CSYNC ≥ (–1) • Y/(ln (Z/SOUTMAX))
LT3753
32
Rev. C
For more information www.analog.com
where,
Y = SYNC minimum pulse duration (50ns; LT8311)
Z = |SYNC level to achieve Y| (±2V: LT8311)
Even though the LT3753 INTVCC pin is allowed to be over
driven by as much as 15.4V, SOUTMAX level should be
designed to not cause TSYNC output to exceed the maximum
ratings of the LT8311’s SYNC pin.
Cost/Space reduction : If discontinuous conduction mode
(DCM) operation is acceptable at light load, the LT8311
has a preactive mode which controls the synchronous
MOSFETs without TSYNC, CSYNC, RSYNC or the LT3753
timing resistors RTAS, RTOS (leave open).
Output Inductor Value
The choice of output inductor value LOUT will depend on
the amount of allowable ripple current. The inductor ripple
current is given by:
IL(RIPPLE)(P-P)
= ∆IL = (VOUT/(LOUT • fOSC)) • (1 – (VOUT/VIN)(NP/NS))
The LT3753 allows very large ∆IL values (low LOUT values)
without the worry of insufficient slope compensation—by
allowing slope compensation to be programmed with an
external resistor in series with the ISENSEP pin (see Cur-
rent Sensing and Programmable Slope Compensation).
Larger ∆IL will allow lower LOUT, reducing component size,
but will also cause higher output voltage ripple and core
losses. For LT3753 applications, ∆IL is typically chosen
to be 40% of IOUT(MAX).
Output Capacitor Selection
The choice of output capacitor value is dependent on
output voltage ripple requirements given by :
∆VOUT ≈ ∆IL(ESR + (1/(8 • fOSC • COUT))
where,
∆IL = output inductor ripple current IL(RIPPLE)(P-P)
ESR = effective series resistance (of COUT)
fOSC = switching frequency
COUT = output capacitance
This gives:
COUT = ∆IL/(8 • fOSC • ( ∆VOUT – ∆IL • ESR))
Typically COUT is made up of a low ESR ceramic capacitor(s)
to minimize ∆VOUT. Additional bulk capacitance is added
in the form of electrolytic capacitors to minimize output
voltage excursions during load steps.
Input Capacitor Selection
The active clamp forward converter demands pulses of
current from the input due to primary winding current and
magnetizing current. The input capacitor is required to
provide high frequency filtering to achieve an input voltage
as close as possible to a pure DC source with low ripple
voltage. For low impedance input sources and medium to
low voltage input levels, a simple ceramic capacitor with
low ESR should suffice. It should be rated to operate at a
worst case RMS input current of :
ICIN(RMS) = (NS/NP) IOUT(MAX)/2
A small 1µF bypass capacitor should also be placed close
to the IC between VIN and GND.
As input voltage levels increase, any use of bulk capacitance
to minimize input ripple can impact on solution size and
cost. In addition, inputs with higher source impedance will
cause an increase in voltage ripple. In these applications it
is recommended to include an LC input filter. The output
impedance of the input filter should remain below the
negative input impedance of the DC/DC forward converter.
APPLICATIONS INFORMATION
LT3753
33
Rev. C
For more information www.analog.com
APPLICATIONS INFORMATION
PCB Layout/Thermal Guidelines
For proper operation, PCB layout must be given special
attention. Critical programming signals must be able to
coexist with high dv/dt signals. Compact layout can be
achieved but not at the cost of poor thermal management.
The following guidelines should be followed to approach
optimal performance.
1. Ensure that a local bypass capacitor is used (and placed
as close as possible) between VIN and GND for the
controller IC(s).
2. The critical programming resistors for timing (pins
TAO,TAS,TOS,TBLNK, IVSEC and RT) must use short traces
to each pin. Each resistor should also use a short trace
to connect to a single ground bus specifically connected
to pin 18 of the IC (GND).
3. The current sense resistor for the forward converter
must use short Kelvin connections to the ISENSEP and
ISENSEN pins.
4. High dv/dt lines should be kept away from all timing
resistors, current sense inputs, COMP pin, UVLO_VSEC/
OVLO pins and the FB trace.
5. Gate driver traces (AOUT, SOUT, OUT) should be kept
as short as possible.
6. When working with high power components, multiple
parallel components are the best method for spread-
ing out power dissipation and minimizing temperature
rise. In particular, multiple copper layers connected
by vias should be used to sink heat away from each
power MOSFET.
7. Keep high switching current PGND paths away from
signal ground. Also minimize trace lengths for those
high current switching paths to minimize parasitic
inductance.
LT3753
34
Rev. C
For more information www.analog.com
APPLICATIONS INFORMATION
Figure 21. 36V to 72V, 5V/20A 100W Active Clamp Isolated Forward Converter
R4
44.2k
R3
1.87k
R5
14.7k R7
57.6k
R6
30.1k
R9
100k
R8
100k
V+
GND-F
GND-S
COLL
C11
3.3nF
R22
34.8k
REF
LT1431
1k
R13 R12
0.012Ω
M1
M3
M4
M2
R14
10k D1
R11
100Ω
PS2801-1
1k
R10 2.2nF
250V
T1: CHAMPS G45R2-0209
L1: CHAMPS PQI2050-3R3
D1: BAS516
D2: CENTRAL SEMI. CMHZ5229B
C2
1µF
C3
22nF
C4
4.7µF
25V
C10
1µF
10V
C9
22µF
10V
R18
1k
VOUT
D2
C13
47µF
10V
VOUT
5V
20A
C12
560µF
10V
3753 F21
C14
1µF
TAO
TAS
TOS
TBLNK
IVSEC
RT
SS1
SS2
FB
COMP
INTVCC
SOUT
ISENSEN
ISENSEP
OUTVIN AOUT
OC
R2
1.96k
R1
105k
UVLO_VSEC
LT3753
SYNC
C5
100nF IRF6217
T1
9:2
C7
68nF
250V
BSC0902NSI
BSC0902NSI
BSC190N15NS3
L1
3.3µH
R20
137k
R21
137k
+
••
C1
4.7µF
100V
×3
VIN
36V TO 72V
GND
OVLO
R19
100Ω
C8
4.7nF
C6, 250V
0.22µF R15
200Ω
R16
5Ω
R17
5Ω
LOAD CURRENT (A)
3753 F21a
201210 16 18140
EFFICIENCY (%)
96
94
92
86
90
88
42 86
36VIN
48VIN
72VIN
Efficiency vs Load Current
LT3753
35
Rev. C
For more information www.analog.com
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
PACKAGE DESCRIPTION
4.75
(.187) REF
FE38 (AB) TSSOP REV B 0910
0.09 – 0.20
(.0035 – .0079)
0° – 8°
0.25
REF
0.50 – 0.75
(.020 – .030)
4.30 – 4.50*
(.169 – .177)
119
PIN NUMBERS 23, 25, 27, 29, 31, 33 AND 35 ARE REMOVED
20
REF
9.60 – 9.80*
(.378 – .386)
38
1.20
(.047)
MAX
0.05 – 0.15
(.002 – .006)
0.50
(.0196)
BSC 0.17 – 0.27
(.0067 – .0106)
TYP
RECOMMENDED SOLDER PAD LAYOUT
0.315 ±0.05
0.50 BSC
4.50 REF
6.60 ±0.10
1.05 ±0.10
4.75 REF
2.74 REF
2.74
(.108)
MILLIMETERS
(INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
SEE NOTE 4
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
6.40
(.252)
BSC
FE Package
Package Variation: FE38 (31)
38-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1865 Rev B)
Exposed Pad Variation AB
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
A 08/15 Changed SS1 and SS2 ABS MAX ratings
Changed AOUT and SOUT driver times
Clarified SS2 pin (Soft-Start: Comp Pin) conditions
3
5
6
B 08/19 Corrected Active Clamp Capacitor Equation 23
C 06/20 Corrected UVLO Typo 3
LT3753
36
Rev. C
For more information www.analog.com
06/20
www.analog.com
© ANALOG DEVICES, INC. 2014–2020
3753 F22
LT3753
UVLO_VSEC
OVLO
IVSEC
RT
TOS
TBLNK
TAO
TAS
GND SS1 SS2
INTVCC
AOUT
FB
SYNC
SOUT
R4
71.5k
C4
1µF
C3
0.47µF
VIN
18V to
72V
VIN
R2
5.9k
R3
1.82k
R5
31.6k
240kHz
R7
34k
COMP
ISENSEN
OC
OUT
ISENSEP
R6
49.9k
C10
2.2µF
100V
••
C9
100nF
C6
4.7µF
R13, 2k
R12
6mΩ
R11
100Ω
C7
1µF
R10
1k
R8
100k
R9
100k
R22
124k
LT8311
FSW
CSW
CSP
CG
CSN
OPTO
GND
COMP
SYNC PMODE
SS
FB
VIN
INTVCC
PGOOD
TIMER
VOUT
12V/8A
VOUT
L1
6.8µH
D2
R19, 1.78k
R20, 1.5k
FG
R16, 2k R25
100k
R24
20k
R26
11.3k
C19
22µF
× 2
R17, 2k
R18, 1.78k
C20
470µF
C18
68pF
C12
15nF
R21
2.94k
C14
1µF
C15
4.7µF
C16
2.2µF
C17
2.2nF
R14
10k
C11
100nF
4:4
T1
R23
100k
2.2nF
PS2801-1
C5
10pF
+
C1
4.7µF
× 3 R1
100k
D1
D3
T1: CHAMPS G45R2-0404.04
L1: CHAMPS PQR2050-6R8
M1: INFINEON BSC077N12NS3
M2: INTERNATIONAL RECTIFIER IRF6217
M3: FAIRCHILD SEMI. FDMS86101DC
M4: INFINEON BSC077N12NS3
D2: CENTRAL SEMI. CMMR1U-02
D3: DIODES INC. SBR1U150SA
M3
M1
M4
M2
RELATED PARTS
TYPICAL APPLICATION
PART NUMBER DESCRIPTION COMMENTS
LT3752/LT3752-1 Active Clamp Synchronous Forward Controllers with
Internal Housekeeping Controller Ideal for Medium Power 24V, 48V and Up to 400V Input Applications
LT8311 Preactive Secondary Synchronous and Opto Control
for Forward Converters Optimized for Use with Primary-Side LT3752-1, LT3753 and LT8310
Controllers
LTC3765/LTC3766 Synchronous No-Opto Forward Controller Chip Set
with Active Clamp Reset Direct Flux Limit, Supports Self Starting Secondary Forward Control
LTC3722/LTC3722-2 Synchronous Full Bridge Controllers Adaptive or Manual Delay Control for Zero Voltage Switching, Adjustable
Synchronous Rectification Timing
LT3748 100V Isolated Flyback Controller 5V ≤ VIN ≤ 100V, No Opto Flyback , MSOP-16 with High Voltage
Spacing
LT3798 Off-Line Isolated No-Opto Flyback Controller with
Active PFC VIN and VOUT Limited Only by External Components
Figure 22. 18V to 72V, 12V/8A Active Clamp Isolated Forward Converter
Efficiency and Power Loss
LOAD CURRENT (A)
0
EFFICIENCY (%)
POWER LOSS (W)
96
94
92
86
90
88
14
12
10
0
8
6
4
2
2
3753 F22a
106 84
VIN = 48V
