CD4052BCSJ - Fairchild Semiconductor

November 1983

Revised April 2002

CD4051BC • CD4052BC • CD40 53BC Single 8-Channel Analog Mul tiplexer/Demultiplexe r • Dual 4-Channel Analog

Multiple xer/Demultipl exer • Triple 2-Channel Ana log Multiplexer/Demultiplexer

CD4051BC • CD4052BC • CD4053BC

Single 8-Channel Analog Multiplexer/Demultiplexer •

Dual 4-Channel Analog Multiplexer/Demultiplexer •

Triple 2-Channe l Ana log Multiplexer/Demultiplexer

General Description

The CD4 051BC, C D4052B C, and CD4 053BC an alog mul -

tiplexers/demultiplexers are digitally controlled analog

switches having low “ON” impedance and very low “OFF”

leakage currents. Control of analog signals up to 15Vp-p

can be ac hieved by di gital s ignal am plitud es of 3 −15V. For

example , if VDD = 5V, VSS = 0V and V EE = −5V, analog sig-

nals from −5V to +5V can b e control led by digi tal inputs of

0−5V. The multiplexer circuits dissipate extremely low qui-

escent power over the full VDD−VSS and VDD−VEE supply

voltage ranges, independent of the logic state of the control

signals. When a logical “1” is present at the inhibit input ter-

minal all channels are “OFF”.

CD4051BC is a single 8-channel multiplexer having three

binary c ontr ol i n put s. A , B, and C, and an i nh ibit i n put . T he

three binary signals select 1 of 8 channels to be turned

“ON” and connect the input to the output.

CD4052BC is a differential 4-channel multiplexer having

two binary control inputs, A and B, and an inhibit input. The

two binary input signals select 1 or 4 pairs of chan nels to

be turned on and connect the differential analog inputs to

the differential outputs.

CD4053BC is a triple 2-channel multiplexer having three

separate d igital control inputs, A, B, and C, and a n inhibit

input. Ea ch control input selects one of a pair of ch annels

which are connected in a single-pole double-throw configu-

ration.

Features

■Wide range of digital and analog signal levels:

digital 3 – 15V, analog to 15Vp-p

■Low “ON” resistance: 80Ω (typ.) over entire 15Vp-p

signal-input range f or VDD − VEE = 15V

■High “OFF” resistance:

channel leakage of ±10 pA (typ.) at VDD − VEE = 10V

■Logic level conversion for digital addressing signals of

3 – 15V (VDD − VSS = 3 – 15V) to switch analog signals

to 15 Vp-p (VDD − VEE = 15V)

■Matched switch characteristics:

∆RON = 5Ω (typ.) for VDD − VEE = 15V

■Very low quiescent power dissipation under all

digital-control input and supply conditions:

1 µ W (typ.) at VDD − VSS = VDD − VEE = 10V

■Binary address decoding on chip

Ordering Code:

Devices also available in Tape and Reel. Spe ci fy by append ing the suffix let t er “X” to the ordering code.

Order Number Package Number Package Description

CD4051BCM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

CD4051BCSJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

CD4051BCMTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

CD4051BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

CD4052BCM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

CD4052BCSJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

CD4052BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

CD4053BCM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

CD4053BCSJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

CD4053BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

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CD4051BC • CD4052BC • CD4053BC

Connection Diagrams

Pin Assignments for DIP and SOIC

CD4051BC CD4052BC

CD4053BC

Truth Table

*Don’t Care condition.

INPUT STATES “ON” CHANNELS

INHIBIT C B A CD4051B CD4052B CD4053B

0 0 0 0 0 0X, 0Y cx, bx, ax

0 0 0 1 1 1X, 1Y cx, bx, ay

0 0 1 0 2 2X, 2Y cx, by, ax

0 0 1 1 3 3X, 3Y cx, by, ay

0 1 0 0 4 cy, bx, ax

0 1 0 1 5 cy, bx, ay

01106 cy, by, ax

01117 cy, by, ay

1 * * * NONE NONE NONE

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CD4051BC • CD4052BC • CD4053BC

Logic Diagrams

CD4051BC

CD4052BC

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CD4051BC • CD4052BC • CD4053BC

Logic Diagrams (Continued) CD4053BC

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CD4051BC • CD4052BC • CD4053BC

Absolute Maximum Ratings(Note 1) Recommended Operating

Conditions

Note 1: “Absolute Maximum Ratings” are tho se values beyond which t he

safety of the device cannot be guaranteed. Except for “Operat ing Tempera -

ture Range” they are not mea nt to imply that the devices sh ould be oper-

ated at t hes e limits . Th e Electrical Charac t eristics t ables prov ide condit ions

for actu al device operation.

DC Electrical Characteristics (Note 2)

DC Supply Voltage (VDD)−0.5 VDC to +18 VDC

Input Voltage (VIN)−0.5 VDC to VDD +0.5 VDC

Storage Temperature

Range (TS)−65°C to +150°C

Power Dissipation (PD)

Dual-In-Line 700 mW

Small Outline 500 mW

Lead Temperature (TL)

(soldering, 10 seconds) 260°C

DC Supply Voltage (VDD)+5 VDC to +15 VDC

Input Voltage (VIN) 0V to VDD VDC

Operati ng Temperatu re Range ( TA)

CD4051BC/CD4052BC/CD4053BC −55°C to +125°C

Symbol Parameter Conditions −55°C+25°125°CUnits

Min Max Min Typ Max Min Max

Control A, B, C and Inhibit

IIN Input Current VDD = 15V, VEE = 0V −0.1 −10−5−0.1 −1.0 µA

VIN = 0V

VDD = 15V, VEE = 0V 0.1 10−50.1 1.0

VIN = 15V

IDD Quiescent Device Current VDD = 5V 5 5 150 µAVDD = 10V 10 10 300

VDD = 15V 20 20 600

Signal Inputs (VIS) and Outputs (VOS)

RON “ON” Resistance (Peak RL = 10 kΩVDD = 2.5V,

800 270 1050 1300 Ω

for VEE ≤ VIS ≤ VDD) (any channel VEE = −2.5V

selected) or VDD = 5V,

VEE = 0V

VDD = 5V,

310 120 400 550 Ω

VEE = −5V

or VDD = 10V,

VEE = 0V

VDD = 7.5V,

200 80 240 320 Ω

VEE = −7.5V

or VDD = 15V,

VEE = 0V

∆RON ∆ “ON” Resistance RL = 10 kΩVDD = 2.5V,

10 Ω

Between Any Two (any channel VEE = −2.5V

Channels selected) or VDD = 5V,

VEE = 0V

VDD = 5V

10 Ω

VEE = −5V

or VDD = 10V,

VEE = 0V

VDD = 7.5V,

5Ω

VEE = −7.5V

or VDD = 15V,

VEE = 0V

“OFF” Channel Leakage VDD=7.5V, VEE=−7.5V

Current, any channel “OFF”O/I=±7.5V, I/O=0V ±50 ±0.01 ±50 ±500 nA

“OFF” Channel Leakage Inhibit = 7.5V CD4051 ±200 ±0.08 ±200 ±2000

Current, all channels VDD = 7.5V,

“OFF” (Common VEE = −7.5V, D4052 ±200 ±0.04 ±200 ±2000

OUT/IN) O/I = 0V

I/O = ±7.5V CD4053 ±200 ±0.02 ±200 ±2000

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CD4051BC • CD4052BC • CD4053BC

DC Electrical Characteristics (Continued)

Note 2: All voltages measured with respect to VSS unless ot herw i s e specified.

Symbol Parameter Conditions −55°C+25°125°CUnits

Min Max Min Typ Max Min Max

Control Inputs A, B, C and Inhibit

VIL LOW Level Input Voltage VEE = VSS RL = 1 kΩ to VSS

IIS<2 µA on all OFF Channels

VIS = VDD thru 1 kΩ

VDD = 5V 1.5 1.5 1.5 VVDD = 10V 3.0 3.0 3.0

VDD = 15V 4.0 4.0 4.0

VIH HIGH Level Input Voltage VDD = 5 3.5 3.5 3.5 VVDD = 10 7 7 7

VDD = 15 11 11 11

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CD4051BC • CD4052BC • CD4053BC

AC Electrical Characteristics (Note 3)

TA = 25°C, tr = tf = 20 ns, unless otherwise specified.

Note 3: AC Paramet ers are guaranteed by DC co rrelated te s tin g.

Note 4: A, B are two arbitrary channels with A turned “ON” and B “OFF”.

Symbol Parameter Conditions VDD Min Typ Max Units

tPZH, Propagation Delay Time from VEE = VSS = 0V 5V 600 1200 nstPZL Inhibit to Signal Output RL = 1 kΩ10V 225 450

(channel turning on) CL = 50 pF 15V 160 320

tPHZ, Propagation Delay Time from VEE = VSS = 0V 5V 210 420 nstPLZ Inhibit to Signal Output RL = 1 kΩ10V 100 200

(channel turning off) CL = 50 pF 15V 75 150

CIN Input Capacitance

Control input 57.5pF

Signal Input (IN/OUT) 10 15

COUT Output Capacitance

(common OUT/IN)

CD4051 10V 30 pFCD4052 VEE = VSS = 0V 10V 15

CD4053 10V 8

CIOS Feedthrough Capacitance 0.2 pF

CPD Power Dissipation Capacitance

CD4051 110 pFCD4052 140

CD4053 70

Signal Inputs (VIS) and Outputs (VOS)

Sine Wave Response RL = 10 kΩ

(Distortion) fIS = 1 kHz 10V 0.04 %

VIS = 5 Vp-p

VEE = VSI = 0V

Frequency Response, Channel RL = 1 kΩ, VEE = 0V, VIS = 5Vp-p, 10V 40 MHz

“ON” (Sine Wave Input) 20 log10 VOS/VIS = −3 dB

Feedthrough, Channel “OFF”RL = 1 kΩ, VEE = VSS = 0V, VIS = 5Vp-p, 10V 10 MHz

20 log10 VOS/VIS = −40 dB

Crosstalk Between Any Two RL = 1 kΩ, VEE = VSS = 0V, VIS(A) = 5Vp-p 10V 3 MHz

Channels (frequency at 40 dB) 20 log10 VOS(B)/VIS(A) = −40 dB (Note 4)

tPHL Propagation Delay Signal VEE = VSS = 0V 5V 25 55 nstPLH Input to Signal Output CL = 50 pF 10V 15 35

15V 10 25

Control Inputs, A, B, C and Inhibit

Control Input to Signal VEE = VSS = 0V, RL = 10 kΩ at both ends

Crosstalk of channel. 10V 65 mV (peak)

Input Square Wave Amplitude = 10V

tPHL, Propagation Delay Time from VEE = VSS = 0V 5V 500 1000 nstPLH Address to Signal Output CL = 50 pF 10V 180 360

(channels “ON” or “OFF”) 15V 120 240

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CD4051BC • CD4052BC • CD4053BC

Special Considerations

In certain applications the external load-resistor current

may include both VDD and signal-line components. To

avoid drawing VDD current when switch current flows into

IN/OUT pin, the voltage drop across the bidirectional

switch must not exceed 0.6V at TA≤25°C, or 0.4V at

TA>25°C (calculated from RON values shown). No VDD

current will flo w through RL if the switch current flows into

OUT/IN pin.

Typical Performance Characteristics

“ON” Resistance vs Si gn al

Voltage for TA = 25°C

“ON” Resistance as a

Function of Temperature f o r

VDD− VEE = 15V

“ON” Resistance as a

Func ti o n of Temperature for

VDD− VEE = 10V

“ON” Resistance as a

Func ti o n of Temperature for

VDD − VEE = 5V

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CD4051BC • CD4052BC • CD4053BC

Switching Time Waveforms

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CD4051BC • CD4052BC • CD4053BC

Physical Dimensions inches (millimeters) unless otherwise noted

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

Package Number M16A

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CD4051BC • CD4052BC • CD4053BC

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package Number M16D

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CD4051BC • CD4052BC • CD4053BC

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Package Number MTC16

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CD4051BC • CD4052BC • CD4053BC Single 8-Channel Analog Multiplexer/Demul tiplexer • Dual 4-Channel Analog

Multiplexer/Demultiplexer • Triple 2-Channel Analog Multiplexer/Demultiplexer

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Package Number N16E

Fairchild does not assume an y responsibility for u se of any circuitry descr ibed, no circuit pat ent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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