v2.0 MIL-STD-1553B Bus Controller Core1553BBC Pr od uc t S um m ary S ynt he si s and S im ul ati on S uppor t In t e n d e d Us e * Synthesis: Exemplar, Synplicity, Design Compiler, FPGA Compiler, FPGA Express * 1553B Bus Controller (BC) * DMA Backend Interface to External Memory K ey Fea tu re s * Simulation: Vital-Compliant VHDL Simulators and OVI-Compliant Verilog Simulators Ve ri fica ti on and Com p lia nce * Supports MIL-STD-1553B * Actel-Developed Simulation Testbench * Interfaces to External RAM * Core Implemented on the 1553B BC Development System - Supports up to 128kbytes of Memory - Synchronous or Asynchronous Backend Interface - Backend Interface Identical to Core1553BRT * Selectable Clock Rate of 12 MHz, 16 MHz, 20, MHz or 24 MHz * Third-Party 1553B Compliance Testing of the 1553B Encoder and Decoder Blocks Implemented in a A54SXA32-STD Device * Provides Direct CPU Access to Memory * Complete 1553B BC Implementation in an SX-A Device * Interfaces to Standard 1553B Transceivers * Includes a PCI Interface for Host CPU Connection * Fully Automated Message Scheduling * Includes Transceivers and Bus Termination Components - - - - Frame Support Conditional Branching and Sub-routines Variable Inter-message Gaps and RT Response Times Real Time Clock for Message Scheduling - Asynchronous Message Support T arg et ed D ev ice s * SX-A Family * RTSX Family * RT54SX-S Family * ProASICPLUS Family * Axcelerator Family Cor e Del iv er abl es * Netlist Version - Compiled RTL Simulation Model, Compliant with Actel's LiberoTM Integrated Design Environment (IDE) - Compatible with Actel's Designer Place-and-Route Tool * RTL Version - VHDL or Verilog Core Source Code - Synthesis Scripts De vel opm en t Sy s te m (opt i onal ) G en er al D e sc r i p t i on The Core1553BBC provides a complete, MIL-STD-1553B Bus Controller (BC). A typical system implementation using the Core1553BBC is shown in Figure 1 on page 2. Core1553BBC reads message descriptor blocks from the memory and generates messages that are transmitted on the 1553B bus. Data words are read from the memory and transmitted on the 1553B bus. Data received is written to the memory. The core can be configured directly to connect to synchronous or asynchronous memory devices. The core consists of five main blocks: 1553B encoder, 1553B decoder, a protocol controller block, CPU interface, and a backend interface (Figure 2 on page 2). A single 1553B encoder takes each word to be transmitted and serializes it using Manchester encoding. The encoder also includes independent logic to prevent the BC from transmitting for greater than the allowed period and loopback fail logic. The loopback logic monitors the received data and verifies that the core has correctly received every word that it transmits. The output of the encoder is gated with the bus enable signals to select which buses the RT should be transmitting. * Actel-Developed Testbenches, VHDL and Verilog March 2003 (c) 2003 Actel Corporation 1 M I L -S TD -1 5 5 3 B B u s C o n t r o l le r C o r e 1 5 5 3 B B C Backend Interface BUSAINEN BUSAINP BUSAINN Memory BUSAOUTINH BUSAOUTP BUSAOUTN CPU Interface Glue Logic CPU BUSBINEN BUSBINP BUSBIN BUSAOUTINH BUSBOUTP BUSBOUTN RCVSTBA RXDAIN RXDAIN TXINHA TXDAIN TXDAIN Transceiver (Not Included) RCVSTBA RXDBIN RXDBIN TXINHA TXDBIN TXDBIN Core1553BBC Actel FPGA Figure 1 * Typical Core1553BBC System BusA Encoder Protocol Controller BusB Decoder Backend Interface Memory 64K*16 CPU Interface and Registers Core1553BBC Figure 2 * Core1553BBC BC Block Diagram Since the BC knows which bus is in use at any time, only a single decoder is required. The decoder takes the serial Manchester received data from the bus and extracts the received data words. The decoder requires a 12 MHz, 16 MHz, 20 MHz, or 24 MHz clock to extract the data and the clock from the serial stream. The decoder contains a digital phased lock loop (PLL) that generates a recovery clock used to sample the incoming serial data. The data is then deserialized and the 16-bit word decoded. The decoder detects whether a command, status or data word has been received and checks that no Manchester encoding or parity errors occurred in the word. The protocol controller block handles all the message sequencing and error recovery. This is a complex state machine that reads the 1553B message frames from the memory and transmits them on the 1553B bus. 2 v2.0 M I L -S TD -1 5 5 3 B B u s C o n t r o l le r C o r e 1 5 5 3 B B C The CPU interface allows the system CPU to access the control registers within the BC. It also allows the CPU to directly access the memory connected to the backend interface; this can simplify the system design. The backend interface for the Core1553BBC allows a simple connection to a memory device. The backend interface can be configured to connect to either synchronous or asynchronous memory devices. This allows the core to be connected to synchronous logic or memory within the FPGA or to external asynchronous memory blocks. The interface supports a standard bus request and grant protocol and provides a WAIT input allowing the core to interface to slow memory devices. This allows the core to share system memory rather than have its own dedicated memory block. Co re1 553B BC Ope rat i on A bus controller is responsible for sending data bus commands, participating in data transfers, receiving status responses, and monitoring the bus system. The system CPU will create message lists in the BC memory, as illustrated in Figure 3. When started, the BC works its way through the message lists. Core1553B transmits the specified 1553B command and data words. It receives the 1553B status word and associated data words and writes them to the BC memory. During this process, the BC monitors all possible 1553B error conditions. If an RT does not respond correctly, the BC will retry the message on both the original bus and the alternate bus. Instruction List INSTRUCTION Message Block Data Block PARAMETER INSTRUCTION PARAMETER MSGCMD INSTRUCTION CW (RTRT RX) PARAMETER CW (RTRT TX) 32 Data Words DATAPTR SW (RTRT TX) SW (RTRT RX) TSW Figure 3 * Message Lists v2.0 3 M I L -S TD -1 5 5 3 B B u s C o n t r o l le r C o r e 1 5 5 3 B B C C or e 1 55 3B B C De vi c e Re q ui r e m e nt s Core1553BBC can be implemented in several Actel FPGA devices. Table 1 gives typical utilization figures for the core implemented in these devices. Table 1 * Device Utilization Cells or Tiles Family Combinatorial Sequential Device Utilization RTAX-S 1,092 546 RTAX1000S-STD 9% 1,103 550 RT54SX32S-STD 57% ProASIC 2,166 532 APA150-STD 44% SX-A 1,085 547 A54SX32A-STD 56% Axcelerator 1,092 546 AX500-STD 20% RT54SX-S PLUS The Core1553BBC clock rate can be programmed to be 12 MHz, 16 MHz, 20 MHz or 24 MHz. All Actel families listed in Table 1 easily meet the required performance. When implemented in ProASICPLUS or Axcelerator devices, the core can be connected directly to the internal FPGA memory blocks, eliminating the need for external memories. C or e 1 55 3B B C Ve r i f i c a t i on a nd C om p l i an c e Core1553BBC is based upon Actel's Core1553BRT, which has been fully verified against the RT validation Test Plan (MIL-HDBK-1553A, Appendix A). This ensures that the 1553B encoders and decoders are fully compliant to the 1553B specification. The actual bus controller function has been extensively verified in both simulation and hardware. Core1553BBC has been implemented on an A54SX32A-STD part connected to external transceivers and memory. 4 M I L - S TD - 1 55 3B B u s O ve r v i ew The MIL-STD-1553B bus is a differential serial bus used in military and space equipment. It is comprised of multiple redundant bus connections and communicates at 1MB per second. The bus has a single active bus controller (BC) and up to 31 remote terminals (RTs). The BC manages all data transfers on the bus using the command and status protocol. The bus controller initiates every transfer by sending a command word and data if required. The selected RT will respond with a status word and data if required. The 1553B command word contains a five-bit RT address, transmit or receive bit, five-bit sub-address and five-bit word count. This allows for 32 RTs on the bus. However, only 31RTs may be connected, since the RT address (31) is used to indicate a broadcast transfer, i.e. all RTs should accept the following data. Each RT has 30 sub-addresses reserved for data transfers. The other two sub-addresses (0 and 31) are reserved for mode codes used for bus control functions. Data transfers contain up to (32) 16-bit data words. Mode code command words are used for bus control functions such as synchronization. v2.0 M I L -S TD -1 5 5 3 B B u s C o n t r o l le r C o r e 1 5 5 3 B B C Mes sa ge Ty pes The 1553B bus supports ten message transfer types, allowing basic point-to-point and broadcast BC to RT data transfers, mode code messages, and direct RT-to-RT messages. Figure 4 shows the message formats. BC-to-RT Transfer BC Transmit Command BC RT Data 0 Data ... Data n Response Time Status Word Message Gap Next Command Data 0 Data ... Data n Message Gap Next Command RT-to-BC Transfer BC Receive Command RT Response Time BC Status Word RT-to-RT Transfer BC RT1 Receive Transmit Command Command Response Time Status Word BC RT2 Data 0 Data ... Data n Response Time Status Word Data n Message Gap Next Command Message Gap Next Command BC-to-all-RTs Broadcast BC Transmit Command BC Data 0 Data ... Data n Response Time Status Word Message Gap Next Command Data 0 Data ... RT-to-all RTs Broadcast BC RT Receive Transmit Command Command BC Mode Command, No Data BC Mode Command BC RT Response Time Status Word Message Gap Next Command Mode Data Message Gap Mode Command, RT Transmit Data BC Mode Command BC RT Response Time Status Word Next Command Mode Command, RT Receive Data BC Mode Command BC RT Mode Data Response Time Status Word Message Gap Next Command Broadcast Mode Command, No Data BC Mode Command BC Message Gap Next Command Broadcast Mode Command with Data BC Mode Command BC Mode Data Message Gap Next Command Figure 4 * 1553B Message Formats v2.0 5 M I L -S TD -1 5 5 3 B B u s C o n t r o l le r C o r e 1 5 5 3 B B C W or d Fo rm a ts There are only three types of words in a 1553B message: a command word (CW), a data word (DW), and a status word (SW). Each 20-bit word consists of a three-bit sync pattern, 16 bits of data, and a parity bit (Figure 5). 4 5 6 CW Sync 7 8 9 10 11 13 14 15 16 17 18 19 1 5 5 1 RT Address T/R Sub-address Word Count/Mode Code P RT Address 1 1 1 Service Request 5 1 P Instrumentation SW 16 Data Message Error Sync 3 Reserved 1 1 1 1 1 1 Figure 5 * 1553B Word Formats I / O Si g n al D e sc r i p t i on s 1553 B Bus In ter f ac e Name BUSAINEN Type Out Description Active high output that enables for the A receiver BUSAINP In Positive data input from the A receiver BUSAINN In Negative data input from the A receiver BUSBINEN BUSBINP BUSBINN Out Active high output that enables for the B receiver In Positive data input from the bus to the B receiver In Negative data input from the bus to the B receiver BUSAOUTIN Out Active high transmitter inhibit for the A transmitter BUSAOUTP Out Positive data output to the bus A transmitter (is held high when no transmission) BUSAOUTN Out Negative data output to the bus A transmitter (is held high when no transmission) BUSBOUTIN Out Active high transmitter inhibits the B transmitter BUSBOUTP Out Positive data output to the bus B transmitter (is held high when no transmission) BUSBOUTN Out Negative data output to the bus B transmitter (is held high when no transmission) 6 20 5 DW Sync 12 Parity 3 Dynamic Bus Acceptance Terminal Flag 2 Subsystem Flag 1 Broadcast Received Busy Bit v2.0 M I L -S TD -1 5 5 3 B B u s C o n t r o l le r C o r e 1 5 5 3 B B C Control and Status Signals Name Type Description CLK In Master clock input (either 12 MHz, 16 MHz, 20 MHz, or 24 MHz) RSTINn In Reset input (active low) INTOUT Out Interrupt Request (active high). The CPU is required to read the internal status register to find the reason for the interrupt. It is cleared by the CPU writing to the interrupt register MEMFAIL Out This goes high if the core fails to read or write data to the backend interface within the required time. This can be caused by the backend not asserting MEMGNTn fast enough or asserting MEMWAITn for too long. It is cleared by the CPU writing to the interrupt register BUSY Out This is high when the core is active, i.e. processing a message list EXTFLAG In External flag input used by the condition codes within the bus controller CP U Int erf ace The CPU interface allows the access to the Core1553BBC internal registers and direct access to the backend memory. This interface is synchronous to the clock (Table 2). Table 2 * CPU Interface Signals Name Type Description CPUCSn In CPU chip select input (active low) CPUWRn[1:0] In CPU write input (active low). Two write inputs are provided for processors that support byte operations. When CPUWRn[1] is '0,' data bits [15:8] are written. When CPUWRn[0] is '0,' data bits [7:0] are written CPURDn In CPU read input (active low) CPUWAITn Out CPU wait output (active low) indicates that the CPU should hold CPURDn or CPUWRn active while the core completes the read or write operation. CPUWAITn is not asserted when the internal CPU registers are accessed. When accessing the backend interface through the core, CPUWAIT will be activated for a minimum of four clock cycles for read operations and three for write operations. CPUWAITn is asserted for extra clock cycles if the backend interface delays asserting MEMGNTn or asserts MEMWAITn. Timing is shown in the "CPU Interface Memory Read Cycle" figure and "CPU Interface Memory Write Cycle" figure on page 19 CPUMEM In Selects whether the CPU accesses internal registers or backend memory. '0': Accesses internal registers, register number is specified on CPUADDR[2:0] '1': Accesses the backend memory CPUADDR[15:0] In CPU address input CPUDOUT[15:0] Out CPU data output In CPU data input CPUDIN[15:0] CPUDEN Out Data bus enable (active high). This signal is high when the core is providing data output on the CPUDOUT bus. It is intended for a tristate enable function v2.0 7 M I L -S TD -1 5 5 3 B B u s C o n t r o l le r C o r e 1 5 5 3 B B C Backend Interface The backend interface supports both synchronous operation and asynchronous operation to backend devices. Synchronous operation directly supports the use of internal FPGA memory blocks. Asynchronous operation allows connection to standard external memory devices. Table 3 * Backend Signals Name Type Description Memory Request (active low) output. The BC holds MEMREQn active if it requires additional memory access cycles to take place immediately after the current memory cycle. This occurs during the inter-message gap MEMREQn Out MEMGNTn In Memory Grant (active low) input. This input should be synchronous to CLK and needs to meet the internal register setup time. This input may be held low if the core has continuous access to the RAM Out Memory Write (active low). When MEMWRn[1] is '0,' D[15:8] is written. When MEMWRn[0] is '0,' D[7:0] is written. Synchronous mode: This output indicates that data will be written on the rising clock edge. If MEMWAITn is asserted, the MEMWRn pulse will be extended until MEMWAITn becomes inactive. Asynchronous mode: This output will be low for a minimum of one clock period and can be extended by the MEMWAITn input. The address and data are valid one clock cycle before MEMWRn is active and held for one clock cycle after MEMWRn goes inactive MEMRDn Out Memory Read (active low) Synchronous mode: This output indicates that data is read on the next rising clock edge. If MEMWAITn is active, then the data will be sampled on the rising clock edge on which MEMWAITn becomes inactive. This signal is intended as the read signal for synchronous RAMS. Asynchronous mode: This output will be low for a minimum of one clock period and can be extended by the MEMWAITn input. The address is valid one clock cycle before MEMRDn is active and held for one clock cycle after MEMRDn goes inactive. The data is sampled as MEMRDn goes high MEMCSn Out Memory Chip Select (active low). This output has the same timing as MEMADDR MEMWRn[1:0] MEMWAITn In Memory Wait (active low) indicates that the backend is not ready, and the core should extend the read or write strobe period. This input should be synchronous to CLK and needs to meet the internal register set up time. It can be permanently held high MEMADDR[15:0] Out Memory address output MEMDOUT[15:0] Out Memory data output In Memory data input MEMDIN[15:0] MEMCEN Out Control signal enable (active high). This signal is high when the core is requesting the memory bus and has been granted control. It is intended to enable any tristate drivers that may be implemented on the memory control and address lines MEMDEN Out Data bus enable (active high). This signal is high when the core is requesting the memory bus has been granted control and is waiting to write data. It is intended to enable any bidirectional drivers that may be implemented on the memory data bus 8 v2.0 M I L -S TD -1 5 5 3 B B u s C o n t r o l le r C o r e 1 5 5 3 B B C The backend interface must allow the bus controller access to the memory when requested. The memory access time from MEMREQn low to completion of the access cycle MEMRDn and MEMWRn high varies on the BC setup. When the CPU is allowed to access the memory through the bus controller (CPUMEMEN active), the memory access time is reduced (Table 4). Table 4 * Memory Access Requirements CPUMEMEN CLK Speed MHz Memory Access Time 0 12 9.58s 0 16 9.68s 0 20 9.75s 0 24 9.79s 1 12 4.58s 1 16 4.68s 1 20 4.75s 1 24 4.79s If the backend fails to allow the bus controller access to the memory in the required time, the bus controller will assert its MEMFAIL output and stop operation. Mi sce lla neous I/O Several inputs are used to modify the core functionality to simplify integration in the application. These inputs should be tied to logic '0' or logic '1' as appropriate (Table 5). Table 5 * Miscellaneous I/O Name Type ASYNCIF In CPUMEMEN In Description When '1,' the backend interface is in asynchronous mode. When '0,' the backend interface is in synchronous mode When '1,' the CPU interface has access to the backend memory. When '0,' the CPU cannot access the backend memory through the core. This must be set to '0' if the core shares the CPU memory, i.e. the CPU and memory buses are connected to the same system bus. Bus C ont r oll er R egi st er s The bus controller has nine internal registers that are used to control the bus controller operation and to provide status information (Table 6). Table 6 * Bus Controller Registers Address Name Type Size Function 000 000 001 CONTROL STATUS SETUP W R RW [3:0] [15:0] [15:0] 010 LISTPTR RW [15:0] 011 MSGPTR R [15:0] 100 CLOCK RW [15:0] 101 ASYNCPTR RW [15:0] 110 STACKPTR RW [15:0] 111 INTERRUPT RW [15:0] Allows the CPU to control the BC Provides status information BC setup register Current LISTPTR value. The address of the current instruction being executed. At the start of operation, the CPU should set this to the point at the first instruction. This value will automatically step through the BC instruction list Current MSGPTR value. Provides the address of the message block being processed BC internal clock value This 16-bit value counts up at a 1s, 4s, 8s, or 32s rate. This gives a maximum timer value of 2 seconds. The CPU may directly load the counter Asynchronous list pointer Provides a pointer to a list of messages that will be processed when started by the ASYNC message list bit in the control register BC stack pointer This is the internal stack pointer register; it is used for the CALL and RETURN instructions. When the bus controller is started, the STACKPTR is set to FFFF. The upper eight bits are fixed to FF, and the lower eight bits will count down and up. This allows up to 255 addresses to be stored in the stack memory Interrupt Register v2.0 9 M I L -S TD -1 5 5 3 B B u s C o n t r o l le r C o r e 1 5 5 3 B B C Setup Register Bits 15 14 13:12 Name FORCEORUN CLOCKEN CLKFREQ Type RW RW RW Reset Function 0 '1': If a BC-RT message with a word count between 1 and 31 is carried out, the BC will transmit for greater than 680us. This will cause the transmitter timer to trigger and the BC to shutdown. '0': Normal operation 0 Enables the internal CLOCK to count. '0': Internal CLOCK will not count '1': Internal CLOCK enabled The clock is automatically enabled by the WAITC instruction 01 Tells the core what the external clock frequency is. 00: 12 MHz 01: 16 MHz 10: 20 MHz 11: 24 MHz 11 RETRYMODE WR 0 Sets how the retry system works '0': Retries on the same bus for the number of times set by the reties setting in the message block. Then on the alternate bus for the number of times set by the alternate bus reties in the message block '1': Reties alternates between the two buses. The total number of retries is the number of reties plus alternative bus retries as set in the message block 10 INTENABLE RW 0 Enables the external interrupt pin, when '1': The INTPENDING bit will drive the INTOUT pin '0': The INTOUT pin is held at a '0' 9 AUTOCLOCK RW 1 '1': Sets the CLOCK register to 0000 when the BC is started '0': The CLOCK register is not reset when the BC is started 8 AUTOSTACK RW 1 '1': Sets the STACKPTR register to FFFF when the BC is started '0': The STACKPTR register is not reset when the BC is started.This allows the BC to be restarted when previously stopped. 00 Sets the rate at which the TIMER and CLOCK count 00: 1s 01: 4s 10: 8s 11: 32s 00 Sets the default minimum inter-message GAP 00: 4s 01: 8s 10: 16s 11: 32s Note: the actual inter-message GAP is a function of the memory access times. Typically, six memory accesses need to take place in the inter-message gap. 7:6 5:4 CLKRATE IMG RW RW 3:2 RESPTIME RW 01 Sets the maximum time that the BC will wait for an RT to respond 00: 12s 01: 16s 10: 20s 11: 24s 1:0 Reserved R 00 Reserved, return 00 10 v2.0 M I L -S TD -1 5 5 3 B B u s C o n t r o l le r C o r e 1 5 5 3 B B C Control Register Bits Name Type Function 3 ASYNC W Writing a '1' causes the bus controller to jump to process the asynchronous instruction list pointed to by the ASYNCPTR register at the end of the current message. When a RETAS instruction is found, the bus controller returns to the original instruction list. An ASYNC instruction can be issued while the bus controller is both active and inactive 2 ABORT W Writing a '1' stops the bus controller immediately; both normal and asynchronous message operation will be aborted 1 STOP W Writing a '1' stops the bus controller at the end of the current message 0 START W Writing a '1' starts the bus controller. The bus controller cannot be started when an asynchronous message is active Status Register Bits Name Type Function 15:8 VERSION R Indicated the Core1553BBC code revision. Core release notes provide latest version numbers 7:6 Reserved R Reserved, set to 00 5 LOOPFAIL R Indicates that a loopback failure occurred in the current frame 4 FRAMEOK R Indicates that all the messages in the current frame have completed successfully, and no system action is required 3 FLAG R Indicates the value of the flag condition stored by the STOREFLAG instruction 2 ASYNC R Asynchronous message requested or in progress. This bit is cleared by the RETAS instruction. When it is active, the bus controller cannot be started 1 BUSINUSE R Indicates which bus is in use 0: Bus A 1: Bus B 0 ACTIVE R BC is Active Interrupt Register Bits 15 Name Type INTPENDING RW Function When set, the BC has an interrupt pending. This bit is set if any of the INTVECT bits are set Interrupt Reason The CPU writing a '1' to the bit clears the bit 14:8 7:0 INTVECT USERVECT RW R 14 BC has completed the message list, HALT instruction executed 13 INTREQ instruction executed 12 Memory access failure. This bit also directly drives the MEMFAIL output 11 Asynchronous message is completed, RETAS instruction is executed 10 Transmitter shutdown is set when the core detects that it has been transmitting continuously on the bus for greater than 700s. When set, the BC disables its transmitter 9 Stack pointer overflow or underflow is set if the BC attempts to push more than 256 return addresses onto the stack or pop of a non-existent address from the stack. BC stops operation when this occurs 8 Corrupt instruction list or data table. Illegal command written to the control register, e.g. start instruction while an asynchronous message is active. BC stops operation when this occurs Provides the user provided interrupt reason as set by the instruction parameter v2.0 11 M I L -S TD -1 5 5 3 B B u s C o n t r o l le r C o r e 1 5 5 3 B B C Bus Controller Operation After power-up, the bus controller waits while the CPU sets up the bus controller memory and registers. The memory contains an instruction list, message blocks, and data blocks. Once the instruction list, message blocks, and data blocks are setup, the CPU starts the bus controller. The bus controller works its way through all the message blocks until it reaches the end of the instruction list (Figure 6). The instruction list contains a list of pointers to message blocks. The message block contains the command words transmitted on the 1553B bus and status words received from the 1553B bus. It also contains a pointer to a data block. The data block contains the data transmitted on the 1553B bus, or the data received from the 1553B bus. Instruction List INSTRUCTION PARAMETER INSTRUCTION PARAMETER INSTRUCTION PARAMETER Message Block MSGCMD CW (RTRT RX) CW (RTRT TX) DATAPTR SW (RTRT TX) SW (RTRT RX) TSW Data Block 32 Data Words Figure 6 * BC Memory Usage Ins tr uct i on L is t Table 7 * Instruction Word The instruction list contains pairs of words: an instruction and a parameter. Core1553BBC supports a broad set of instructions allowing branching and sub-routine calls with condition code support. This allows complex instruction lists to be supported. The instruction contains a four-bit OPCODE and five-bit condition code field (Table 7 and Table 8). 15:13 12:8 7:4 3:0 Reserved CONDCODE Reserved OPCODE All of the OPCODES support the condition code field. If the condition is TRUE, then the OPCODE is carried out; otherwise, the BC continues to the next instruction. For RT-to-RT messages, the condition code will be true if the bit is set in either status word or not set in either status word (Table 9 on page 13). Table 8 * Supported Instructions Condition Code Parameter OPCODE Function 0000 0001 0010 NOP DOMSG JUMP N/A Yes Yes 0011 INTR Yes 0100 HALT Yes 0101 DELAY Yes 0110 0111 1000 LOADC WAITC CALL Yes Yes Yes 12 N/A Message Block Address New Instruction Address User interrupt value (Lower 8 bits) User interrupt value (Lower 8 bits) Timer value (Lower 8 bits) Clock value Clock value New Instruction Address Description No operation, jumps to next message Process the message block Jumps to the new message list address Force a BC interrupt Stop the BC Loads the timer with the parameter and waits until the timer reaches zero Loads the BC clock Waits until the BC clock reaches the specified value Jumps to the new message list address and pushes the return address onto the stack. v2.0 M I L -S TD -1 5 5 3 B B u s C o n t r o l le r C o r e 1 5 5 3 B B C Table 8 * Supported Instructions (Continued) OPCODE Function Condition Code Parameter 1001 RET Yes N/A 1010 RETAS Yes N/A 1011 STOREF Yes N/A Illegal N/A N/A Others Description Gets a return instruction address from the stack and jumps to it Gets a return instruction address from the stack and jumps to it. Also clears the ASYNC bit in the status register allowing further ASYNC messages to be accepted Stores the selected flag so that it may be tested at a later stage. The condition code field indicates which flag to store Will halt operation and set the illegal OPCODE interrupt Table 9 * Condition Codes Condition Code Function Description 00000 00001 00010 00011 00100 ALWAYS RESP GBR TF DBA 00101 00110 00111 01000 01001 01010 SSF BUSY BR SR ME SWE 01011 SWAB 01100 01101 01110 10000 10001 10010 10011 10100 ASYNC EXT SFLAG NEVER NORESP NGBR NTF NDBA 10101 10110 10111 NSSF NBUSY NBR 11000 11001 11010 NSR NME NSWE 11011 NOSWAB 11100 11101 11110 Others 0xxxx Others 1xxxx NASYNC NEXT NSFLAG Illegal Illegal Always perform the associated instruction Performs the instruction if there was a response to the previous message Performs the instruction if the previous message was successful Performs the instruction if the Terminal Flag was set in the last received status word Perform the instruction if the Dynamic Bus Acceptance flag was set in the last received status word Performs the instruction if the Sub-system Flag was set in the last received status word Performs the instruction if the Busy bit was set in the last received status word Performs the instruction if the Broadcast Received bit was set in the last received status word Performs the instruction if the Service Request bit was set in the last received status word Performs the instruction if the Message Error bit was set in the last received status word Performs the instruction if the RT address field is incorrect, the instrumentation bit is set, or any of the reserved bits was set in the last received status word Performs the instruction if any bits are set in the last received status word (ignoring the RT address field) Performs the instruction if asynchronous message processing is active Performs the instruction if the External flag input is active '1' Performs the instruction if the previously stored flag bit was set Never performs the associated instruction Performs the instruction if there was no response to the previous message Performs the instruction if the previous message was unsuccessful Performs the instruction if the Terminal Flag was not set in the last received status word Performs the instruction if the Dynamic Bus Acceptance flag was not set in the last received status word Performs the instruction if the Sub-System Flag was not set in the last received status word Performs the instruction if the Busy bit was not set in the last received status word Performs the instruction if the Broadcast Received bit was not set in the last received status word Performs the instruction if the Service Request bit was not set in the last received status word Performs the instruction if the Message Error bit was not set in the last received status word Performs the instruction if the RT address field is correct and the instrumentation bit is not set, and none of the reserved bits are set in the last received status word Performs the instruction if no bits (ignoring the RT address field) are set in the last received status word Performs the instruction if asynchronous message processing is not active Performs the instruction if the External flag input is inactive '0' Performs the instruction if the previously stored flag bit was not set Equivalent to NEVER Equivalent to ALWAYS v2.0 13 M I L -S TD -1 5 5 3 B B u s C o n t r o l le r C o r e 1 5 5 3 B B C Mes sa ge Blo ck An eight-word message block controls each message. The BC reads the 1553B command words from the message block and will write the received status words back to message block. Message blocks must be positioned on an eight-word memory boundary (Table 10). Table 10 * Message Block Offset Contents 0 MSGCMD 1 2 3 4 5 6 7 14 Written by Description CPU Type of 1553B Message Inter-message GAP after this message, 0 to 63s When 000000, it uses the inter-message gap as set by the BC setup register. Longer IMG values can be achieved by using the DELAY 15:10 instruction between messages. The actual IMG may be longer than when set by this register. The BC needs to perform up to six memory accesses during the IMG period. If the backend memory responds slowly, then the IMG may increase '0': Normal Operation 9 '1': The CLOCK value at the mid-point of the data word sync is used as the data for the synchronize with data mode code. Bus to use 8: '0': Bus A '1': Bus B 7:6 Retries on Alternate Bus 0 to 3 5:4 Retries on Bus 0 to 3 0000 0 BC-to-RT 0001 1 RT-to-BC 0110 6 Mode Code with no data 0010 2 Mode Code RT RX with data 0011 3 Mode Code RT TX with data 3:0 0101 5 RT-to-RT 1000 8 Broadcast BC-to-RT 1110 E Broadcast Mode Code RT with no data 1010 A Broadcast Mode Code RX with data 1101 D Broadcast RT-to-RT Others Illegal CW CPU 1553B Command Word. For RT-to-RT messages, this is the RX command word RTRT TX CW CPU RT-to-RT TX 1553B Command Word Data Pointer to memory location containing the 32-word data buffer. Must Messages be on a 32-word boundary, i.e. bits 4:0 are 00000 DATAPTR CPU or BC Mode Code Mode code data word Messages SW BC Received status word. For RT-to-RT messages this is the status word from the TX RT RTRT RX SW BC Received status word from the RX RT for RT-to-RT messages TSW BC Message Transfer Status Word. Provides status information on the message block. The CPU should clear this field when setting up the message block Message Okay 15 '1': Message completed okay with no errors. May have been retried. '0': Message failed after all retries completed 14 No response from RT 13 RT Signaled Message Error 12 1553B Error occurred, encoding, parity, too many words, etc. 11:9 Number of retry attempts to transmit the message (0-6) 8 Unexpected bit set in the status word 7 Got the RT-to-RT RX status word 6 Got the status word, for RT-to-RT got the TX status word Number or data words transmitted or received. 5:0 Note: '000000' indicates 0 and '100000' indicates 32 Reserved -15:0 Not Used v2.0 M I L -S TD -1 5 5 3 B B u s C o n t r o l le r C o r e 1 5 5 3 B B C Det ai led Ope ra ti on Flow Table 11 shows the operations the core goes through in processing a message list containing two messages. The first message is a BC-to-RT transfer of three words, and the second is an RT-to-BC transfer of three words. Table 11 * Typical Operation Time Memory Accesses Operation 1553B Activity Read first Instruction code Read first Instruction parameter Read first MSGCMD Read first CW Wait until the Inter-message gap expired Read the DATAPTR Transmit the command word Read the 1st DW Read the 2nd DW Transmit the 1st data word Read the 3rd DW Transmit the 2nd data word Transmit the 3rd data word Wait for the RT Response Time RT responds with SW Write the SW to memory Write the TSW to memory Read second Instruction code Read second instruction parameter Read second MSGCMD Read second CW Wait until the Inter-message gap expired Read the DATAPTR Wait for the RT Response Time Transmit the command word RT responds with SW Write the SW to memory RT sends 1st data word Write the 1st DW to memory RT sends 2nd data word Write the 2nd DW to memory RT sends 3rd data word Write the 2nd DW to memory Write the TSW to memory Read third Instruction code (HALT) Generate the complete interrupt v2.0 15 M I L -S TD -1 5 5 3 B B u s C o n t r o l le r C o r e 1 5 5 3 B B C E rr or C ondi t ions Core1553BBC monitors bus errors and in most cases will perform automatic retry operations if recovery is possible (Table 12). Table 12 * Error Conditions Error Condition Group Signaling Memory Status Word Action Error 1553B signaling error, parity, Manchester error, too many or to few words, or incorrect SYNC type Message is retried 1553B Loopback Failure. Can occur if an RT responds late, causing the RT response and following command word to corrupt each other on the bus Message is retried Loopback bit set in BC status BC continues to process messages Transmitter Overrun. Internal timer detects the BC has transmitted for greater than 688s BC controller aborts and asserts the transmitter shutdown interrupt Memory Access Failure BC controller aborts and asserts the memory failure interrupt Stack Overflow or Underflow BC controller aborts and asserts the stack overflow interrupt Terminal Flag in SW Sub-system Flag in SW Service Request Flag in SW Broadcast bit is SW Unexpected bit in 1553B status bit set in the TSW. Message is not retried Busy Flag in SW Message Error bit in SW Message is retried Other SW bit Message is retried RT Response No or Late Response Message is retried Miscellaneous Corrupt Instruction List Illegal OPCODE Message block MSGCMD message type bits [3:0] mismatch the provided command word BC controller aborts and asserts the corrupt instruction list interrupt Retry Fails Retries do not correct the error Message Okay bit in TSW not set CPU Interface Start or second asynchronous message command issued while an asynchronous message is active Command is ignored and an illegal command interrupt generated Loop B ack Te st s Core1553BBC performs loop back testing on all of its transmissions; the transmit data is fed back into the receiver, and each transmitted word is compared to the original. If an error is detected, the transmitter shutdown bit is set in the BC status register. To support message timing and minor/major frame timing, Core1553BBC has a built-in real time clock (16-bit) and timer (8-bit) that can be used to synchronize message timing. The real time clock and timer have a programmable resolution of 1s, 4s, 8s, or 32s. Messages can be programmed to be sent at an absolute time or relative to the end of the previous message. Mes sa ge Se quenc e C ont r ol A sy nchr on ous Mes s ages Core1553BBC message sequence control enables it to automatically sequence messages without CPU intervention. It supports conditional jumps and sub-routine calls as well as time control functions. All instructions make use of the condition codes. The condition codes cover error conditions, 1553B status word values, and an external input. Core1553BBC supports CALL and RETURN instructions with the aid of a stack that allows for 255 return addresses to be stored. The stack occupies the top 256 words of memory. 16 Core1553BBC supports asynchronous messages. While idle or when a normal message list is being processed, the CPU can initiate the core to jump to a secondary (asynchronous) message list and process these messages. When complete, the core will go back to the original message list. The asynchronous message list can be started directly by the CPU by writing to the control register. When the current message completes, the core pushes the current LISTPTR address on the stack and load the LISTPTR with the value v2.0 M I L -S TD -1 5 5 3 B B u s C o n t r o l le r C o r e 1 5 5 3 B B C required between each message to read and write to the message block. These six memory accesses directly effect the inter-message gap. The actual IMG will be the largest of the duration of these six memory cycles or the programmed IMG value. specified in the ASYNCPTR. It will execute these instructions until an RETAS instruction is found. At this point, the LISTPTR is reloaded from the stack and the bus controller enters the idle state or resumes the original instruction list. While the asynchronous message list is being processed, the START instruction and further asynchronous events are disabled. They are re-enabled by the RETAS instruction. B us Tr an sc ei v e rs Core1553BBC needs a 1553B transceiver to drive the 1553B bus. Core1553BBC is designed to directly interface to common MIL-STD-1553 transceivers, such as the DDC BU-63147, and the Aeroflex ACT4402. When using ProASICPLUS or Axcelerator, level translators are required to connect the 5V output levels of the 1553B transceivers to the 3.3V input levels of the FPGA. Ret r y Oper at io ns Core1553BBC supports an automatic retry system that retries messages that fail automatically. On detecting an error that can be retried, the BC immediately retries the message. Each message can be retried up to six times. Core1553BBC can be programmed to retry up to three times on the original bus. Then retry up to three times on the alternative bus or to simply retry initially on the alternative bus and then switch buses after each attempt. In addition to the transceiver, a pulse transformer is required for interfacing to the 1553B bus. Figure 7, Figure 8, and Figure 9 on page 18 show the connections required from the Core1553BBC to the transceivers and then to the bus via the pulse transformers. Int er -Me ss age Gap (IMG) Co ntr ol Core1553BBC provides several ways to control the 1553B inter-message gaps. First, a default IMG is programmed into the Core1533BBC control register. Secondly, every message block can be programmed with its own inter-message gap; this specifies the delay to the next message. Finally, the WAITC and DELAY instructions can be used to insert extra delays between messages. D ev el o pm en t S ys t em A complete 1553B Bus controller development system is also available. The Actel part number is "Core1553BBC Eval Board." The development system implements a PCI to 1553B bus controller on a single PCB using an Actel A54SX32A FPGA. The actual IMG gap is also a function of the backend memory access system. There is a six-cycle overhead PCI Target Interface PCI Interface Pulse Transformer 1553B Control Backend Interface Memory Access CPU Interface Memory 64K*16 The PCI target interface uses the Actel CorePCI66 PCI target interface core. Pulse Transceiver Transformer Core1553BBC Actel FPGA Development PCB Figure 7 * Core1553BBC Development System v2.0 17 M I L -S TD -1 5 5 3 B B u s C o n t r o l le r C o r e 1 5 5 3 B B C Ty pi ca l B C S ys t e m core and removes the need for external bus arbitration on the CPU bus. Core1553BBC requires a master CPU to set up the data tables. The CPU needs to be able to access the internal core registers as well as the backend memory. Core1553BBC can be configured in two ways with the CPU shared memory and with its own memory. Alternatively, the core can share the CPU memory as shown in Figure 9. In this case, both the backend memory and CPU interfaces are connected to the CPU bus. The core provides control lines that allow the memory and CPU interfaces to share the same top-level I/O pins. When in this configuration, the core needs to read or write the memory it uses MEMREQn and MEMGNTn signals to arbitrate for the CPU bus before completing the cycle. Memory Backend Interface When configured with its own memory, only the CPU port needs to be connected to the CPU. The CPU accesses the backend memory via Core1553BBC. This configuration also supports using an internal FPGA memory connected to the BUSAINEN BUSAINP BUSAINN BUSAOUTINH BUSAOUTP BUSAOUTN RCVSTBA RXDAIN RXDAIN TXINHA TXDAIN TXDAIN Transceiver CPU Interface CPU BUSBINEN BUSBINP BUSBIN BUSAOUTINH BUSBOUTP BUSBOUTN Pulse Transformer RCVSTBA RXDBIN RXDBIN Pulse Transformer TXINHA TXDBIN TXDBIN Core1553BBC Actel FPGA Memory Backend Interface Figure 8 * Core1553BBC with its Own Memory BUSAINEN BUSAINP BUSAINN BUSAOUTINH BUSAOUTP BUSAOUTN RCVSTBA RXDAIN RXDAIN TXINHA TXDAIN TXDAIN CPU Interface Transceiver Bus Arbritator BUSBINEN BUSBINP BUSBIN BUSAOUTINH BUSBOUTP BUSBOUTN CPU Core1553BBC Actel FPGA Figure 9 * Core1553BBC Using Shared Memory 18 v2.0 Pulse Transformer RCVSTBA RXDBIN RXDBIN TXINHA TXDBIN TXDBIN Pulse Transformer M I L -S TD -1 5 5 3 B B u s C o n t r o l le r C o r e 1 5 5 3 B B C Sp e ci f i c a t i on s CP U Int erf ace Ti m ing CPU Interface Register Read Cycle CPUCSN CPURDN CPUADDR ADDR CPUMEM Tpd Tpd CPUDOUT Data CPUDEN CPUWAITN CPU Interface Register Write Cycle CLK CPUCSN CPUWRN[1:0] CPUADDR ADDR CPUMEM CPUDIN Data CPUWAITN Write done CPU Interface Memory Read Cycle CLK CPUCSN CPURDN CPUADDR ADDR CPUMEM CPUDOUT Data CPUDEN Tpd Tpd CPUWAITN CPU Interface Memory Write Cycle CLK CPUCSN CPUWRN CPUADDR ADDR CPUMEM CPUDIN Data Write Tpd Tpd CPUWAITN v2.0 19 M I L -S TD -1 5 5 3 B B u s C o n t r o l le r C o r e 1 5 5 3 B B C CPUWAITn will be driven low for a minimum of three clock cycles for write cycles and four for read cycles and the number of clock cycles the memory backend delays the assertion of MEMGNTn and asserts MEMWAITn. CPUWAITn is driven low by CPURDn/CPUWRn becoming active and returns high on the falling clock edge after data is valid. The CPU interface signals are internally synchronized to the Core1553BBC master clock. If these inputs are asynchronous, then CPUCSn, CPUADDR, CPUDATA should be valid/invalid before CPUWRn and remain valid after CPUWRn. CPUWRn must be active for at least one clock cycle. Interrupt Timing CLK Tiack INTOUT CPURDN Mem or y T im i ng Asynchronous Memory Read Cycle CLK MEMREQn Tsu MEMGNTn MEMCEN MEMDEN MEMCSn MEMADDR Tsu MEMDIN MEMRDn Tsu Tsu Tsu Tsu MEMWAITn Asynchronous Memory Write Cycle CLK MEMREQn Tsu MEMGNTn MEMCEN MEMDEN MEMCSn MEMADDR MEMDOUT MEMWRn MEMWAITn 20 v2.0 M I L -S TD -1 5 5 3 B B u s C o n t r o l le r C o r e 1 5 5 3 B B C Synchronous Memory Read Cycle CLK MEMREQn Tsu MEMGNTn MEMCEN MEMDEN MEMCSn MEMRDn MEMADDR Tsu MEMDIN Tsu Tsu MEMWAITn Synchronous Memory Write Cycle CLK MEMREQn Tsu MEMGNTn MEMCEN MEMDEN MEMCSn MEMADDR MEMDOUT MEMWRn Tsu Tsu MEMWAITn Synchronous Memory Read Cycle with MEMGNTn Active CLK MEMREQn MEMGNTn MEMCEN MEMDEN MEMCSn MEMRDn MEMADDR Tsu MEMDIN MEMWAITn v2.0 21 M I L -S TD -1 5 5 3 B B u s C o n t r o l le r C o r e 1 5 5 3 B B C Synchronous Memory Write Cycle with MEMGNTn Active CLK MEMREQn MEMGNTn MEMCEN MEMDEN MEMCSn MEMADDR MEMDOUT MEMWRn MEMWAITn Memory Grant Time-out CLK Timeout MEMREQn MEMGNTn MEMCEN MEMDEN MEMCSn MEMRDn/WRn MEMWAITn MEMFAIL Memory Wait Time-out CLK Timeout MEMREQn MEMGNTn MEMCEN MEMDEN MEMCSn MEMRDn/WRn Tsu MEMWAITn MEMFAIL Cl ock Req uir em en ts To meet the 1553B transmission bit rate requirements, the Core1553BBC clock input must be 12 MHz, 16 MHz, 20 MHz, or 24 MHz with a tolerance of 0.01%. 22 v2.0 M I L -S TD -1 5 5 3 B B u s C o n t r o l le r C o r e 1 5 5 3 B B C O r d e r i n g I nf o r m a t i o n Core1553BBC can be ordered through your local Actel sales representative. It should be ordered using the following number scheme: Core1553BBC-XX, where XX is (Table 13): The Evaluation board can also be ordered using the following order code "Core1553BBC Eval Board." Table 13 * Ordering Codes XX Description EV Evaluation Version SN Single-use Netlist for use on Actel devices AN Netlist for unlimited use on Actel devices AR RTL for unlimited use on Actel devices UR RTL for unlimited use and not restricted to Actel devices D at a s h e et C a t e g o r i e s P rod uct D efin it ion This version of the datasheet is the definition of the product. A prototype may or may not be available. Data presented is subject to significant changes. P rod uct ion (un m ar ked) This version of the datasheet contains complete information on the final core. All components are fully operational and the core has been thoroughly verified. Adv anc ed This version of the datasheet provides nearly complete information for a prototype IP product. Code is fully operational, but may not support all features expected in the production release. A prototype core and a preliminary testbench are available. v2.0 23 Actel, the Actel logo, Libero, and DirectCore are registered trademarks of Actel Corporation. All other trademarks are the property of their owners. http://www.actel.com Actel Corporation Actel Europe Ltd. Actel Japan Actel Hong Kong 955 East Arques Avenue Sunnyvale, California 94086 USA Tel: (408) 739-1010 Fax: (408) 739-1540 Dunlop House, Riverside Way Camberley, Surrey GU15 3YL United Kingdom Tel: +44 (0)1276 401450 Fax: +44 (0)1276 401490 EXOS Ebisu Bldg. 4F 1-24-14 Ebisu Shibuya-ku Tokyo 150 Japan Tel: +81 03-3445-7671 Fax: +81 03-3445-7668 39th Floor One Pacific Place 88 Queensway Admiralty, Hong Kong Tel: 852-22735712 51700015-0/3.02