EFM32 Giant Gecko Series 1 Family

EFM32GG11 Family Data Sheet

The EFM32 Giant Gecko Series 1 MCUs are the world’s most

energy-friendly microcontrollers, featuring new connectivity interfa-

ces and user interface features.

EFM32GG11 includes a powerful 32-bit ARM® Cortex®-M4 and provides robust security

via a unique cryptographic hardware engine supporting AES, ECC, SHA, and True Ran-

dom Number Generator (TRNG). New features include an SD/MMC/SDIO controller, Oc-

tal/Quad-SPI memory controller, 10/100 Ethernet MAC, CAN bus controller, highly robust

• ARM Cortex-M4 at 72 MHz

• Ultra low energy operation

• 80 µA/MHz in Energy Mode 0 (EM0)

• 2.1 μA EM2 Deep Sleep current (RTCC

running with state and RAM retention)

• Octal/Quad-SPI memory interface w/ XIP

• SD/MMC/SDIO Host Controller

• 10/100 Ethernet MAC with 802.3az EEE,

• Dual CAN 2.0 Bus Controller

• 5 V tolerant I/O

• Smart energy meters

• Industrial and factory automation

• Home automation and security

• Mid- and high-tier wearables

• IoT devices

32-bit bus

Debug Interface

LDMA

CRYPTO

Energy Management

Clock Management

Backup Domain

Peripheral Reflex System

Pin Wakeup

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The EFM32GG11 highlighted features are listed below.

• High performance 32-bit processor @ up to 72 MHz

RTCC running from LFRCO)

• Dual-bank with read-while-write support

• 256 kB with ECC (SEC-DED)

• Supports 3 V and 1.8 V memories

• 1/2/4/8-bit data bus

• Quad-SPI Execute In Place (XIP)

• Patent-pending Low-Energy Mode (LEM)

• SD/MMC/SDIO Host Controller

• SD v3.01, SDIO v3.0 and MMC v4.51

• 1/4/8-bit bus width

• 10/100 Ethernet MAC with MII/RMII interface

• IEEE1588-2008 precision time stamping

• Energy Efficient Ethernet (802.3az)

• Up to 2× CAN Bus Controller

• Version 2.0A and 2.0B up to 1 Mbps

• 6× Universal Synchronous/Asynchronous Receiver/ Trans-

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EFM32GG11B840F1024GL152-A 1024 512 Yes Yes Yes Yes Yes Yes 121 BGA152 -40 to +85°C

EFM32GG11B840F1024IL152-A 1024 512 Yes Yes Yes Yes Yes Yes 121 BGA152 -40 to +125°C

EFM32GG11B820F2048GL120-A 2048 512 Yes Yes Yes Yes Yes Yes 95 BGA120 -40 to +85°C

EFM32GG11B820F2048IL120-A 2048 512 Yes Yes Yes Yes Yes Yes 95 BGA120 -40 to +125°C

EFM32GG11B840F1024GL120-A 1024 512 Yes Yes Yes Yes Yes Yes 95 BGA120 -40 to +85°C

EFM32GG11B840F1024IL120-A 1024 512 Yes Yes Yes Yes Yes Yes 95 BGA120 -40 to +125°C

EFM32GG11B820F2048GQ100-A 2048 512 Yes Yes Yes Yes Yes Yes 80 QFP100 -40 to +85°C

EFM32GG11B820F2048IQ100-A 2048 512 Yes Yes Yes Yes Yes Yes 80 QFP100 -40 to +125°C

EFM32GG11B840F1024GQ100-A 1024 512 Yes Yes Yes Yes Yes Yes 80 QFP100 -40 to +85°C

EFM32GG11B840F1024IQ100-A 1024 512 Yes Yes Yes Yes Yes Yes 80 QFP100 -40 to +125°C

EFM32GG11B840F1024IQ64-A 1024 512 Yes Yes Yes Yes Yes Yes 47 QFP64 -40 to +125°C

EFM32GG11B840F1024IM64-A 1024 512 Yes Yes Yes Yes Yes Yes 50 QFN64 -40 to +125°C

EFM32GG11B520F2048GL120-A 2048 512 Yes No No No No Yes 95 BGA120 -40 to +85°C

EFM32GG11B510F2048GL120-A 2048 384 Yes No No No No Yes 95 BGA120 -40 to +85°C

EFM32GG11B520F2048IL120-A 2048 512 Yes No No No No Yes 95 BGA120 -40 to +125°C

EFM32GG11B510F2048IL120-A 2048 384 Yes No No No No Yes 95 BGA120 -40 to +125°C

EFM32GG11B520F2048GQ100-A 2048 512 Yes No No No No Yes 83 QFP100 -40 to +85°C

EFM32GG11B510F2048GQ100-A 2048 384 Yes No No No No Yes 83 QFP100 -40 to +85°C

EFM32GG11B520F2048IQ100-A 2048 512 Yes No No No No Yes 83 QFP100 -40 to +125°C

EFM32GG11B510F2048IQ100-A 2048 384 Yes No No No No Yes 83 QFP100 -40 to +125°C

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EFM32GG11B520F2048GQ64-A 2048 512 Yes No No No No Yes 50 QFP64 -40 to +85°C

EFM32GG11B510F2048GQ64-A 2048 384 Yes No No No No Yes 50 QFP64 -40 to +85°C

EFM32GG11B520F2048GM64-A 2048 512 Yes No No No No Yes 53 QFN64 -40 to +85°C

EFM32GG11B510F2048GM64-A 2048 384 Yes No No No No Yes 53 QFN64 -40 to +85°C

EFM32GG11B520F2048IQ64-A 2048 512 Yes No No No No Yes 50 QFP64 -40 to +125°C

EFM32GG11B510F2048IQ64-A 2048 384 Yes No No No No Yes 50 QFP64 -40 to +125°C

EFM32GG11B520F2048IM64-A 2048 512 Yes No No No No Yes 53 QFN64 -40 to +125°C

EFM32GG11B510F2048IM64-A 2048 384 Yes No No No No Yes 53 QFN64 -40 to +125°C

EFM32GG11B420F2048GL120-A 2048 512 No Yes Yes Yes Yes Yes 93 BGA120 -40 to +85°C

EFM32GG11B420F2048GM64-A 2048 512 No Yes Yes Yes Yes Yes 53 QFN64 -40 to +85°C

EFM32GG11B420F2048IQ64-A 2048 512 No Yes Yes Yes Yes Yes 50 QFP64 -40 to +125°C

EFM32GG11B420F2048IM64-A 2048 512 No Yes Yes Yes Yes Yes 53 QFN64 -40 to +125°C

EFM32GG11B320F2048GL112-A 2048 512 No No No No No Yes 90 BGA112 -40 to +85°C

EFM32GG11B310F2048GL112-A 2048 384 No No No No No Yes 90 BGA112 -40 to +85°C

EFM32GG11B320F2048GQ100-A 2048 512 No No No No No Yes 86 QFP100 -40 to +85°C

EFM32GG11B310F2048GQ100-A 2048 384 No No No No No Yes 86 QFP100 -40 to +85°C

EFM32GG11B120F2048GQ64-A 2048 512 No No No No No No 53 QFP64 -40 to +85°C

EFM32GG11B110F2048GQ64-A 2048 384 No No No No No No 53 QFP64 -40 to +85°C

EFM32GG11B120F2048GM64-A 2048 512 No No No No No No 56 QFN64 -40 to +85°C

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Table of Contents

1. Feature List ................................2

2. Ordering Information ............................4

3. System Overview .............................11

3.6.6 Quad-SPI Flash Controller (QSPI)

The QSPI provides access to to a wide range of flash devices with wide I/O busses. The I/O and clocking configuration is flexible and

supports many types of devices. Up to 8-bit wide interfaces are supported. The QSPI handles opcodes, status flag polling, and timing

configuration automatically.

The external flash memory is mapped directly to internal memory to allow random access to any word in the flash and direct code exe-

cution. An integrated instruction cache minimizes latency and allows efficient code execution. Execute in Place (XIP) is supported for

devices with this feature.

Large data chunks can be transferred with DMA as efficiently as possible with high throughput and minimimal bus load, utilizing an

3.6.7 SDIO Host Controller (SDIO)

The SDIO is an SD3.01 / SDIO3.0 / eMMC4.51-compliant Host Controller interface for transferring data to and from SD/MMC/SDIO

devices. The module conforms to the SD Host Controller Standard Specification Version 3.00. The Host Controller handles

SDIO/SD/MMC Protocol at the transmission level, packing data, adding cyclic redundancy check (CRC), Start/End bits, and checking

for transaction format correctness.

3.6.8 Universal Serial Bus (USB)

The USB is a full-speed/low-speed USB 2.0 compliant host/device controller. The USB can be used in device and host-only configura-

3.6.9 Ethernet (ETH)

The Ethernet peripheral is compliant with IEEE 802.3-2002 for Ethernet MAC. It supports 802.1AS and IEEE 1588 precision clock syn-

chronization protocol, as well as 802.3az Energy Efficient Ethernet. The ETH supports a wide variety of frame formats and standard

operating modes such as MII/RMII. Direct Memory Access (DMA) support makes it possible to transmit and receive large frames at

high data rates with minimal CPU overhead. The Ethernet peripheral supports 10 Mbps and 100 Mbps operation, and includes a total of

8 kB of dedicated dual-port RAM FIFO (4 kB for TX and 4 kB for RX).

3.6.10 Controller Area Network (CAN)

The CAN peripheral provides support for communication at up to 1 Mbps over CAN protocol version 2.0 part A and B. It includes 32

message objects with independent identifier masks and retains message RAM in EM2. Automatic retransmittion may be disabled in

order to support Time Triggered CAN applications.

The Low Energy Sensor Interface LESENSETM is a highly configurable sensor interface with support for up to 16 individually configura-

ble sensors. By controlling the analog comparators, ADC, and DAC, LESENSE is capable of supporting a wide range of sensors and

measurement schemes, and can for instance measure LC sensors, resistive sensors and capacitive sensors. LESENSE also includes a

programmable finite state machine which enables simple processing of measurement results without CPU intervention. LESENSE is

available in energy mode EM2, in addition to EM0 and EM1, making it ideal for sensor monitoring in applications with a strict energy

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3.7 Security Features

3.7.1 GPCRC (General Purpose Cyclic Redundancy Check)

The GPCRC module implements a Cyclic Redundancy Check (CRC) function. It supports both 32-bit and 16-bit polynomials. The sup-

ported 32-bit polynomial is 0x04C11DB7 (IEEE 802.3), while the 16-bit polynomial can be programmed to any value, depending on the

needs of the application.

The CRYPTO module allows fast processing of GCM (AES), ECC and SHA with little CPU intervention. CRYPTO also provides trigger

signals for DMA read and write operations.

3.7.3 True Random Number Generator (TRNG)

The TRNG module is a non-deterministic random number generator based on a full hardware solution. The TRNG is validated with

NIST800-22 and AIS-31 test suites as well as being suitable for FIPS 140-2 certification (for the purposes of cryptographic key genera-

3.7.4 Security Management Unit (SMU)

The Security Management Unit (SMU) allows software to set up fine-grained security for peripheral access, which is not possible in the

Memory Protection Unit (MPU). Peripherals may be secured by hardware on an individual basis, such that only priveleged accesses to

the peripheral's register interface will be allowed. When an access fault occurs, the SMU reports the specific peripheral involved and

3.8.2 Analog Comparator (ACMP)

The Analog Comparator is used to compare the voltage of two analog inputs, with a digital output indicating which input voltage is high-

er. Inputs are selected from among internal references and external pins. The tradeoff between response time and current consumption

is configurable by software. Two 6-bit reference dividers allow for a wide range of internally-programmable reference sources. The

ACMP can also be used to monitor the supply voltage. An interrupt can be generated when the supply falls below or rises above the

programmable threshold.

3.8.3 Analog to Digital Converter (ADC)

The ADC is a Successive Approximation Register (SAR) architecture, with a resolution of up to 12 bits at up to 1 Msps. The output

sample resolution is configurable and additional resolution is possible using integrated hardware for averaging over multiple samples.

The ADC includes integrated voltage references and an integrated temperature sensor. Inputs are selectable from a wide range of

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3.8.4 Capacitive Sense (CSEN)

The CSEN module is a dedicated Capacitive Sensing block for implementing touch-sensitive user interface elements such a switches

and sliders. The CSEN module uses a charge ramping measurement technique, which provides robust sensing even in adverse condi-

tions including radiated noise and moisture. The module can be configured to take measurements on a single port pin or scan through

multiple pins and store results to memory through DMA. Several channels can also be shorted together to measure the combined ca-

ksps, 12-bit converter. The opamps are used in conjunction with the VDAC, to provide output buffering. One opamp is used per single-

ended channel, or two opamps are used to provide differential outputs. The VDAC may be used for a number of different applications

such as sensor interfaces or sound output. The VDAC can generate high-resolution analog signals while the MCU is operating at low

frequencies and with low total power consumption. Using DMA and a timer, the VDAC can be used to generate waveforms without any

CPU intervention. The VDAC is available in all energy modes down to and including EM3.

3.8.7 Operational Amplifiers

The opamps are low power amplifiers with a high degree of flexibility targeting a wide variety of standard opamp application areas, and

are available down to EM3. With flexible built-in programming for gain and interconnection they can be configured to support multiple

common opamp functions. All pins are also available externally for filter configurations. Each opamp has a rail to rail input and a rail to

rail output. They can be used in conjunction with the VDAC module or in stand-alone configurations. The opamps save energy, PCB

the device on a regular basis for updating data.

3.9 Reset Management Unit (RMU)

The RMU is responsible for handling reset of the EFM32GG11. A wide range of reset sources are available, including several power

supply monitors, pin reset, software controlled reset, core lockup reset, and watchdog reset.

3.10 Core and Memory

3.10.1 Processor Core

The ARM Cortex-M processor includes a 32-bit RISC processor integrating the following features and tasks in the system:

• ARM Cortex-M4 RISC processor with FPU achieving 1.25 Dhrystone MIPS/MHz

• Memory Protection Unit (MPU) supporting up to 8 memory segments

• Embedded Trace Macrocell (ETM) for real-time trace and debug

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3.10.2 Memory System Controller (MSC)

The Memory System Controller (MSC) is the program memory unit of the microcontroller. The flash memory is readable and writable

from both the Cortex-M and DMA. The flash memory is divided into two blocks; the main block and the information block. Program code

is normally written to the main block, whereas the information block is available for special user data and flash lock bits. There is also a

read-only page in the information block containing system and device calibration data. Read and write operations are supported in en-

3.10.4 Bootloader

All devices come pre-programmed with a UART bootloader. This bootloader resides in flash and can be erased if it is not needed. More

Silicon Labs website (www.silabs.com/32bit-appnotes) or within Simplicity Studio in the [Documentation] area.

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3.11 Memory Map

The EFM32GG11 memory map is shown in the figures below. RAM and flash sizes are for the largest memory configuration.

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3.12 Configuration Summary

The features of the EFM32GG11 are a subset of the feature set described in the device reference manual. The table below describes

device specific implementation of the features. Remaining modules support full configuration.

Table 3.2. Configuration Summary

Module Configuration Pin Connections

USART0 IrDA, SmartCard US0_TX, US0_RX, US0_CLK, US0_CS

USART1 I2S, SmartCard US1_TX, US1_RX, US1_CLK, US1_CS

USART2 IrDA, SmartCard, High-Speed US2_TX, US2_RX, US2_CLK, US2_CS

USART3 I2S, SmartCard US3_TX, US3_RX, US3_CLK, US3_CS

TIMER4 with DTI TIM4_CC[2:0], TIM4_CDTI[2:0]

TIMER5 - TIM5_CC[2:0]

TIMER6 with DTI TIM6_CC[2:0], TIM6_CDTI[2:0]

WTIMER0 with DTI WTIM0_CC[2:0], WTIM0_CDTI[2:0]

WTIMER1 - WTIM1_CC[3:0]

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• Typical values are based on TAMB=25 °C and VDD= 3.3 V, by production test and/or technology characterization.

• Minimum and maximum values represent the worst conditions across supply voltage, process variation, and operating temperature,

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4.1.1 Absolute Maximum Ratings

Stresses above those listed below may cause permanent damage to the device. This is a stress rating only and functional operation of

the devices at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure

to maximum rating conditions for extended periods may affect device reliability. For more information on the available quality and relia-

bility data, see the Quality and Reliability Monitor Report at http://www.silabs.com/support/quality/pages/default.aspx.

Voltage ramp rate on any

supply pin

DC voltage on any GPIO pin VDIGPIN 5V tolerant GPIO pins1 2 3-0.3 — Min of 5.25

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4.1.2 Operating Conditions

When assigning supply sources, the following requirements must be observed:

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4.1.7 Current Consumption

4.1.7.1 Current Consumption 3.3 V without DC-DC Converter

Unless otherwise indicated, typical conditions are: VREGVDD = AVDD = DVDD = 3.3 V. T = 25 °C. DCDC is off. Minimum and maxi-

mum values in this table represent the worst conditions across supply voltage and process variation at T = 25 °C.

Parameter Symbol Test Condition Min Typ Max Unit

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Current consumption in EM2

— 3.9 — µA

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4.1.7.2 Current Consumption 3.3 V using DC-DC Converter

Unless otherwise indicated, typical conditions are: VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = 1.8 V DC-DC output. T = 25 °C.

Minimum and maximum values in this table represent the worst conditions across supply voltage and process variation at T = 25 °C.

Parameter Symbol Test Condition Min Typ Max Unit

Current consumption in EM0

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Current consumption in EM0

Current consumption in EM0

mode with all peripherals dis-

abled and voltage scaling

enabled, DCDC in LP mode3

Current consumption in EM1

mode with all peripherals dis-

abled, DCDC in Low Noise

Current consumption in EM1

mode with all peripherals dis-

abled, DCDC in Low Power

mode3

Current consumption in EM1

mode with all peripherals dis-