High Voltage Latch-Up Proof,
Dual SPDT Switches
Data Sheet
ADG5236
Rev. B Document Feedback
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Technical Support www.analog.com
FEATURES
Latch-up immune under all circumstances
2.5 pF off source capacitance
12 pF off drain capacitance
−0.6 pC charge injection
Low leakage: 0.4 nA maximum at 85°C
±9 V to ±22 V dual-supply operation
9 V to 40 V single-supply operation
48 V supply maximum ratings
Fully specified at ±15 V, ±20 V, +12 V, and +36 V
VSS to VDD analog signal range
APPLICATIONS
High voltage signal routing
Automatic test equipment
Analog front-end circuits
Precision data acquisition
Industrial instrumentation
Amplifier gain select
Relay replacement
FUNCTIONAL BLOCK DIAGRAMS
ADG5236
S1A
S1B
IN1
S2A
S2B
IN2
D1
D2
SWITCHES SHOWN FOR A LOGIC 1 INPUT.
09769-001
Figure 1. TSSOP Package
ADG5236
S2A
D2
S2B
S1A
D1
S1B
IN2 ENIN1
LOGIC
SWITCHES SHOWN FOR A LOGIC 1 INPUT.
09769-002
Figure 2. LFCSP Package
GENERAL DESCRIPTION
The ADG5236 is a monolithic CMOS device containing two
independently selectable single-pole/double throw (SPDT)
switches. An EN input on the LFCSP package enables or
disables the device. When disabled, all channels switch off. Each
switch conducts equally well in both directions when on and
has an input signal range that extends to the supplies. In the off
condition, signal levels up to the supplies are blocked. Both
switches exhibit break-before-make switching action for use in
multiplexer applications.
The ultralow capacitance and charge injection of these switches
make them ideal solutions for data acquisition and sample-and-
hold applications, where low glitch and fast settling are required.
Fast switching speed together with high signal bandwidth make
the device suitable for video signal switching.
PRODUCT HIGHLIGHTS
1. Trench Isolation Guards Against Latch-Up.
A dielectric trench separates the P and N channel
transistors thereby preventing latch-up even under severe
overvoltage conditions.
2. Ultralow Capacitance and <1 pC Charge Injection.
3. Dual-Supply Operation.
For applications where the analog signal is bipolar, the
ADG5236 can be operated from dual supplies up to ±22 V.
4. Single-Supply Operation.
For applications where the analog signal is unipolar, the
ADG5236 can be operated from a single rail power supply
up to 40 V.
5. 3 V Logic-Compatible Digital Inputs.
VINH = 2.0 V, VINL = 0.8 V.
6. No VL Logic Power Supply Required.
ADG5236 Data Sheet
Rev. B | Page 2 of 20
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagrams ............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
±15 V Dual Supply ....................................................................... 3
±20 V Dual Supply ....................................................................... 4
12 V Single Supply ........................................................................ 5
36 V Single Supply ........................................................................ 6
Continuous Current per Channel, Sx or Dx ............................. 7
Absolute Maximum Ratings ............................................................8
ESD Caution...................................................................................8
Pin Configurations and Function Descriptions ............................9
Truth Tables for Switches .............................................................9
Typical Performance Characteristics ........................................... 10
Test Circuits ..................................................................................... 14
Terminology .................................................................................... 16
Trench Isolation .............................................................................. 17
Applications Information .............................................................. 18
Outline Dimensions ....................................................................... 19
Ordering Guide .......................................................................... 19
REVISION HISTORY
11/13—Rev. A to Rev. B
Changes to Features and Applications Sections ........................... 1
Changes to Figure 23 ...................................................................... 13
4/12—Rev. 0 to Rev. A
Updated Outline Dimensions ....................................................... 19
Changes to Ordering Guide .......................................................... 19
7/11—Revision 0: Initial Version
Data Sheet ADG5236
Rev. B | Page 3 of 20
SPECIFICATIONS
±15 V DUAL SUPPLY
VDD = +15 V ± 10%, VSS = −15 V ± 10%, GND = 0 V, unless otherwise noted.
Table 1.
Parameter 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range VDD to VSS V max
On Resistance, RON 160 Ω typ VS = ±10 V, IS = −1 mA, see Figure 25
200 250 280 Ω max VDD = +13.5 V, VSS = −13.5 V
On-Resistance Match
Between Channels, ∆RON
1.4 Ω typ VS = ±10 V, IS = −1 mA
8 9 10 Ω max
On-Resistance Flatness, RFLAT (ON) 38 Ω typ VS = ±10 V, IS = −1 mA
50
70
Ω max
LEAKAGE CURRENTS VDD = +16.5 V, VSS = −16.5 V
Source Off Leakage, IS (Off ) 0.01 nA typ VS = ±10 V, VD =
10 V, see Figure 27
0.1 0.2 0.4 nA max
Drain Off Leakage, ID (Off ) 0.01 nA typ VS = ±10 V, VD =
10 V, see Figure 27
0.1 0.4 1.2 nA max
Channel On Leakage, ID (On), IS (On) 0.02 nA typ VS = VD = ±10 V, see Figure 24
0.2
1.2
nA max
DIGITAL INPUTS
Input High Voltage, VINH 2.0 V min
Input Low Voltage, VINL 0.8 V max
Input Current, IINL or IINH 0.002 µA typ VIN = VGND or VDD
±0.1 µA max
Digital Input Capacitance, C
IN
3
pF typ
DYNAMIC CHARACTERISTICS1
Transition Time, tTRANSITION 150 ns typ RL = 300 Ω, CL = 35 pF
230 280 315 ns max VS = 10 V, see Figure 30
tON 170 ns typ RL = 300 Ω, CL = 35 pF
215 265 300 ns max VS = 10 V, see Figure 32
tOFF 160 ns typ RL = 300 Ω, CL = 35 pF
185 205 225 ns max VS = 10 V, see Figure 32
Break-Before-Make Time Delay, tD 75 ns typ RL = 300 Ω, CL = 35 pF
30
ns min
V
S1
= V
S2
= 10 V, see Figure 31
Charge Injection, QINJ −0.6 pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF,
see Figure 33
Off Isolation −85 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz,
see Figure 28
Channel-to-Channel Crosstalk
−85
dB typ
R
L
= 50 Ω, C
L
= 5 pF, f = 1 MHz,
see Figure 26
−3 dB Bandwidth 266 MHz typ RL = 50 Ω, CL = 5 pF, see Figure 29
Insertion Loss −7 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz,
see Figure 29
CS (Off ) 2.5 pF typ VS = 0 V, f = 1 MHz
C
D
(Off )
12
pF typ
V
S
= 0 V, f = 1 MHz
CD (On), CS (On) 15 pF typ VS = 0 V, f = 1 MHz
ADG5236 Data Sheet
Rev. B | Page 4 of 20
Parameter 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments
POWER REQUIREMENTS VDD = +16.5 V, VSS = −16.5 V
IDD 45 µA typ Digital inputs = 0 V or VDD
55 70 µA max
ISS 0.001 µA typ Digital inputs = 0 V or VDD
1
µA max
VDD/VSS ±9/±22 V min/V max GND = 0 V
1 Guaranteed by design; not subject to production test.
±20 V DUAL SUPPLY
VDD = +20 V ± 10%, VSS = −20 V ± 10%, GND = 0 V, unless otherwise noted.
Table 2.
Parameter 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range VDD to VSS V max
On Resistance, RON 140 Ω typ VS = ±15 V, IS = −1 mA, see Figure 25
160 200 230 Ω max VDD = +18 V, VSS = −18 V
On-Resistance Match
Between Channels, ∆RON
1.3 Ω typ VS = ±15 V, IS = −1 mA
8 9 10 Ω max
On-Resistance Flatness, RFLAT (ON) 33 Ω typ VS = ±15 V, IS = −1 mA
45 55 60 Ω max
LEAKAGE CURRENTS VDD = +22 V, VSS = −22 V
Source Off Leakage, IS (Off ) 0.01 nA typ VS = ±15 V, VD =
15 V, see Figure 27
0.1 0.2 0.4 nA max
Drain Off Leakage, ID (Off ) 0.01 nA typ VS = ±15 V, VD =
15 V, see Figure 27
0.1
0.4
1.2
nA max
Channel On Leakage, ID (On), IS (On) 0.02 nA typ VS = VD = ±15 V, see Figure 24
0.2 0.4 1.2 nA max
DIGITAL INPUTS
Input High Voltage, VINH 2.0 V min
Input Low Voltage, VINL 0.8 V max
Input Current, IINL or IINH 0.002 µA typ VIN = VGND or VDD
±0.1
µA max
Digital Input Capacitance, CIN 3 pF typ
DYNAMIC CHARACTERISTICS1
Transition Time, tTRANSITION 150 ns typ RL = 300 Ω, CL = 35 pF
210 260 290 ns max VS = 10 V, see Figure 30
tON 150 ns typ RL = 300 Ω, CL = 35 pF
190 235 267 ns max VS = 10 V, see Figure 32
tOFF 155 ns typ RL = 300 Ω, CL = 35 pF
180 200 215 ns max VS = 10 V, see Figure 32
Break-Before-Make Time Delay, tD 60 ns typ RL = 300 Ω, CL = 35 pF
30 ns min VS1 = VS2 = 10 V, see Figure 31
Charge Injection, QINJ −0.6 pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF, see
Figure 33
Off Isolation −85 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz,
see Figure 28
Channel-to-Channel Crosstalk
−85
dB typ
R
L
= 50 Ω, C
L
= 5 pF, f = 1 MHz,
see Figure 26
−3 dB Bandwidth 266 MHz typ RL = 50 Ω, CL = 5 pF, see Figure 29
Insertion Loss −7 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz,
see Figure 29
Data Sheet ADG5236
Rev. B | Page 5 of 20
Parameter 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments
CS (Off ) 2.5 pF typ VS = 0 V, f = 1 MHz
CD (Off ) 12 pF typ VS = 0 V, f = 1 MHz
CD (On), CS (On) 15 pF typ VS = 0 V, f = 1 MHz
POWER REQUIREMENTS VDD = +22 V, VSS = −22 V
IDD 50 µA typ Digital inputs = 0 V or VDD
70 110 µA max
ISS 0.001 µA typ Digital inputs = 0 V or VDD
1
µA max
VDD/VSS ±9/±22 V min/V max GND = 0 V
1 Guaranteed by design; not subject to production test.
12 V SINGLE SUPPLY
VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.
Table 3.
Parameter 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range 0 V to VDD V max
On Resistance, RON 350 Ω typ VS = 0 V to 10 V, IS = −1 mA, see
Figure 25
500 610 700 Ω max VDD = 10.8 V, VSS = 0 V
On-Resistance Match
Between Channels, ∆RON
3
Ω typ VS = 0 V to 10 V, IS = −1 mA
20 21 22 Ω max
On-Resistance Flatness, RFLAT (ON) 145 Ω typ VS = 0 V to 10 V, IS = −1 mA
280 335 370 Ω max
LEAKAGE CURRENTS VDD = 13.2 V, VSS = 0 V
Source Off Leakage, IS (Off ) 0.01 nA typ VS = 1 V/10 V, VD = 10 V/1 V,
see Figure 27
0.1
0.2
0.4
nA max
Drain Off Leakage, ID (Off ) 0.01 nA typ VS = 1 V/10 V, VD = 10 V/1 V,
see Figure 27
0.1 0.4 1.2 nA max
Channel On Leakage, ID (On), IS (On) 0.02 nA typ VS = VD = 1 V/10 V, see Figure 24
0.2 0.4 1.2 nA max
DIGITAL INPUTS
Input High Voltage, VINH 2.0 V min
Input Low Voltage, VINL 0.8 V max
Input Current, IINL or IINH 0.002 µA typ VIN = VGND or VDD
±0.1 µA max
Digital Input Capacitance, CIN 3 pF typ
DYNAMIC CHARACTERISTICS1
Transition Time, tTRANSITION 220 ns typ RL = 300 Ω, CL = 35 pF
390 430 490 ns max VS = 8 V, see Figure 30
tON 275 ns typ RL = 300 Ω, CL = 35 pF
380 440 510 ns max VS = 8 V, see Figure 32
tOFF 160 ns typ RL = 300 Ω, CL = 35 pF
195 225 245 ns max VS = 8 V, see Figure 32
Break-Before-Make Time Delay, tD 145 ns typ RL = 300 Ω, CL = 35 pF
65 ns min VS1 = VS2 = 8 V, see Figure 31
Charge Injection, QINJ −0.6 pC typ VS = 6 V, RS = 0 Ω, CL = 1 nF, see
Figure 33
ADG5236 Data Sheet
Rev. B | Page 6 of 20
Parameter 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments
Off Isolation −90 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz,
see Figure 28
Channel-to-Channel Crosstalk −90 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz,
see Figure 26
−3 dB Bandwidth
185
MHz typ
R
L
= 50 Ω, C
L
= 5 pF, see Figure 29
Insertion Loss −11 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz,
see Figure 29
CS (Off ) 3 pF typ VS = 6 V, f = 1 MHz
CD (Off ) 16 pF typ VS = 6 V, f = 1 MHz
CD (On), CS (On) 16 pF typ VS = 6 V, f = 1 MHz
POWER REQUIREMENTS VDD = 13.2 V
IDD 40 µA typ Digital inputs = 0 V or VDD
65 µA max
V
DD
9/40
V min/V max
GND = 0 V, V
SS
= 0 V
1 Guaranteed by design; not subject to production test.
36 V SINGLE SUPPLY
VDD = 36 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.
Table 4.
Parameter 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range 0 V to VDD V max
On Resistance, RON 150 Ω typ VS = 0 V to 30 V, IS = −1 mA,
see Figure 25
170 215 245 Ω max VDD = 32.4 V, VSS = 0 V
On-Resistance Match
Between Channels, ∆RON
1.4 Ω typ VS = 0 V to 30 V, IS = −1 mA
8 9 10 Ω max
On-Resistance Flatness, RFLAT(O N) 35 Ω typ VS = 0 V to 30 V, IS = −1 mA
50 60 65 Ω max
LEAKAGE CURRENTS VDD = 39.6 V, VSS = 0 V
Source Off Leakage, IS (Off ) 0.01 nA typ VS = 1 V/30 V, VD = 30 V/1 V,
see Figure 27
0.1 0.2 0.4 nA max
Drain Off Leakage, I
D
(Off )
0.01
nA typ
V
S
= 1 V/30 V, V
D
= 30 V/1 V,
see Figure 27
0.1 0.4 1.2 nA max
Channel On Leakage, ID (On), IS (On) 0.02 nA typ VS = VD = 1 V/30 V, see Figure 24
0.2 0.4 1.2 nA max
DIGITAL INPUTS
Input High Voltage, VINH 2.0 V min
Input Low Voltage, VINL 0.8 V max
Input Current, I
INL
or I
INH
0.002
µA typ
V
IN
= V
GND
or V
DD
±0.1 µA max
Digital Input Capacitance, CIN 3 pF typ
DYNAMIC CHARACTERISTICS1
Transition Time, tTRANSITION 180 ns typ RL = 300 Ω, CL = 35 pF
250 275 305 ns max VS = 18 V, see Figure 30
tON 170 ns typ RL = 300 Ω, CL = 35 pF
225 265 295 ns max VS = 18 V, see Figure 32
Data Sheet ADG5236
Rev. B | Page 7 of 20
Parameter 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments
tOFF 170 ns typ RL = 300 Ω, CL = 35 pF
215 215 225 ns max VS = 18 V, see Figure 32
Break-Before-Make Time Delay, tD 75 ns typ RL = 300 Ω, CL = 35 pF
35 ns min VS1 = VS2 = 18 V, see Figure 31
Charge Injection, Q
INJ
−0.6
pC typ
V
S
= 18 V, R
S
= 0 Ω, C
L
= 1 nF,
see Figure 33
Off Isolation −85 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz,
see Figure 28
Channel-to-Channel Crosstalk −85 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz,
see Figure 26
−3 dB Bandwidth 266 MHz typ RL = 50 Ω, CL = 5 pF, see Figure 29
Insertion Loss −7 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz,
see Figure 29
CS (Off ) 2.5 pF typ VS = 18 V, f = 1 MHz
CD (Off ) 12 pF typ VS = 18 V, f = 1 MHz
C
D
(On), C
S
(On)
15
pF typ
V
S
= 18 V, f = 1 MHz
POWER REQUIREMENTS VDD = 39.6 V
IDD 85 µA typ Digital inputs = 0 V or VDD
100 130 µA max
VDD 9/40 V min/V max GND = 0 V, VSS = 0 V
1 Guaranteed by design; not subject to production test.
CONTINUOUS CURRENT PER CHANNEL, SxA, SxB, OR Dx
Table 5.
Parameter 25°C 85°C 125°C Unit
CONTINUOUS CURRENT, SxA, SxB, or Dx
VDD = +15 V, VSS = −15 V
TSSOP (θJA = 112.6°C/W) 19 7 2.8 mA max
LFCSP (θJA = 30.4°C/W) 30 7.7 2.8 mA max
VDD = +20 V, VSS = −20 V
TSSOP (θJA = 112.6°C/W) 21 7 2.8 mA max
LFCSP (θJA = 30.4°C/W) 31 7.7 2.8 mA max
VDD = 12 V, VSS = 0 V
TSSOP (θJA = 112.6°C/W) 14 6.3 2.7 mA max
LFCSP (θJA = 30.4°C/W) 22.5 7.3 2.8 mA max
VDD = 36 V, VSS = 0 V
TSSOP (θ
JA
= 112.6°C/W)
24
7.4
2.8
mA max
LFCSP (θJA = 30.4°C/W) 35 7.8 2.8 mA max
ADG5236 Data Sheet
Rev. B | Page 8 of 20
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 6.
Parameter Rating
VDD to VSS 48 V
VDD to GND −0.3 V to +48 V
VSS to GND +0.3 V to −48 V
Analog Inputs1 VSS − 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs first
Digital Inputs1 VSS − 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs first
Peak Current, SxA, SxB, or Dx
Pin
63 mA (pulsed at 1 ms,
10% duty cycle maximum)
Continuous Current, SxA, SxB,
or Dx2
Data + 15%
Temperature Range
Operating −40°C to +125°C
Storage −65°C to +150°C
Junction Temperature 150°C
Thermal Impedance, θJA
16-Lead TSSOP (4-Layer
Board)
112°C/W
16-Lead LFCSP 30.4°C/W
Reflow Soldering Peak
Temperature, Pb Free
260(+0/−5)°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Only one absolute maximum rating can be applied at any
one time.
ESD CAUTION
1 Overvoltages at the INx, SxA, SxB, and Dx pins are clamped by internal diodes.
Limit the current to the maximum ratings given.
2 See Table 5.
Data Sheet ADG5236
Rev. B | Page 9 of 20
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
IN1
1
S1A
2
D1
3
S1B
4
NC
16
NC
15
NC
14
V
DD
13
V
SS 5
S2B
12
GND
6
D2
11
NC
7
S2A
10
NC
8
IN2
9
NC = NO CONNECT
ADG5236
TOP VI EW
(No t t o Scal e)
09769-003
Figure 3. TSSOP Pin Configuration
NOTES
1. EXPOSED PAD TIED TO SUBSTRATE, V
SS
.
2. NC = NO CO NNE CT.
1
D1
2
S1B
3
V
SS
4GND
11 V
DD
12 EN
10 S2B
9D2
5
NC
6
IN2
7
NC
8
S2A
15 IN1
16 S1A
14 NC
13 NC
TOP VI EW
(No t t o Scal e)
ADG5236
09769-004
Figure 4. LFCSP Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
TSSOP LFCSP Mnemonic Description
1 15 IN1 Logic Control Input 1.
2 16 S1A Source Terminal 1A. This pin can be an input or output.
3 1 D1 Drain Terminal 1. This pin can be an input or output.
4 2 S1B Source Terminal 1B. This pin can be an input or output.
5 3 VSS Most Negative Power Supply Potential.
6 4 GND Ground (0 V) Reference.
7, 8, 14 to 16 5, 7, 13, 14 NC No Connect. These pins are open.
9 6 IN2 Logic Control Input 2.
10 8 S2A Source Terminal 2A. This pin can be an input or output.
11 9 D2 Drain Terminal 2. This pin can be an input or output.
12 10 S2B Source Terminal 2B. This pin can be an input or output.
13 11 VDD Most Positive Power Supply Potential.
N/A1 12 EN Active High Digital Input. When this pin is low, the device is disabled and all switches are
off. When this pin is high, the INx logic inputs determine the on switches.
N/A1 EP Exposed Pad Exposed Pad.
The exposed pad is connected internally. For increased reliability of the solder
joints and maximum thermal capability, it is recommended that the pad be soldered to the
substrate, VSS.
1 N/A means not applicable.
TRUTH TABLES FOR SWITCHES
Table 8. TSSOP Truth Table
INx SxA SxB
0 Off On
1 On Off
Table 9. LFCSP Truth Table
EN INx SxA SxB
0 X1 Off Off
1 0 Off On
1 1 On Off
1 X means don’t care.
ADG5236 Data Sheet
Rev. B | Page 10 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
160
0
20
40
60
80
100
120
140
–25 –20 –15 –10 –5 0510 15 20 25
ON RESISTANCE (Ω)
V
S
, V
D
(V)
T
A
= 25° C
V
DD
= +18V
V
SS
= –18V
V
DD
= +20V
V
SS
= –20V V
DD
= +22V
V
SS
= –22V
09769-105
Figure 5. On Resistance vs. VS, VD (Dual Supply)
250
200
150
100
50
0
–20 –15 –10 –5 0 5 10 15 20
ON RESISTANCE (Ω)
V
S
, V
D
(V)
T
A
= 25° C V
DD
= +9V
V
SS
= –9V
V
DD
= +13. 2V
V
SS
= –13.2V
V
DD
= +15V
V
SS
= –15V
V
DD
= +16. 5V
V
SS
= –16.5V
09769-106
Figure 6. On Resistance vs. VS, VD (Dual Supply)
500
450
400
350
300
250
200
150
100
50
00141210
8642
ON RESISTANCE (Ω)
V
S
, V
D
(V)
T
A
= 25° C V
DD
= 9V
V
SS
= 0V
V
DD
= 10.8V
V
SS
= 0V
V
DD
= 12V
V
SS
= 0V
V
DD
= 13.2V
V
SS
= 0V
09769-107
Figure 7. On Resistance vs. VS, VD (Single Supply)
160
140
120
100
80
60
40
20
00403530252015105
ON RESISTANCE (Ω)
V
S
, V
D
(V)
T
A
= 25° C
V
DD
= 32.4V
V
SS
= 0V
V
DD
= 36V
V
SS
= 0V
V
DD
= 39.6V
V
SS
= 0V
09769-108
Figure 8. On Resistance vs. VS, VD (Single Supply)
250
200
150
100
50
0
–15 –10 –5 0 5 10 15
ON RESISTANCE (Ω)
VS, VD (V)
VDD = + 15V
VSS = –15V
TA = +125°C
TA = +85°C
TA = +25°C
TA = –40° C
09769-109
Figure 9. On Resistance vs. VD or VS for Different Temperatures,
±15 V Dual Supply
200
160
120
80
40
180
140
100
60
20
0
–20 –15 –10 –5 0510 2015
ON RESISTANCE (Ω)
VS, VD (V)
VDD = + 20V
VSS = –20V
TA = +125°C
TA = +85°C
TA = +25°C
TA = –40° C
09769-110
Figure 10. On Resistance vs. VD or VS for Different Temperatures,
±20 V Dual Supply
Data Sheet ADG5236
Rev. B | Page 11 of 20
500
400
300
200
100
450
340
250
150
50
00 2 4 6 8 10 12
ON RESISTANCE (Ω)
VS, VD (V)
VDD = 12V
VSS = 0V
TA = +125°C
TA = +85°C
TA = +25°C
TA = –40° C
09769-111
Figure 11. On Resistance vs. VD or VS for Different Temperatures,
12 V Single Supply
250
200
100
150
50
00353025
201510
5
ON RESISTANCE (Ω)
V
S
,V
D
(V)
V
DD
= 36V
V
SS
= 0V
T
A
= +125°C
T
A
= +85°C
T
A
= +25°C
T
A
= –40° C
09769-112
Figure 12. On Resistance vs. VS or VD for Different Temperatures,
36 V Single Supply
10
–70
–60
–50
–40
–30
–20
–10
0
020 40 60 80 100 120
LE AKAGE CURRENT (p A)
TEMPERATURE (°C)
V
DD
= +15V
V
SS
= –15V
V
BIAS
= +10V/–10V
I
D
(OFF) – +
I
S
(OFF) – +
I
S
(OFF) + –
I
D
(OFF) + –
I
D,
I
S
(ON) + +
I
D,
I
S
(O N) – –
09769-113
Figure 13. Leakage Current vs. Temperature, ±15 V Dual Supply
020 40 60 80 100 120
TEMPERATURE (°C)
100
–200
–150
–100
–50
0
50
LE AKAGE CURRENT (p A)
VDD = + 20V
VSS = –20V
VBIAS = + 15V /–15V
ID (OFF) – +
IS (OFF) – +
IS (OFF) + –
ID (OFF) + –
ID, IS (ON) + +
ID, IS (ON) – –
09769-114
Figure 14. Leakage Current vs. Temperature, ±20 V Single Supply
020 40 60 80 100 120
TEMPERATURE (°C)
40
20
–120
–100
–80
–60
–40
–20
0
LE AKAGE CURRENT (p A)
VDD = 12V
VSS = 0V
VBIAS = 1V /10V
ID (OFF) – +
IS (OFF) – +
IS (OFF) + –
ID (OFF) + –
ID, IS (ON) + +
ID, IS (ON) – –
09769-115
Figure 15. Leakage Current vs. Temperature, 12 V Single Supply
020 40 60 80 100 120
TEMPERATURE (°C)
50
–250
–200
–150
–100
–50
0
LE AKAGE CURRENT (p A)
VDD = 36V
VSS = 0V
VBIAS = 1V /30V
ID (OFF) – +
IS (OFF) – +
IS (OFF) + –
ID (OFF) + –
ID, IS (ON) + +
ID, IS (ON) – –
09769-116
Figure 16. Leakage Current vs. Temperature, 36 V Single Supply
ADG5236 Data Sheet
Rev. B | Page 12 of 20
10k 100k 1M 10M 100M 1G
FRE QUENCY ( Hz )
0
–120
–100
–80
–60
–40
–20
I
L
(d B)
T
A
= 25° C
V
DD
= +15V
V
SS
= –15V
09769-117
Figure 17. Off Isolation vs. Frequency
10k 100k 1M 10M 100M 1G
FRE QUENCY ( Hz )
0
–140
–120
–100
–80
–60
–40
–20
CROS S TALK ( dB)
T
A
= 25° C
V
DD
= +15V
V
SS
= –15V
BET WEEN S A AND S B
BET WEEN S 1 AND S 2
09769-118
Figure 18. Crosstalk vs. Frequency
–20 –10 010 20 30 40
V
S
(V)
1.5
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
CHARGE INJECT ION ( pC)
T
A
= 25° C V
DD
= +20V
V
SS
= –20V
V
DD
= +15V
V
SS
= –15V
V
DD
= +36V
V
SS
= 0V
V
DD
= +12V
V
SS
= 0V
09769-119
Figure 19. Charge Injection vs. Source Voltage
1k 10k 100k 1M 10M
FRE QUENCY ( Hz )
0
–120
–100
–80
–60
–40
–20
ACPSRR ( dB)
TA = 25° C
VDD = + 15V
VSS = –15V
NO DE COUPL ING CAP ACITORS
DECO UP LING CAPACI TORS
09769-120
Figure 20. ACPSRR vs. Frequency
100k 1M 10M 100M 1G
FRE QUENCY ( Hz )
0
–20
–18
–16
–14
–12
–10
–8
–6
–4
–2
ATTENUAT ION ( dB)
T
A
= 25° C
V
DD
= +15V
V
SS
= –15V
09769-122
Figure 21. Bandwidth
350
300
250
200
150
100
50
0
–40 –20 020 40 60 80 100 120
TIME (n s)
TEMPERATURE (°C)
VDD = + 12V
VSS = 0V
VDD = + 36V
VSS = 0V
VDD = + 15V
VSS = –15V
VDD = + 20V
VSS = –20V
09769-123
Figure 22. tTRANSITION Time vs. Temperature
Data Sheet ADG5236
Rev. B | Page 13 of 20
–15 –10 –5 0 5 10 15
V
S
(V)
0
5
10
15
20
CAPACI T ANCE ( p F)
09769-124
SO URCE / DRAIN ON
DRAIN OFF
SO URCE OFF
T
A
= 25°C
V
DD
= +15V
V
SS
= –15V
Figure 23. Capacitance vs. Source Voltage, Dual Supply
ADG5236 Data Sheet
Rev. B | Page 14 of 20
TEST CIRCUITS
SxA/SxB Dx A
V
D
I
D
(ON)
NC
NC = NO CONNECT
09769-025
Figure 24. On Leakage
I
DS
SxA/SxB Dx
V
S
V
09769-023
Figure 25. On Resistance
CHANNEL-TO-CHANNEL CROSSTALK = 20 log V
OUT
GND
SxA
Dx
SxB
V
OUT
NETWORK
ANALYZER
R
L
50Ω
R
L
50Ω
V
S
V
S
V
DD
V
SS
0.1µF
V
DD
0.1µF
V
SS
INx
09769-032
Figure 26. Channel-to-Channel Crosstalk
SxA/SxB Dx
V
S
A A
V
D
I
S
(OFF) I
D
(OFF)
09769-024
Figure 27. Off Leakage
V
OUT
50Ω
NETWORK
ANALYZER
R
L
50Ω
INx
V
IN
SxA
Dx
V
S
V
DD
V
SS
0.1µF
V
DD
0.1µF
V
SS
GND
50Ω
NC
SxB
OFF ISOLATION = 20 log
V
OUT
V
S
09769-030
Figure 28. Off Isolation
V
OUT
50Ω
NETWORK
ANALYZER
R
L
50Ω
INx
V
IN
SxA
Dx
V
S
V
DD
V
SS
0.1µF
V
DD
0.1µF
V
SS
GND
50Ω
NC
SxB
INSERTION LOSS = 20 log
V
OUT
WITH SWITCH
V
OUT
WITHOUT SWITCH
09769-031
Figure 29. Bandwidth
Data Sheet ADG5236
Rev. B | Page 15 of 20
INx
V
OUT
Dx
SxA
V
DD
V
SS
V
DD
V
SS
GND
C
L
35pF
SxB
V
IN
V
S
0.1µF0.1µF
R
L
300
50%
50%
90%
50%
50%
90%
tON
TRANSITION
tOFF
TRANSITION
V
IN
V
OUT
V
IN
09769-026
Figure 30. Switching Times
INx
V
OUT
Dx
SxA
V
DD
V
SS
V
DD
V
SS
GND
C
L
35pF
SxB
V
IN
V
S
0.1µF0.1µF
R
L
300
80%
t
D
t
D
V
OUT
V
IN
09769-027
Figure 31. Break-Before-Make Time Delay tD
OUTPUT
INx
50300
GND
SxA
SxB
Dx
35pF
V
IN
EN
V
DD
V
SS
V
DD
V
SS
V
S
3V
0V
OUTPUT
50% 50%
t
OFF
(EN)
t
ON
(EN)
0.9V
OUT
0.1V
OUT
ENABLE
DRIVE (V
IN
)
09769-028
Figure 32. Enable Delay, tON (EN), tOFF (EN)
V
IN
(NORMALLY
CLOSED SWITCH)
V
OUT
V
IN
(NORMALLY
OPEN SWITCH)
OFF
V
OUT
ON
Q
INJ
= C
L
× V
OUT
INx
V
OUT
Dx
SxA
V
DD
V
SS
V
DD
V
SS
GND
C
L
1nF
NC
SxB
V
IN
V
S
0.1µF0.1µF
09769-029
Figure 33. Charge Injection
ADG5236 Data Sheet
Rev. B | Page 16 of 20
TERMINOLOGY
IDD
IDD represents the positive supply current.
ISS
ISS represents the negative supply current.
VD, VS
VD and VS represent the analog voltage on Terminal D and
Terminal S, respectively.
RON
RON represents the ohmic resistance between Terminal D and
Terminal S.
∆RON
∆RON represents the difference between the RON of any two
channels.
RFLAT (ON)
Flatness that is defined as the difference between the maximum
and minimum value of on resistance measured over the specified
analog signal range is represented by RFLAT (ON).
IS (Off)
IS (Off) is the source leakage current with the switch off.
ID (Off)
ID (Off) is the drain leakage current with the switch off.
ID (On), IS (On)
ID (On) and IS (On) represent the channel leakage currents with
the switch on.
VINL
VINL is the maximum input voltage for Logic 0.
VINH
VINH is the minimum input voltage for Logic 1.
IINL, IINH
IINL and IINH represent the low and high input currents of the
digital inputs.
CD (Off)
CD (Off) represents the off switch drain capacitance, which is
measured with reference to ground.
CS (Off)
CS (Off) represents the off switch source capacitance, which is
measured with reference to ground.
CD (On), CS (On)
CD (On) and CS (On) represent on switch capacitances, which
are measured with reference to ground.
CIN
CIN is the digital input capacitance.
tON
tON represents the delay between applying the digital control
input and the output switching on.
tOFF
tOFF represents the delay between applying the digital control
input and the output switching off.
tD
tD represents the off time measured between the 80% point
of both switches when switching from one address state to
another.
Off Isolation
Off isolation is a measure of unwanted signal coupling through
an off switch.
Charge Injection
Charge injection is a measure of the glitch impulse transferred
from the digital input to the analog output during switching.
Crosstalk
Crosstalk is a measure of unwanted signal that is coupled
through from one channel to another as a result of parasitic
capacitance.
Bandwidth
Bandwidth is the frequency at which the output is attenuated
by 3 dB.
On Response
On response is the frequency response of the on switch.
Insertion Loss
Insertion loss is the loss due to the on resistance of the switch.
AC Power Supply Rejection Ratio (ACPSRR)
ACPSRR is the ratio of the amplitude of signal on the output to the
amplitude of the modulation. This is a measure of the ability of
the device to avoid coupling noise and spurious signals that appear
on the supply voltage pin to the output of the switch. The dc voltage
on the device is modulated by a sine wave of 0.62 V p-p.
Data Sheet ADG5236
Rev. B | Page 17 of 20
TRENCH ISOLATION
In the ADG5236, an insulating oxide layer (trench) is placed
between the NMOS and the PMOS transistors of each CMOS
switch. Parasitic junctions, which occur between the transistors
in junction isolated switches, are eliminated, and the result is a
completely latch-up proof switch.
In junction isolation, the N and P wells of the PMOS and
NMOS transistors form a diode that is reverse-biased under
normal operation. However, during overvoltage conditions, this
diode can become forward-biased. A silicon controlled rectifier
(SCR) type circuit is formed by the two transistors causing a
significant amplification of the current that, in turn, leads to
latch-up. With trench isolation, this diode is removed, and the
result is a latch-up proof switch.
NMOS PMOS
P WELL N W E LL
BURIE D OXI DE LAYER
HANDLE WAFE R
TRENCH
09769-045
Figure 34. Trench Isolation
ADG5236 Data Sheet
Rev. B | Page 18 of 20
APPLICATIONS INFORMATION
The ADG52xx family of switches and multiplexers provide a
robust solution for instrumentation, industrial, automotive,
aerospace, and other harsh environments that are prone to
latch-up, which is an undesirable high current state that can
lead to device failure and persists until the power supply is
turned off. The ADG5236 high voltage switches allow single-
supply operation from 9 V to 40 V and dual supply operation
from ±9 V to ±22 V.
Data Sheet ADG5236
Rev. B | Page 19 of 20
OUTLINE DIMENSIONS
16 9
81
PIN 1
SEATING
PLANE
8°
0°
4.50
4.40
4.30
6.40
BSC
5.10
5.00
4.90
0.65
BSC
0.15
0.05
1.20
MAX 0.20
0.09 0.75
0.60
0.45
0.30
0.19
COPLANARITY
0.10
COM PLI ANT TO JE DE C S TANDARDS MO-153-AB
Figure 35. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
2.70
2.60 SQ
2.50
COMPLIANT
TO
JEDEC STANDARDS MO-220-WGGC.
1
0.65
BSC
BOTTOM VIEWTOP VIEW
16
5
8
9
12 13
4
EXPOSED
PAD
PIN1
INDICATOR
4.10
4.00 SQ
3.90
0.45
0.40
0.35
S
EATING
PLANE
0.80
0.75
0.70 0.05 MAX
0.02 NOM
0.20 REF
0.20 MIN
COPLANARITY
0.08
PIN 1
INDICATOR
0.35
0.30
0.25
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
08-16-2010-C
Figure 36. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
4 mm × 4 mm Body, Very Very Thin Quad
(CP-16-17)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
ADG5236BRUZ −40°C to +125°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADG5236BRUZ-RL7 −40°C to +125°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADG5236BCPZ-RL7 −40°C to +125°C 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-16-17
1 Z = RoHS Compliant Part.
ADG5236 Data Sheet
Rev. B | Page 20 of 20
NOTES
©2011–2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09769-0-11/13(B)