© Semiconductor Components Industries, LLC, 2016
February, 2016 − Rev. 7 1Publication Order Number:
MC74LVXT4052/D
MC74LVXT4052
Analog Multiplexer/
Demultiplexer
High−Performance Silicon−Gate CMOS
The MC74LVXT4052 utilizes silicon−gate CMOS technology to
achieve fast propagation delays, low ON resistances, and low OFF
leakage currents. This analog multiplexer/demultiplexer controls
analog voltages that may vary across the complete power supply range
(from VCC to VEE).
The LVXT4052 is similar in pinout to the high−speed HC4052A
and the metal−gate MC14052B. The Channel−Select inputs determine
which one of the Analog Inputs/Outputs is to be connected, by means
of an analog switch, to the Common Output/Input. When the Enable
pin is HIGH, all analog switches are turned off.
The Channel−Select and Enable inputs are compatible with standard
TTL levels.
This device has been designed so the ON resistance (RON) is more
linear over input voltage than the RON of metal−gate CMOS analog
switches and High−Speed CMOS analog switches.
Features
•Select Pins Compatible with TTL Levels
•Fast Switching and Propagation Speeds
•Low Crosstalk Between Switches
•Analog Power Supply Range (VCC − VEE) = −3.0 V to )3.0 V
•Digital (Control) Power Supply Range (VCC − GND) = 2.5 to 6.0 V
•Improved Linearity and Lower ON Resistance Than Metal−Gate,
HSL, or VHC Counterparts
•Low Noise
•Designed to Operate on a Single Supply with VEE = GND,
or Using Split Supplies up to ±3.0 V
•Break−Before−Make Circuitry
•These Devices are Pb−Free and are RoHS Compliant
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See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
ORDERING INFORMATION
MARKING DIAGRAMS
TSSOP−16
DT SUFFIX
CASE 948F
SOIC−16
D SUFFIX
CASE 751B
LVXT4052G
AWLYWW
1
16
1
16
LVXT4052 = Specific Device Code
A = Assembly Location
WL, L = Wafer Lot
Y = Year
WW, W = Work Week
G or G= Pb−Free Package
(Note: Microdot may be in either location)
LVXT
4052
ALYWG
G
TSSOP−16
SOIC−16
1516 14 13 12 11 10
21 34567
VCC
9
8
X2 X1 X X0 X3 A B
Y0 Y2 Y Y3 Y1 Enable VEE GND
PIN ASSIGNMENT
MC74LVXT4052
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2
Figure 1. Logic Diagram
Double−Pole, 4−Position Plus Common Off
FUNCTION TABLE
L
L
H
H
X
L
H
L
H
X
Control Inputs
ON Channels
Enable Select
BA
X0
X1
X2
X3
L
L
L
L
H
X = Don’t Care
Y0
Y1
Y2
Y3 NONE
X0 12
X1 14
X2 15
X3 11
Y0 1
Y1 5
Y2 2
Y3 4
A10
B9
ENABLE 6
X SWITCH
Y SWITCH
X
13
ANALOG
INPUTS/OUTPUTS
CHANNEL‐SELECT
INPUTS PIN 16 = VCC
PIN 7 = VEE
PIN 8 = GND
COMMON
OUTPUTS/INPUTS
Y
3
NOTE: This device allows independent control of each switch.
Channel−Select Input A controls the X−Switch, Input B controls the Y−Switch.
ORDERING INFORMATION
Device Package Shipping†
MC74LVXT4052DG SOIC−16
(Pb−Free) 48 Units / Rail
MC74LVXT4052DR2G SOIC−16
(Pb−Free) 2500 Tape & Reel
MC74LVXT4052DTG TSSOP−16
(Pb−Free) 96 Units / Rail
MC74LVXT4052DTRG TSSOP−16
(Pb−Free) 2500 Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
MC74LVXT4052
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3
MAXIMUM RATINGS
Symbol Parameter Value Unit
VEE Negative DC Supply Voltage (Referenced to GND) −7.0 to +0.5 V
VCC Positive DC Supply Voltage (Referenced to GND)
(Referenced to VEE)−0.5 to +7.0
−0.5 to +7.0 V
VIS Analog Input Voltage VEE − 0.5 to VCC + 0.5 V
VIN Digital Input Voltage (Referenced to GND) −0.5 to 7.0 V
IDC Current, Into or Out of Any Pin ±20 mA
TSTG Storage Temperature Range −65 to +150 _C
TLLead Temperature, 1 mm from Case for 10 Seconds 260 _C
TJJunction Temperature under Bias +150 _C
JA Thermal Resistance SOIC
TSSOP 143
164 °C/W
PDPower Dissipation in Still Air, SOIC
TSSOP 500
450 mW
MSL Moisture Sensitivity Level 1
FRFlammability Rating Oxygen Index: 30% − 35% UL 94−V0 @ 0.125 in
VESD ESD Withstand Voltage Human Body Model (Note 1)
Machine Model (Note 2)
Charged Device Model (Note 3)
u2000
u200
u1000
V
ILATCHUP Latchup Performance Above VCC and Below GND at 125°C (Note 4) ±300 mA
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be af fected.
1. Tested to EIA/JESD22−A114−A.
2. Tested to EIA/JESD22−A115−A.
3. Tested to JESD22−C101−A.
4. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
ÎÎÎÎÎ
ÎÎÎÎÎ
VEE
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Negative DC Supply Voltage (Referenced to GND)
ÎÎÎÎ
ÎÎÎÎ
−6.0
ÎÎÎÎ
ÎÎÎÎ
GND
ÎÎÎ
ÎÎÎ
V
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
VCC
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Positive DC Supply Voltage (Referenced to GND)
(Referenced to VEE)
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
2.5
2.5
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
6.0
6.0
ÎÎÎ
ÎÎÎ
ÎÎÎ
V
ÎÎÎÎÎ
VIS
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Analog Input Voltage
ÎÎÎÎ
VEE
ÎÎÎÎ
VCC
ÎÎÎ
V
ÎÎÎÎÎ
ÎÎÎÎÎ
VIN
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Digital Input Voltage (Note 5) (Referenced to GND)
ÎÎÎÎ
ÎÎÎÎ
0
ÎÎÎÎ
ÎÎÎÎ
6.0
ÎÎÎ
ÎÎÎ
V
ÎÎÎÎÎ
ÎÎÎÎÎ
TA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Operating Temperature Range, All Package Types
ÎÎÎÎ
ÎÎÎÎ
−55
ÎÎÎÎ
ÎÎÎÎ
125
ÎÎÎ
ÎÎÎ
_C
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
tr, tf
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Input Rise/Fall Time VCC = 3.0 V ± 0.3 V
(Channel Select or Enable Inputs) VCC = 5.0 V ± 0.5 V
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
0
0
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
100
20
ÎÎÎ
ÎÎÎ
ÎÎÎ
ns/V
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
5. Unused inputs may not be left open. All inputs must be tied to a high−logic voltage level or a low−logic input voltage level.
DEVICE JUNCTION TEMPERATURE VERSUS
TIME TO 0.1% BOND FAILURES
Junction
Temperature °CTime, Hours Time, Years
80 1,032,200 117.8
90 419,300 47.9
100 178,700 20.4
110 79,600 9.4
120 37,000 4.2
130 17,800 2.0
140 8,900 1.0
1
1 10 100 1000
FAILURE RATE OF PLASTIC = CERAMIC
UNTIL INTERMETALLICS OCCUR
Figure 2. Failure Rate vs. Time Junction Temperature
NORMALIZED FAILURE RATE
TIME, YEARS
TJ = 130_C
TJ = 120_C
TJ = 110_C
TJ = 100_C
TJ = 90_C
TJ = 80_C
MC74LVXT4052
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DC CHARACTERISTICS − Digital Section (Voltages Referenced to GND)
Symbo
l
Parameter Condition VCC
V
Guaranteed Limit
Unit
−55 to 25°Cv85°Cv125°C
VIH Minimum High−Level Input Volt-
age,
Channel−Select or Enable Inputs
3.0
4.5
5.5
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
V
VIL Maximum Low−Level Input Volt-
age,
Channel−Select or Enable Inputs
3.0
4.5
5.5
0.5
0.8
0.8
0.5
0.8
0.8
0.5
0.8
0.8
V
IIN Maximum Input Leakage Current,
Channel−Select or Enable Inputs VIN = 6.0 or GND 0 V to 6.0 V ±0.1 ±1.0 ±1.0 A
ICC Maximum Quiescent Supply
Current (per Package) Channel Select, Enable and
VIS = VCC or GND 6.0 4.0 40 80 A
DC ELECTRICAL CHARACTERISTICS − Analog Section
Symbo
l
Parameter Test Conditions VCC
VVEE
V
Guaranteed Limit
Unit
−55 to 25°Cv85_Cv125_C
RON Maximum “ON” Resistance VIN = VIL or VIH
VIS = ½ (VCC − VEE)
|IS| = 2.0 mA (Figure 3)
3.0
4.5
3.0
0
0
−3.0
86
37
26
108
46
33
120
55
37
RON Maximum Difference in “ON” Re-
sistance Between Any Two
Channels in the Same Package
VIN = VIL or VIH
VIS = ½ (VCC − VEE)
|IS| = 2.0 mA
3.0
4.5
3.0
0
0
−3.0
15
13
10
20
18
15
20
18
15
Ioff Maximum Off−Channel Leakage
Current, Any One Channel Vin = VIL or VIH;
VIO = VCC or GND;
Switch Off (Figure 3)
5.5
+3.0 0
−3.0 0.1
0.1 0.5
0.5 1.0
1.0 A
Maximum Off−Channel
Leakage Current,
Common Channel
Vin = VIL or VIH;
VIO = VCC or GND;
Switch Off (Figure 4)
5.5
+3.0 0
−3.0 0.2
0.2 2.0
2.0 4.0
4.0
Ion Maximum On−Channel
Leakage Current,
Channel−to−Channel
Vin = VIL or VIH;
Switch−to−Switch =
VCC or GND; (Figure 5)
5.5
+3.0 0
−3.0 0.2
0.2 2.0
2.0 4.0
4.0 A
AC CHARACTERISTICS (Input tr = tf = 3 ns)
Symbo
l
Parameter Test Conditions VCC
VVEE
V
Guaranteed Limit
Unit
−55 to 25_C
v85_Cv125_C
Min Typ*
tBBM Minimum Break−Before−Make
Time VIN = VIL or VIH
VIS = VCC
RL = 300 CL = 35 pF
(Figures 11 and 12)
3.0
4.5
3.0
0.0
0.0
−3.0
1.0
1.0
1.0
6.5
5.0
3.5
−
−
−
−
−
−
ns
*Typical Characteristics are at 25_C.
MC74LVXT4052
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AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 3 ns)
Symbo
l
Parameter VCC
VVEE
V
Guaranteed Limit
Unit
−55 to 25°Cv85°Cv125°C
Min Typ Max Min Max Min Max
tPLH,
tPHL Maximum Propagation Delay, Channel−Select
to Analog Output
(Figures 15 and 16)
2.5
3.0
4.5
3.0
0
0
0
−3.0
40
28
23
23
45
30
25
25
50
35
30
28
ns
tPLZ,
tPHZ Maximum Propagation Delay, Enable to Analog
Output (Figures 13 and 14) 2.5
3.0
4.5
3.0
0
0
0
−3.0
40
28
23
23
45
30
25
25
50
35
30
28
ns
tPZL,
tPZH Maximum Propagation Delay, Enable to Analog
Output (Figures 13 and 14) 2.5
3.0
4.5
3.0
0
0
0
−3.0
40
28
23
23
45
30
25
25
50
35
30
28
ns
CPD Power Dissipation Capacitance (Figure 17) (Note 6)
Typical @ 25°C, VCC = 5.0 V, VEE = 0 V
45 pF
CIN Maximum Input Capacitance, Channel−Select or Enable Inputs 10 pF
CI/O Maximum Capacitance Analog I/O
(All Switches Off) Common O/I
Feedthrough
10
10
1.0 pF
6. Used to determine the no−load dynamic power consumption: PD = C PD VCC2f + ICC VCC.
ADDITIONAL APPLICATION CHARACTERISTICS (GND = 0 V)
Symbo
l
Parameter Condition VCC
VVEE
V
Typ
Unit
25°C
BW Maximum On−Channel Bandwidth or Minimum
Frequency Response VIS = ½ (VCC − VEE)
Ref and Test Attn = 10 dB
Source Amplitude = 0 dB
(Figure 6)
3.0
4.5
6.0
3.0
0.0
0.0
0.0
−3.0
80
80
80
80
MHz
VISO Off−Channel Feedthrough Isolation f = 1 MHz; VIS = ½ (VCC − VEE)
Adjust Network Analyzer output to 10 dBm
on each output from the power splitter.
(Figures 7 and 8)
3.0
4.5
6.0
3.0
0.0
0.0
0.0
−3.0
−70
−70
−70
−70
dB
VONL Maximum Feedthrough On Loss VIS = ½ (VCC − VEE)
Adjust Network Analyzer output to 10 dBm
on each output from the power splitter.
(Figure 10)
3.0
4.5
6.0
3.0
0.0
0.0
0.0
−3.0
−2
−2
−2
−2
dB
QCharge Injection VIN = VCC to VEE, fIS = 1 kHz, tr = tf = 3 ns
RIS = 0 , CL= 1000 pF, Q = CL * VOUT
(Figure 9)
5.0
3.0 0.0
−3.0 9.0
12 pC
THD Total Harmonic Distortion THD + Noise fIS = 1 MHz, RL = 10 K, CL = 50 pF,
VIS = 5.0 VPP sine wave
VIS = 6.0 VPP sine wave
(Figure 18)
6.0
3.0 0.0
−3.0 0.10
0.05
%
MC74LVXT4052
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Figure 3. On Resistance, Test Set−Up
PLOTTER
MINI
COMPUTER
PROGRAMMABLE
POWER
SUPPLY DC ANALYZER
VCC
DEVICE
UNDER TEST
GND
ANALOG IN COMMON OUT
GND
*)
Figure 4. Maximum Off Channel Leakage Current,
Any One Channel, Test Set−Up Figure 5. Maximum On Channel Leakage Current,
Channel to Channel, Test Set−Up
Figure 6. Maximum On Channel Bandwidth, Test Set−Up
OFF
OFF
6
7
8
16
COMMON O/I
VCC
VIH
NC
A
VCC
VEE
VCC
ON
OFF
6
7
8
16
COMMON O/I
VCC
VIL
VCC
VEE
VCC
N/C
A
ANALOG I/O
VEE
VEE
ON
OFF
6
7
8
VCC
VEE
9−11
All untested Analog I/O pins
HP11667B
Pwr Splitter
HP4195A
Network Anl
0.1 F
S1 R1 T1 0.1 F
50 K
100 K
VIS
A
Channel Selects
connected to address
pins on HP4195A and
appropriately configured
to test each switch.
MC74LVXT4052
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Figure 7. Maximum Off Channel Feedthrough Isolation, Test Set−Up
Figure 8. Maximum Common−Channel Feedthrough Isolation, Test Set−Up
OFF
ON
6
7
8
VCC
VEE
9−11
All untested Analog I/O pins
HP11667B
Pwr Splitter
HP4195A
Network Anl
0.1 F
S1 R1 T1 0.1 F
50 K
100 K
VIS
16
Config = Network
Format = T/R (dB)
CAL = Trans Cal
Display = Rectan X*A)B
Scale Ref = Auto Scale
View = Off, Off, Off
Trig = Cont Mode
Source Amplitude = )13 dB
Reference Attenuation = 20 dB
Test Attenuation = 0 dB
VISO(dB) = 20 log (VT1/VR1)
6
7
8
VCC
VEE
9−11
All untested Analog I/O pins
HP11667B
Pwr Splitter
HP4195A
Network Anl
0.1 F
S1 R1 T1 0.1 F
50
100 K
VIS
16
Config = Network
Format = T/R (dB)
CAL = Trans Cal
Display = Rectan X*A)B
Scale Ref = Auto Scale
View = Off, Off, Off
Trig = Cont Mode
Source Amplitude = )13 dB
Reference Attenuation = 20 dB
Test Attenuation = 0 dB
VISOC(dB) = 20 log (VT1/VR1)
ON
50 K
OFF
Channel Selects
connected to address
pins on HP4195A and
appropriately configured
to test each switch.
Channel Selects
connected to address
pins on HP4195A and
appropriately configured
to test each switch.
MC74LVXT4052
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Figure 9. Charge Injection, Test Set−Up
ON/OFF
7
8
V
CC
VOUT
OFF/ON
9−11
CL*
VIH
VIL
*Includes all probe and jig capacitance.
16
Bias Channel Selects to
test each combination of
analog inputs to common
analog output.
6
Enable
VEE
VIN RIS
VIS
VOUT VOUT
Q = CL * VOUT
Figure 10. Maximum On Channel Feedthrough On Loss, Test Set−Up
OFF
ON
6
7
8
VCC
VEE
9−11
All untested Analog I/O pins
HP11667B
Pwr Splitter
HP4195A
Network Anl
0.1 F
S1 R1 T1 0.1 F
50
100 K
VIS
16
Config = Network
Format = T/R (dB)
CAL = Trans Cal
Display = Rectan X*A)B
Scale Ref = Auto Scale
View = Off, Off, Off
Trig = Cont Mode
Source Amplitude = )13 dB
Reference Attenuation = 20 dB
Test Attenuation = 20 dB
VONL(dB) = 20 log (VT1/VR1)
Channel Selects
connected to address
pins on HP4195A and
appropriately configured
to test each switch.
MC74LVXT4052
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Figure 11. Break−Before−Make, Test Set−Up Figure 12. Break−Before−Make Time
ON
OFF
6
7
8
VCC
VEE
9−11
Tek 11801B
DSO
COM INPUT
16
RLCL
VIN
50
VIN
80%
VCC
tBBM
80% of
VOH
Figure 13. Propagation Delays, Channel Select
to Analog Out Figure 14. Propagation Delay, Test Set−Up
Channel Select to Analog Out
VCC
GND
CHANNEL
SELECT
ANALOG
OUT 50%
tPLH tPHL
50%
ON/OFF
6
7
8
16
VCC
CL*
CHANNEL SELECT
TEST
POINT
COMMON
OFF/ON
ANALOG I/O
VCC
ON/OFF
6
7
8
ENABLE
VCC
ENABLE 90%
50%
10%
tftrVCC
GND
ANALOG
OUT
tPZL
ANALOG
OUT
tPZH
HIGH
IMPEDANCE
VOL
VOH
HIGH
IMPEDANCE
10%
90%
tPLZ
tPHZ
50%
50% ANALOG I/O
CL*
TEST
POINT
16
VCC 1 K
1
2
1
2
POSITION 1 WHEN TESTING tPHZ AND tPZH
POSITION 2 WHEN TESTING tPLZ AND tPZL
GND
GND
O/I
Channel Selects connected
to VIN and appropriately
configured to test each switch.
VOH
*Includes all probe and jig capacitance.
Figure 15. Propagation Delays, Enable to
Analog Out Figure 16. Propagation Delay, Test Set−Up
Enable to Analog Out
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Figure 17. Power Dissipation Capacitance, Test Set−Up
ON/OFF
12
V
CC
NC
OFF/ON
10 − 11,
13 − 14 Channel
Select
15
VIL
VCC A
Figure 18. Total Harmonic Distortion, Test Set−Up
6
7
89−11
HP3466
DMM
16
50 K
)V
COM
HP3466
DMM
)V
COM
HP E3630A
DC Pwr Supply
COM )20 V *20 V
HP 339
Distortion Measurement Set
Analyzer
Input COM Oscillator
Output COM
RLCL
ON
OFF
Channel Selects connected
to DC bias supply or ground
and appropriately configured
to test each switch.
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APPLICATIONS INFORMATION
The Channel Select and Enable control pins should be at
VCC or GND logic levels. VCC being recognized as a logic
high and GND being recognized as a logic low. In this
example: VCC = )5 V = logic high
GND = 0 V = logic low
The maximum analog voltage swing is determined by the
supply voltages VCC and VEE. The positive peak analog
voltage should not exceed VCC. Similarly, the negative peak
analog voltage should not go below VEE. In this example,
the di fference between VCC and VEE is five volts. Therefore,
using the configuration of Figure 20, a maximum analog
signal of five volts peak−to−peak can be controlled. Unused
analog inputs/outputs may be left floating (i.e., not
connected). However, tying unused analog inputs and
outputs to VCC or GND through a low value resistor helps
minimize crosstalk and feedthrough noise that may be
picked up by an unused switch.
Although used here, balanced supplies are not a
requirement. The only constraints on the power supplies are
that: VEE − GND = 0 to *6 volts
VCC − GND = 2.5 to 6 volts
VCC − VEE = 2.5 to 6 volts
and VEE v GND
When voltage transients above VCC and/or below VEE are
anticipated on the analog channels, external Germanium or
Schottky diodes (Dx) are recommended as shown in
Figure 21. These diodes should be able to absorb the
maximum anticipated current surges during clipping.
ANALOG
SIGNAL
Figure 19. Application Example
ON
6
7
8
16
+3.0 V
ANALOG
SIGNAL
+3.0 V
−3.0 V
+3.0 V
−3.0 V
11
10
9
TO EXTERNAL CMOS
CIRCUITRY 0 to 3.0 V
DIGITAL SIGNALS
−3.0 V
Figure 20. Application Example
ANALOG
SIGNAL
ON
6
7
8
16
+5 V
ANALOG
SIGNAL
+5 V
GND
+5 V
GND
11
10
9
TO EXTERNAL CMOS
CIRCUITRY 0 to 5 V
DIGITAL SIGNALS
ON/OFF
7
8
16
VCC
VEE
Dx
VCC
Dx
VEE
Dx
VCC
Dx
VEE
Figure 21. External Germanium or Schottky Clipping Diodes
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PACKAGE DIMENSIONS
TSSOP−16
CASE 948F
ISSUE B
ÇÇÇ
ÇÇÇ
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A4.90 5.10 0.193 0.200
B4.30 4.50 0.169 0.177
C−−− 1.20 −−− 0.047
D0.05 0.15 0.002 0.006
F0.50 0.75 0.020 0.030
G0.65 BSC 0.026 BSC
H0.18 0.28 0.007 0.011
J0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L6.40 BSC 0.252 BSC
M0 8 0 8
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
____
SECTION N−N
SEATING
PLANE
IDENT.
PIN 1
18
16 9
DETAIL E
J
J1
B
C
D
A
K
K1
H
G
ÉÉÉ
ÉÉÉ
DETAIL E
F
M
L
2X L/2
−U−
S
U0.15 (0.006) T
S
U0.15 (0.006) T
S
U
M
0.10 (0.004) V S
T
0.10 (0.004)
−T−
−V−
−W−
0.25 (0.010)
16X REFK
N
N
7.06
16X
0.36 16X
1.26
0.65
DIMENSIONS: MILLIMETERS
1
PITCH
SOLDERING FOOTPRINT*
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
MC74LVXT4052
www.onsemi.com
14
PACKAGE DIMENSIONS
SOIC−16
CASE 751B−05
ISSUE K NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
18
16 9
SEATING
PLANE
F
J
M
RX 45_
G
8 PLP
−B−
−A−
M
0.25 (0.010) B S
−T−
D
K
C
16 PL
S
B
M
0.25 (0.010) A S
T
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A9.80 10.00 0.386 0.393
B3.80 4.00 0.150 0.157
C1.35 1.75 0.054 0.068
D0.35 0.49 0.014 0.019
F0.40 1.25 0.016 0.049
G1.27 BSC 0.050 BSC
J0.19 0.25 0.008 0.009
K0.10 0.25 0.004 0.009
M0 7 0 7
P5.80 6.20 0.229 0.244
R0.25 0.50 0.010 0.019
____
6.40
16X
0.58
16X 1.12
1.27
DIMENSIONS: MILLIMETERS
1
PITCH
SOLDERING FOOTPRINT*
16
89
8X
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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