MAIN FEATURES ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! 8-bit resolution. 500 Msps (min) sampling rate. 1.3 GHz full power input bandwidth. Band Flatness: TBD Input VSWR (packaged device): TBD SINAD = 45 dB (7.2 Effective Bits), SFDR = 54 dBc @ FS = 500 Msps, FIN = 20 MHz : SINAD = 43 dB (7.1 Effective Bits), SFDR = 53 dBc @ FS = 500 Msps, FIN = 250 MHz : SINAD = 42 dB (7.0 Effective Bits), SFDR = 52 dBc @ FS = 500 Msps, FIN = 500 MHz (-3 dB FS) 2-tone IMD : TBD (199.5 MHz, 200.5 MHz) @ 500 MSPS. DNL = 0.3 LSB INL = 0.7 LSB. Low Bit Error Rate (10-13 ) @ 500 Msps, Tj = 90C Power consumption : 3.8 W @ Tj = 70C Typical 500 mVpp differential or single-ended analog inputs. Differential or single-ended 50 ECL compatible clock inputs. ECL or LVDS/HSTL output compatibility. ADC gain adjust. Data ready output with asynchronous reset. Gray or Binary selectable output data ; NRZ output mode. ADC 8-bit 500 Msps TS8308500 APPLICATIONS ! ! ! ! Digital Sampling Oscilloscopes. Satellite receiver. Electronic countermeasures / Electronic warfare. Direct RF down-conversion. SCREENING ! Atmel-Grenoble standard screening level ! Temperature range: up to 0C < Tc ; Tj < +90C 1/ Evaluation board : TSEV8308500 Detailed specification on request. 2/ Demultiplexer : parallel 8-bit 2 Gsps TS81102G0 : companion device available DESCRIPTION The TS8308500 is a monolithic 8-bit analog-to-digital converter, designed for digitizing wide bandwidth analog signals at very high sampling rates of up to 500 Msps. The TS8308500 is using an innovative architecture, including an on chip Sample and Hold (S/H), and is fabricated with an advanced high speed bipolar process. The on-chip S/H has a 1.3 GHz full power input bandwidth, providing excellent dynamic performance in undersampling applications (High IF digitizing). G Suffix : CBGA 72 Ceramic Ball Grid Array With decoupling R and C on the package January 2002 Product Specification -site Preliminary Specification -site TABLE OF CONTENTS 1. SIMPLIFIED BLOCK DIAGRAM ....................................................................................................................................3 2. FUNCTIONAL DESCRIPTION ........................................................................................................................................3 3. SPECIFICATIONS ..............................................................................................................................................................4 3.1. 3.2. 3.3. 3.4. 3.5. 3.6. 3.7. 4. ABSOLUTE MAXIMUM RATINGS (SEE NOTES BELOW) .................................................................................................................4 RECOMMENDED CONDITIONS OF USE ..........................................................................................................................................4 ELECTRICAL OPERATING CHARACTERISTICS..............................................................................................................................5 TIMING DIAGRAMS ...........................................................................................................................................................................9 EXPLANATION OF TEST LEVELS................................................................................................................................................... 10 FUNCTIONS DESCRIPTION............................................................................................................................................................ 10 DIGITAL OUTPUT CODING ............................................................................................................................................................. 10 PACKAGE DESCRIPTION. ............................................................................................................................................11 4.1. TS8308500 PAD DESCRIPTION ...................................................................................................................................................... 11 4.2. TS8308500 PIN DESCRIPTION ....................................................................................................................................................... 12 4.3. TS8308500 PINOUT OF CBGA72 PACKAGE .................................................................................................................................. 13 4.4. TS8308500 CAPACITIES AND RESISTANCES IMPLANT ............................................................................................................... 14 OUTLINE DIMENSIONS - 72 PINS CBGA ..................................................................................................................................................... 14 OUTLINE DIMENSIONS - 72 PINS CBGA ..................................................................................................................................................... 15 4.5. THERMAL AND MOISTURE CHARACTERISTICS................................................................................................................................ 16 5. TYPICAL CHARACTERIZATION RESULTS .............................................................................................................17 5.1. 5.2. 5.3. 5.4. 5.5. 5.6. 5.7. 5.8. 5.9. 5.10. STATIC LINEARITY - FS = 50 MSPS / FIN = 10 MHZ ...................................................................................................................... 17 EFFECTIVE NUMBER OF BITS VERSUS POWER SUPPLIES VARIATION.................................................................................... 18 TYPICAL FFT RESULTS .................................................................................................................................................................. 19 SPURIOUS FREE DYNAMIC RANGE VERSUS INPUT AMPLITUDE ...................................................... ERREUR! SIGNET NON DEFINI. DYNAMIC PERFORMANCE VERSUS ANALOG INPUT FREQUENCY ........................................................................................... 21 EFFECTIVE NUMBER OF BITS (ENOB) VERSUS SAMPLING FREQUENCY ................................................................................ 22 SFDR VERSUS SAMPLING FREQUENCY ...................................................................................................................................... 22 TS8308500 ADC PERFORMANCES VERSUS JUNCTION TEMPERATURE................................................................................... 23 TYPICAL FULL POWER INPUT BANDWIDTH ................................................................................................................................. 24 ADC STEP RESPONSE ................................................................................................................................................................... 25 6. DEFINITION OF TERMS ................................................................................................................................................26 7. TS8308500 MAIN FEATURES.........................................................................................................................................28 7.1. 7.2. 7.3. 7.4. 7.5. 7.6. 7.7. 7.8. 7.9. 7.10. 8. TIMING INFORMATIONS ................................................................................................................................................................. 28 PRINCIPLE OF DATA READY SIGNAL CONTROL BY DRRB INPUT COMMAND .......................................................................... 29 ANALOG INPUTS (VIN) (VINB) ........................................................................................................................................................ 29 CLOCK INPUTS (CLK) (CLKB)......................................................................................................................................................... 30 NOISE IMMUNITY INFORMATIONS ................................................................................................................................................ 32 DIGITAL OUTPUTS .......................................................................................................................................................................... 32 OUT OF RANGE BIT ........................................................................................................................................................................ 35 GRAY OR BINARY OUTPUT DATA FORMAT SELECT ................................................................................................................... 35 DIODE PIN K1 .................................................................................................................................................................................. 35 ADC GAIN CONTROL PIN K6 .......................................................................................................................................................... 36 EQUIVALENT INPUT / OUTPUT SCHEMATICS ......................................................................................................37 8.1. 8.2. 8.3. 8.4. 8.5. 8.6. 9. EQUIVALENT ANALOG INPUT CIRCUIT AND ESD PROTECTIONS.............................................................................................. 37 EQUIVALENT ANALOG CLOCK INPUT CIRCUIT AND ESD PROTECTIONS................................................................................. 37 EQUIVALENT DATA OUTPUT BUFFER CIRCUIT AND ESD PROTECTIONS ................................................................................ 38 ADC GAIN ADJUST EQUIVALENT INPUT CIRCUITS AND ESD PROTECTIONS........................................................................... 38 GORB EQUIVALENT INPUT SCHEMATIC AND ESD PROTECTIONS............................................................................................ 39 DRRB EQUIVALENT INPUT SCHEMATIC AND ESD PROTECTIONS ............................................................................................ 39 TSEV8308500G : DEVICE EVALUATION BOARD ....................................................................................................40 10. 10.1. 10.2. 2 ORDERING INFORMATION .....................................................................................................................................41 PACKAGE DEVICE .......................................................................................................................................................................... 41 EVALUATION BOARD...................................................................................................................................................................... 41 TS8308500 TS8308500 1. SIMPLIFIED BLOCK DIAGRAM GAIN MASTER/SLAVE TRACK & HOLD AMPLIFIER VIN,VINB G=2 T/H G=1 T/H G=1 RESISTOR CHAIN ANALOG ENCODING BLOCK 4 INTERPOLATION STAGES 4 5 REGENERATION LATCHES 4 5 ERROR CORRECTION & DECODE LOGIC CLK, CLKB CLOCK BUFFER 8 OUTPUT LATCHES & BUFFERS 8 DRRB DR,DRB 2. GORB DATA,DATAB OR,ORB FUNCTIONAL DESCRIPTION The TS8308500 is an 8 bit 500MSPS ADC based on an advanced high speed bipolar technology featuring a cutoff frequency of 25 GHz. The TS8308500 includes a front-end master/slave Track and Hold stage (S/H), followed by an analog encoding stage and interpolation circuitry. Successive banks of latches are regenerating the analog residues into logical data before entering an error correction circuitry and a resynchronization stage followed by 75 differential output buffers. The TS8308500 works in fully differential mode from analog inputs up to digital outputs. The TS8308500 features a full power input bandwidth of 1.3 GHz. Control pin GORB is provided to select either Gray or Binary data output format. Gain control pin is provided in order to adjust the ADC gain. A Data Ready output asynchronous reset (DRRB) is available on TS8308500. The TS8308500 uses only vertical isolated NPN transistors together with oxide isolated polysilicon resistors, which allow enhanced radiation tolerance (no performance drift measured at 150kRad total dose). Preliminary Specification -site 3 Preliminary Specification -site 3. SPECIFICATIONS 3.1. ABSOLUTE MAXIMUM RATINGS (SEE NOTES BELOW) Parameter Symbol VCC GND to 6 V DVEE GND to -5.7 V Digital positive supply voltage VPLUSD GND-0.3 to 2.8 V Negative supply voltage VEE GND to -6 V Maximum difference between negative supply voltages DVEE to VEE 0.3 V Analog input voltages VIN or VINB -1 to +1 V Maximum difference between VIN and VINB VIN - VINB -2 to +2 V Digital input voltage VD GORB -0.3 to VCC +0.3 V Digital input voltage VD DRRB VEE -0.3 to +0.9 V Maximum difference between VCLK and VCLKB Vo VPLUSD-3 to VPLUSD -0.5 V VCLK or VCLKB -3 to +1.5 V VCLK - VCLKB -2 to +2 V Tj +135 o Tstg -65 to +150 o +300 o Maximum junction temperature Storage temperature Lid temperature (soldering 10s) Tleads For dry pack C C C (see chapter 4.5) Absolute maximum ratings are limiting values (referenced to GND=0V), to be applied individually, while other parameters are within specified operating conditions. Long exposure to maximum rating may affect device reliability. The use of a thermal heat sink is mandatory (see Thermal characteristics). RECOMMENDED CONDITIONS OF USE Parameter Positive supply voltage Positive digital supply voltage Symbol VPLUSD ECL output compatibility VPLUSD LVDS output compatibility VEE, DVEE Differential analog input voltage (Full Scale) VIN, VINB Operating temperature range Comments VCC Negative supply voltages Clock input power level 4 Unit Digital negative supply voltage Clock input voltage 3.2. Value Positive supply voltage Digital output voltage Notes : Comments 50 differential or single-ended VIN -VINB PCLK PCLKB TJ TS8308500 50 single-ended clock input Commercial grade: "C" Min. Typ. Max. Unit 4.75 +5 5.25 V GND V +1.4 +2.4 +2.6 V -5.25 -5.0 -4.75 V 113 125 137 mV 450 500 550 mVpp 3 4 10 dBm 0 < Tc ; Tj < 90 o C TS8308500 3.3. ELECTRICAL OPERATING CHARACTERISTICS VEE = DVEE = -5 V ; VCC = +5 V ; VIN -VINB = 500 mVpp Full Scale differential input ; Digital outputs 75 or 50 differentially terminated ; Tj (typical) = 70C. Parameter Symb Test level Min Typ Max Unit 4.5 5 5.5 V POWER REQUIREMENTS Positive supply voltage Positive supply current VCC 1 Digital (ECL) Analog VPLUSD 4 Digital (LVDS) VPLUSD 4 Analog ICC 1 Digital IPLUSD 1 Negative supply voltage Negative supply current 0 1.4 2.4 2.6 V 420 445 mA 130 145 mA -5 -4.5 V VEE 1 Analog AIEE 1 185 200 mA Digital DIEE 1 160 180 mA PD 1 3.8 4.1 W PSRR 4 0.5 2 mV/V 8 bits 125 mV Nominal power dissipation Power supply rejection ratio (note 2) -5.5 V RESOLUTION ANALOG INPUTS Full Scale Input Voltage range (differential mode) ( 0 Volt common mode voltage ) VIN 4 -125 -125 125 mV 4 -250 250 mV VINB VIN Full Scale Input Voltage range (single-ended input option ) (see Application Notes) VINB Analog input capacitance CIN 4 3 3.5 pF Input bias current IIN 4 10 20 A Input Resistance RIN 4 0 0.5 mV 1 M Full Power input Bandwidth FPBW 4 1.2 1.3 GHz Small Signal input Bandwidth (10 % full scale) SSBW 4 1.2 1.3 GHz CLOCK INPUTS Logic compatibility for clock inputs (see Application Notes) (note 10 ) ECL or specified clock input power level in dBm ECL Clock inputs voltages (VCLK or VCLKB) : 4 * Logic "0" voltage VIL * Logic "1" voltage VIH * Logic "0" current IIL * Logic "1" current IIH -1.5 -1.1 Clock input power level into 50 termination 5 50 A 5 50 A 4 10 dBm 3 3.5 pF DBm into 50 Clock input power level Clock input capacitance V V 4 CCLK 4 -2 Preliminary Specification -site 5 Preliminary Specification -site Parameter Symb Test level Min Typ Max Unit DIGITAL OUTPUTS (notes 1,6) Single ended or differential input mode, 50 % clock duty cycle (CLK,CLKB), Binary output data format, Tj (typical) = 70C. Full temperature range : 0C < Tc ; Tj < +90C Logic compatibility for digital outputs ( Depending on the value of VPLUSD ) (see Application Notes) ECL or LVDS 4 Differential output voltage swings ( assuming VPLUSD = 0V) : 75 open transmission lines ( ECL levels ) 1.50 1.620 V 75 differentially terminated 0.70 0.825 V 50 differentially terminated 0.54 0.660 V Output levels ( assuming VPLUSD = 0V) 75 open transmission lines 4 (note 6) * Logic "0" voltage VOL * Logic "1" voltage VOH Output levels ( assuming VPLUSD = 0V) 75 differentially terminated -1.54 -0.8 V V 4 (note 6) * Logic "0" voltage VOL * Logic "1" voltage VOH Output levels ( assuming VPLUSD = 0V) 50 differentially terminated -1.62 -0.88 -1.41 -1.07 -1.34 -1 V V (note 6) * Logic "0" voltage VOL 1, 2 * Logic "1" voltage VOH 1, 2 -1.16 -1.10 V DOS 4 270 300 mV Differential Output Swing Output level drift with temperature -1.40 4 -1.32 1.6 V mV/C DC ACCURACY Single ended or differential input mode, 50 % clock duty cycle (CLK,CLKB), Binary output data format, Tj (typical) = 70C. Differential non linearity Integral non linearity (notes 2,3) (notes 2,3) DNL- 1 DNL+ 1 INL- 1 INL+ No missing codes 6 (note 3) -0.6 -0.3 -1.0 -0.7 0.3 1 0.7 LSB 0.6 LSB LSB 1.0 LSB Guaranteed over specified temperature range Gain error 1, 2 -10 -2 10 % FS Input offset voltage 1, 2 -26 -5 26 mV Gain error drift 4 100 125 150 ppm/C Offset error drift 4 40 50 60 ppm/C TS8308500 TS8308500 Parameter Symb Test level Min Typ Max Unit TRANSIENT PERFORMANCE Bit Error Rate FS = 1 Gsps (notes 2, 4) BER 4 1E-12 Fin = 62.5 MHz Error/ sample ADC settling time VIn -VinB = 400 mVpp (note 2) TS 4 0.5 1 ns Overvoltage recovery time (note 2) TOR 4 0.5 1 ns AC PERFORMANCE (Expected values) Single ended or differential input and clock mode, 50 % clock duty cycle (CLK,CLKB), Binary output data format, Tj. = 70C, unless otherwise specified. Signal to Noise and Distortion ratio (note 2) SINAD FS = 500 Msps Fin = 20 MHz 4 FS = 500 Msps Fin = 500 MHz (Tj = 90C) 4 FS = 500 Msps Fin = 1000 MHz (-1dB Fs) 4 FS = 50 Msps Fin = 25 MHz 1 Effective Number Of bits 44 43 44 dB 45 dB dB 40 45 dB ENOB FS = 500 Msps Fin = 20 MHz 4 FS =500 Msps Fin = 500 MHz (Tj = 90C) 4 6.8 7.0 FS = 500 Msps Fin = 1000 MHz (-1dBFs) 4 6.4 6.6 Bits 1 7.0 7.2 Bits 45 dB FS = 50 Msps Fin = 25 MHz Signal to Noise Ratio (note 2) 7.2 Bits 7.3 Bits SNR FS = 500 Msps Fin = 20 MHz 4 FS = 500 msps Fin = 500 MHz (Tj = 90C) 4 44 45 FS = 500 Msps Fin = 1000 MHz (-1dBFs) 4 40 41 dB 1 44 45 dB 50 dB FS = 50 Msps Fin = 25 MHz Total Harmonic Distortion (note 2) 4 FS = 500 Msps Fin = 500 MHz (Tj = 90C) 4 FS = 500 Msps Fin = 1000 MHz (-1dBFs) 4 FS = 50 Msps Fin = 25 MHz 1 (note 2) 4 FS = 500 Msps Fin = 500 MHz (Tj = 90C) 4 FS = 500 Msps Fin = 1000 MHz (-1dBFs) 4 FS = 500 Gsps Fin = 1000 MHz (-3dBFs) 4 FS = 50 Msps Fin = 25 MHz 1 FIN1 = 199.5 MHz @ FS = 500 Msps (note 2) 48 49 53 dB dB 46 51 dB 54 dBc SFDR FS = 500 Msps Fin = 20 MHz Two-tone inter-modulation distortion dB THD FS = 500 Msps Fin = 20 MHz Spurious Free Dynamic Range 46 IMD 52 53 54 dBc dBc dBc 48 55 dBc TBD TBD dBc 4 FIN2 = 200.5 MHz @ FS = 500 Msps Preliminary Specification -site 7 Preliminary Specification -site Parameter Symb Test level Min Typ Max Unit SWITCHING PERFORMANCE AND CHARACTERISTICS - See Timing Diagrams Figure 1, Figure 2 Maximum clock frequency (Note 14) FS 500 700 Msps Minimum clock frequency (Note 15) FS 4 10 50 Msps TC1 4 1710 TC2 4 1710 TA 4 100 Jitter 4 0.4 Minimum Clock pulse width (high) Minimum Clock pulse width (low) Aperture delay (Note 2) Aperture uncertainty (Notes 2, 5) Data output delay (Notes 2, 10, 11, 12) 2 50 ns 2 50 ns +250 400 ps 0.6 ps (rms) TOD 4 1150 1360 1660 ps Output rise/fall time for DATA (20 % - 80 %) (note 11) TR/TF 4 250 350 550 ps Output rise/fall time for DATA READY TR/TF 4 250 350 550 ps TDR 4 1110 1320 1620 ps Data ready reset delay TRDR 4 720 1000 ps Data to data ready - clock low pulse width TODTDR 4 0 40 80 ps TD1 4 920 960 1000 ps TPD 4 (20 % - 80 % ) (note 11) Data ready output delay (Notes 2,10, 11, 12) (See timing diagram, notes 9, 13,14) Data to data ready output delay (50% duty cycle) (See timing diagram, notes 2, 15) @ 500 Msps Data pipeline delay Note 1 : Note 2 : Note 3 : Note 4 : Note 5 : 4 clock cycles Differential output buffers are internally loaded by 75 resistors. Buffer bias current = 11 mA. See definition of terms Histogram testing based on sampling of a 10 MHz sinewave at 50 MSPS. Output error amplitude < 4 LSB around worst code. Maximum jitter value obtained for single-ended clock input on the JTS8308500 die (chip on board) : 200 fs. (500 fs expected on TS8308500) Note 6 : Digital output back termination options depicted in Application Notes figures 3,4,5 . Note 7 : With a typical value of TD = 465 ps, at 500 Msps, the timing safety margin for the data storing using the ECLinPS 10E452 output registers from Motorola is of 315 ps, equally shared before and after the rising edge of the Data Ready signals (DR, DRB). Note 8 : The clock inputs may be indifferently entered in differential or single-ended, using ECL levels or 4 dBm typical power level into the 50 termination resistor of the inphase clock input. (4 dBm into 50 clock input correspond to 10 dBm power level for the clock generator.) Note 9 : At 500 MSPS, 50/50 clock duty cycle, TC2 = 1 ns (TC1). TDR - TOD = -100 ps (typ) does not depend on the sampling rate. Note 10 : Specified loading conditions for digital outputs : - 50 or 75 controlled impedance traces properly 50 / 75 terminated, or unterminated 75 controlled impedance traces. - Controlled impedance traces far end loaded by 1 standard ECLinPS register from Motorola.( e.g. : 10E452 ) ( Typical input parasitic capacitance of 1.5 pF including package and ESD protections. ) Note 11 : Termination load parasitic capacitance derating values : - 50 or 75 controlled impedance traces properly 50 / 75 terminated : 60 ps / pF or 75 ps per additional ECLinPS load. - Unterminated ( source terminated ) 75 controlled impedance lines : 100 ps / pF or 150 ps per additional ECLinPS termination load. Note 12 : apply proper 50 / 75 impedance traces propagation time derating values : 6 ps / mm (155 ps/inch) for TSEV8308500 Evaluation Board. Note 13 : Values for TOD and TDR track each other over temperature, (1 % variation for TOD - TDR per 100 oC temperature variation). Therefore TOD - TDR variation over temperature is negligible. Moreover, the internal (onchip ) and package skews between each Data TODs and TDR effect can be considered as negligible. Consequently, minimum values for TOD and TDR are never more than 100 ps apart. The same is true for the TOD and TDR maximum values (see Advanced Application Notes about TOD - TDR variation over temperature in section 7). Note 14 : Min value guarantees performance. Max value guarantees functionality. Note 15 : Min value guarantees functionality. Max value guarantees performance. 8 TS8308500 TS8308500 3.4. TIMING DIAGRAMS TC = 2 ns N+1 N VIN / VINB N+3 N+2 TA = 250 ps TC1 TC2 CLK / CLKB Digital OUTPUTS TOD = 1360 ps TPD = 4.0 Clock Periods 1360 ps N -4 N -5 TDR = 1320 ps DATA READY DR / DRB TD2 = TC2 + TOD - TDR = TC2 + 40 ps = 1040 ps TRDR = 720 ps DATA READY RESET N+1 TD1 = TC1 + TDR - TOD = TC1 - 40 ps = 960 ps 2 ns TDR = 1320 ps N N -1 N -2 N -3 1 ns Figure 1: TS8308500 TIMING DIAGRAM (500 MSPS CLOCK RATE) Data Ready Reset, Clock Held at LOW Level N VIN / VINB N+3 N+2 TA = 250 ps N+1 TC = 2 ns TC1 TC2 CLK / CLKB TPD = 4.0 Clock Periods 1360 ps Digital OUTPUTS N -5 TDR = 1320 ps N -4 TDR = 1320 ps N -3 N -2 2 ns DATA READY DR / DRB N -1 N N+1 TD1 = TC1 + TDR - TOD = TC1 - 40 ps = 960 ps TD2 = TC2 + TOD - TDR = TC2 + 40 ps = 1040 ps TRDR = 720 ps DATA READY RESET TOD = 1360 ps 1 ns Figure 2: TS8308500 TIMING DIAGRAM (500 MSPS CLOCK RATE) Data Ready Reset, Clock Held at HIGH Level Preliminary Specification -site 9 Preliminary Specification -site 3.5. EXPLANATION OF TEST LEVELS 1 100% production tested at +25C (1) (for "C" Temperature range (2) ). 2 100 % production tested at +25C (1), and sample tested at specified temperatures (for "V" and "M" Temperature ranges (2) ). 3 Sample tested only at specified temperatures 4 Parameter is guaranteed by design and characterization testing (thermal steady-state conditions at specified temperature). 5 Parameter is a typical value only Only MIN and MAX values are guaranteed (typical values are issuing from characterization results). (1) Unless otherwise specified, all tests are pulsed tests : therefore Tc = Ta where Tc and Ta are case and ambient temperature. (2) Refer to ORDERING INFORMATION chapter. 3.6. 3.7. FUNCTIONS DESCRIPTION Name Function VCC Positive power supply VEE Analog negative power supply VPLUSD Digital positive power supply GND Ground VIN, VINB Differential analog inputs CLK, CLKB Differential clock inputs VCC = +5 V <D0:D7> <D0B:D7B> Differential output data port DR ; DRB Differential data ready outputs OR ; ORB Out of range outputs GAIN ADC gain adjust GORB Gray or Binary digital output select DIOD/DRRB Die junction temp. measurement/ asynchronous data ready reset VPLUSD = +0 V (ECL) VPLUSD=+2.4V (LVDS) VIN OR VINB ORB CLK 16 TS8308500 CLKB D0 D7 D0B D7B GAIN DR GORB DRB DIOD/ DRRB DVEE=-5V VEE=-5V GND DIGITAL OUTPUT CODING NRZ (Non Return to Zero) mode, ideal coding : does not include gain, offset, and linearity voltage errors. Differential Voltage level Digital output Out of Range analog input Binary GORB = VCC or floating 10 Gray GORB = GND > +251 mV > Positive full scale + 1/2 LSB 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 +251 mV +249 mV Positive full scale + 1/2 LSB Positive full scale - 1/2 LSB 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 +126 mV +124 mV Positive 1/2 scale + 1/2 LSB Positive1/2 scale - 1/2 LSB 1 1 0 0 0 0 0 0 1 0 1 1 1 1 1 1 1 0 1 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 +1 mV -1 mV Bipolar zero + 1/2 LSB Bipolar zero - 1/2 LSB 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 -124 mV -126 mV Negative 1/2 scale + 1/2 LSB Negative 1/2 scale - 1/2 LSB 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 -249 mV -251 mV Negative full scale + 1/2 LSB Negative full scale - 1/2 LSB 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 < -251 mV < Negative full scale - 1/2 LSB 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 TS8308500 TS8308500 4. 4.1. PACKAGE DESCRIPTION. TS8308500 PAD DESCRIPTION Pad number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 Chip pad Name VPLUSD D5 D5B D4 D4B DVEE DR DRB D3 D3B VPLUSD D2 D2B D1 D1B D0 D0B GORB VCC GND VCC VEE VCC GND CLK GND CLKB GND VEE VCC VEE DIOD/DRRB GND VIN GND VINB GND GAIN VCC VCC OR ORB D7 D7B D6 D6B Chip Pad Function Positive digital supply (double pad) (note 2) In phase (+) digital output, bit 5 (D7 is the MSB ; Bit 7, D0 is the LSB ; Bit 0) Inverted phase (-)digital output, bit 5 In phase (+) digital output, bit 4 Inverted phase (-) digital output, bit 4 -5V digital supply (double pad) In phase (+) Data Ready Inverted Phase (-) Data Ready In phase (+) digital output, bit 3 Inverted phase (-) digital output, bit 3 Positive digital supply (double pad) (note 2) In phase (+) digital output, bit 2 Inverted phase (-) digital output, bit 2 In phase (+) digital output, bit 1 Inverted phase (-) digital output, bit 1 In phase (+) digital output, bit 0, Least Significant Bit Inverted phase (-) digital output, bit 0, Least Significant Bit Gray or Binary data output format select. (Note 1) +5V supply (double pad) Analog Ground (double pad) +5V supply (double pad) -5V analog supply (double pad) +5V supply (double pad) Analog Ground (double pad) In phase (+) clock input (double pad) Analog Ground Inverted phase (-) clock input (double pad) Analog Ground (double pad) -5V analog supply (double pad) +5V supply (double pad) -5V analog supply (double pad) Diode input for Tj monitoring / Input for asynchronous Data Ready Reset Analog Ground In phase (+) analog input (double pad) Analog Ground Inverted phase (-) analog input (double pad) Analog Ground (double pad) ADC gain adjust input +5V supply (double pad) +5V supply In phase (+) Out of Range digital output Inverted phase (-) Out of Range digital output In phase (+) digital output, bit 7, Most Significant Bit Inverted phase (-) digital output bit 7 In phase (+) digital output, bit 6 Inverted phase (-) digital output, bit 6 Note 1: GORB tied to Vcc or floating : Binary output data format. GORB tied to GND : Gray output data format Note2: The common mode level of the output buffers is 1.2V below the positive digital supply. For ECL compatibility the positive digital supply must be set at 0V (ground). For LVDS compatibility (output common mode at +1.2V) the positive digital supply must be set at 2.4V. If the subsequent LVDS circuitry can withstand a lower level for input common mode, it is recommended to lower the positive digital supply level in the name proportion in order to spare power dissipation. Preliminary Specification -site 11 Preliminary Specification -site 4.2. TS8308500 PIN DESCRIPTION Symbol Pin number Function GND A2, A5, B1, B5, B10, C2, C9, D2, E1, E2, E11, F1, F2, G11, J3, J9, K2, K3, K4, K5, K10, L2, L5 Ground pins. To be connected to external ground plane. VCC A4, A6, B2, B4, B6, C3, H1, H2, L6, L7 +5 V positive supply. VEE A3, B3, G1, G2, J1, J2 5 V analog negative supply DVEE F10, F11 -5 V digital negative supply. VIN L3 In phase (+) analog input signal of the sample and Hold differential preamplifier. VINB L4 Inverted phase (-) of ECL clock input signal (CLK). CLK C1 In phase (+) ECL clock input signal. The analog input is sampled and held on the rising edge of the CLK signal. CLKB D1 Inverted phase (-) of ECL clock input signal (CLK). B0, B1, B2, B3, B4, B5, B6, B7 A8, A9, A10, D10, H11, J11, K9, K8 In phase (+) digital outputs. B0 is the LSB. B7 is the MSB. B0B, B1B, B2B, B3B, B4B, B5B, B6B, B7B B7, B8, B9, C11, G10, H10, L10, L9 Inverted phase (-) Digital outputs. B0B is the inverted LSB. B7B is the inverted MSB. OR K7 In phase (+) Out of Range Bit. Out of Range is high on the leading edge of code 0 and code 256. ORB L8 Inverted phase (+) of Out of Range Bit (OR). DR E10 In phase (+) output of Data Ready Signal. DRB D11 Inverted phase (-) output of Data Ready Signal (DR). GORB A7 Gray or Binary select output format control pin. - Binary output format if GORB is floating or VCC. - Gray output format if GORB is connected at ground (0 V). GAIN K6 ADC gain adjust pin. The gain pin is by default grounded, the ADC gain transfer fuction is nominally close to one. DIOD/DRRB K1 Die function temperature measurement pin and asynchronous data ready reset active low, single ended ECL input. VPLUSD B11, C10, J10, K11 + 2.4 V for LVDS output levels otherwise to GND (1) NC A1, A11, L1, L11 Not connected. Note 1 : 12 The common mode level of the output buffers is 1.2V below the positive digital supply. For ECL compatibility the positive digital supply must be set at 0V (ground ). For LVDS compatibility (output common mode at +1.2V) the positive digital supply must be set at 2.4V. If the subsequent LVDS circuitry can withstand a lower level for input common mode, it is recommended to lower the positive digital supply level in the same proportion in order to spare power dissipation. TS8308500 TS8308500 4.3. TS8308500 PINOUT OF CBGA72 PACKAGE BOTTOM VIEW Preliminary Specification -site 13 Preliminary Specification -site 4.4. TS8308500 CAPACITIES AND RESISTANCES IMPLANT 100 F Ohm 50 100 F Ohm 50 100 F 100 F 100 F 100 F 100 F 100 100 Only on-package marking Electrically isolated 14 TS8308500 100 100 50 Ohm 50 Ohm TS8308500 OUTLINE DIMENSIONS - 72 PINS CBGA 100 F Preliminary Specification -site 15 Preliminary Specification -site 4.5. THERMAL AND MOISTURE CHARACTERISTICS 4.5.1. THERMAL RESISTANCE FROM JUNCTION TO AMBIENT : RTHJA The following table lists the convector thermal performances parameters of the device itself, with no external heatsink added. (m/s) Estimated ja thermal resistance (oC / W) 0 45 0,5 35,8 1 30,8 1,5 27,4 2 24,9 2,5 23 3 21,5 4 19,3 5 17,7 4.5.2. 50 Rthja (deg.C/W) Air flow 40 30 20 10 0 0 1 2 3 Air flow (m/s) 4 5 THERMAL RESISTANCE FROM JUNCTION TO CASE : RTHJC Typical value for Rthjc is given to 1.56C/W. This value does not include thermal contact resistance between package and external component (heatsink or PCBoard). As an example, 2.0C/W can be taken for 50 m of thermal grease. 4.5.3. CBGA72 BOARD ASSEMBLY WITH EXTERNAL HEATSINK It is recommended to use an external heatsink or PCBoard special design. Cooling system efficiency can be monitored using the Temperature Sensing Diode, integrated in the device. Note: Units = mm 4.5.4. MOISTURE CHARACTERISTICS This device is very sensitive to the moisture (MSL6 according JEDEC standard). When receiving the devices (in dry pack), you must follow strictly the instructions on the sticker. The devices must be mounted within 6 hours at factory conditions of 30C/60% Relative Humidity (RH). These devices, if subjected to infrared reflow, vapor-phase reflow, or equivalent processing (peak package body temp. 220C), must be baked before mounting for : 192 hours at 40C + 5C/-0C and <5% RH for low-temperature device containers, or 24 hours at 125C 5C for high-temperature device containers. Note : in case of reworking of a component on a board containing this device, the board could need to be heated. In this case and to preserve the TS8308500, it is important to bake the board first, according to the instructions above. 16 TS8308500 TS8308500 5. TYPICAL CHARACTERIZATION RESULTS 50/50 clock duty cycle, Binary output coding, Tj = 70C, single-ended analog and clock inputs, unless otherwise specified. 5.1. 5.1.1. STATIC LINEARITY - FS = 50 MSPS / FIN = 10 MHZ INTEGRAL NON LINEARITY LSB INL = +/- 0.7 LSB code Clock Frequency = 50Msps Signal Frequency = 10MHz Positive peak : 0.68 LSB 5.1.2. Negative peak : -0.69 LSB DIFFERENTIAL NON LINEARITY LSB DNL = +/- 0.3 LSB code Clock Frequency = 50Msps Positive peak : 0.3 LSB Signal Frequency = 10MHz Negative peak : -0.29 LSB Preliminary Specification -site 17 Preliminary Specification -site 5.2. EFFECTIVE NUMBER OF BITS VERSUS POWER SUPPLIES VARIATION Effective number of bits = f (VEEA) ; Fs = 500 MSPS ; Fin = 100 MHz 8 7 ENOB (bits) 6 5 4 3 2 1 0 -7 -6,5 -6 -5,5 -5 -4,5 -4 VEEA (V) Effective number of bits = f (VCC) ; Fs = 500 MSPS ; Fin = 100 MHz 8 7 ENOB (bits) 6 5 4 3 2 1 0 3 3,5 4 4,5 5 5,5 6 6,5 7 VCC (V) Effective number of bits = f (VEED) ; Fs = 500 MSPS ; Fin = 100 MHz 8 7 ENOB (bits) 6 5 4 3 2 1 0 -6 -5,5 -5 -4,5 VEED (V) 18 TS8308500 -4 -3,5 -3 TS8308500 5.3. 5.3.1 TYPICAL FFT RESULTS SPECTRUM FOR FS = 500 MSPS, FIN = 498 MHZ (FULL SCALE INPUT) Acquisition of 4096 points Fs = 500 MSPS Fin = 498 MHz SFSR = -0.94 dB SNR = 45.39 dB 5.3.2. THD = -49.67 dBc SINAD = 44.01 dB SFDR = -54.31 dBc ENOB = 7.13 bits RECONSTRUCTED SIGNAL FOR FS = 500 MSPS, FIN = 498 MHZ (FULL SCALE INPUT) Acquisition of 4096 samples Fs = 500 MSPS Fin = 498 MHz Amplitude: 0.221V (114.5 LSB) Offset: 0V (122.5 LSB) Preliminary Specification -site 19 Preliminary Specification -site 5.3.1. SPECTRUM FOR FS = 500 MSPS, FIN = 250 MHZ (FULL SCALE INPUT) Acquisition of 4096 points Fs = 500 MSPS Fin = 250 MHz SFSR = -1.02 dB SNR = 45.84 dB 5.3.2. RECONSTRUCTED SIGNAL FOR FS = 500 MSPS; FIN = 250 MHZ (FULL SCALE INPUT) Acquisition of 4096 samples Fs = 500 MSPS Fin = 250 MHz 20 THD = -49.81 dBc SINAD = 44.38 dB SFDR = -52.78 dBc ENOB = 7.19 bits TS8308500 Amplitude: 0.189V (113.5 LSB) Offset: 0V (122.5 LSB) TS8308500 5.4. DYNAMIC PERFORMANCE VERSUS ANALOG INPUT FREQUENCY Fs=500 Msps, Fin = 20MHz up to 1000 MHz, -1dB Full Scale input, To be completed: ENOB, SNR and SFDR plots Preliminary Specification -site 21 Preliminary Specification -site 5.5. EFFECTIVE NUMBER OF BITS (ENOB) VERSUS SAMPLING FREQUENCY Analog Input Frequency : Fin = 250 MHz and Fs = 20 Msps to 1300 Msps To Be Completed 5.6. SFDR VERSUS SAMPLING FREQUENCY Analog Input Frequency : Fin = 250 MHz and Fs = 20 Msps to 1300 Msps To Be Completed 22 TS8308500 TS8308500 5.7. TS8308500 ADC PERFORMANCES VERSUS JUNCTION TEMPERATURE Fs = 500 Msps, Fin = 250 MHz, -1dB Full Scale Input, Tj = 0C to 120C. ENOB, SNR and THD plots to be completed Preliminary Specification -site 23 Preliminary Specification -site Power consumption versus junction temperature Fs = 500MSPS ; Fin = 250 MHz ; Duty cycle = 50% Power consumption (W) 5 4 3 2 1 0 -40 -20 0 20 40 60 80 100 120 140 160 o Temperature ( C) 5.8. TYPICAL FULL POWER INPUT BANDWIDTH 1.3 GHz at -3 dB (-2dBm full power input) Band Flatness / 8Bit 500Msps (-1 dB FS) 0 -1 SFSR (dB FS) -2 -3 -4 -5 -6 0 200 400 600 800 Frequency (MHz) 24 TS8308500 1000 1200 1400 1600 TS8308500 5.9. ADC STEP RESPONSE Test pulse input characteristics : 20% to 80% input full scale and rise time ~ 200ps. Note : This step response was obtained with the TSEV8308500 on board (device in die form). TEST PULSE DIGITIZED WITH 20 GHZ DSO 5.9.1. Vpp ~ 260 mV Tr ~ 270 ps 50 mV/div 50 mV/div 600 ps/div 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 time (ns) 5.9.2. SAME TEST PULSE DIGITIZED WITH TS8308500 ADC N.B. : ripples are due to the test setup (they are present on both measurements) 200 ADC code 150 Tr ~ 330 ps 50 codes/div (Vpp ~260 mV) 600 ps/div 100 50 0 0 0.6 1.2 1.8 2.4 3.0 3.6 4.2 4.8 5.4 6.0 time (ns) Preliminary Specification -site 25 Preliminary Specification -site 6. DEFINITION OF TERMS (BER) Bit Error Rate Probability to exceed a specified error threshold for a sample. An error code is a code that differs by more than +/- 4 LSB from the correct code. (BW) Full power input bandwidth Analog input frequency at which the fundamental component in the digitally reconstructed output has fallen by 3 dB with respect to its low frequency value (determined by FFT analysis) for input at Full Scale. (SINAD) Signal to noise and distortion ratio Ratio expressed in dB of the RMS signal amplitude, set to 1dB below Full Scale, to the RMS sum of all other spectral components, including the harmonics except DC. (SNR) Signal to noise ratio Ratio expressed in dB of the RMS signal amplitude, set to 1dB below Full Scale, to the RMS sum of all other spectral components excluding the five first harmonics. (THD) Total harmonic distorsion Ratio expressed in dBc of the RMS sum of the first five harmonic components, to the RMS value of the measured fundamental spectral component. (SFDR) Spurious free dynamic range (ENOB) Effective Number Of Bits Ratio expressed in dB of the RMS signal amplitude, set at 1dB below Full Scale, to the RMS value of the next highest spectral component (peak spurious spectral component). SFDR is the key parameter for selecting a converter to be used in a frequency domain application ( Radar systems, digital receiver, network analyzer ....). It may be reported in dBc (i.e., degrades as signal levels is lowered), or in dBfs (i.e. always related back to converter full scale). SINAD - 1.76 + 20 log (A/V/2) Where A is the actual input amplitude and V ENOB = is the full scale range of the ADC under test 6.02 (DNL) Differential non linearity The Differential Non Linearity for an output code i is the difference between the measured step size of code i and the ideal LSB step size. DNL (i) is expressed in LSBs. DNL is the maximum value of all DNL (i). DNL error specification of less than 1 LSB guarantees that there are no missing output codes and that the transfer function is monotonic. (INL) Integral non linearity The Integral Non Linearity for an output code i is the difference between the measured input voltage at which the transition occurs and the ideal value of this transition. INL (i) is expressed in LSBs, and is the maximum value of all |INL (i)|. (DG) Differential gain The peak gain variation (in percent) at five different DC levels for an AC signal of 20% Full Scale peak to peak amplitude. FIN = 5 MHz. (TBC) (DP) Differential phase Peak Phase variation (in degrees) at five different DC levels for an AC signal of 20% Full Scale peak to peak amplitude. FIN = 5 MHz. (TBC) (TA) Aperture delay Delay between the rising edge of the differential clock inputs (CLK,CLKB) (zero crossing point), and the time at which (VIN,VINB) is sampled. (JITTER) Aperture uncertainty Sample to sample variation in aperture delay. The voltage error due to jitter depends on the slew rate of the signal at the sampling point. (TS) Settling time Time delay to achieve 0.2 % accuracy at the converter output when a 80% Full Scale step function is applied to the differential analog input. (ORT) Overvoltage recovery time Time to recover 0.2 % accuracy at the output, after a 150 % full scale step applied on the input is reduced to midscale. (TOD) Digital data Output delay Delay from the falling edge of the differential clock inputs (CLK,CLKB) (zero crossing point) to the next point of change in the differential output data (zero crossing) with specified load. (TD1) Time delay from Data to Data Ready Time delay from Data transition to Data ready. (TD2) Time delay from Data Ready to Data General expression is TD1 = TC1 + TDR - TOD with TC = TC1 + TC2 = 1 encoding clock period. (TC) Encoding clock period TC1 = Minimum clock pulse width (high) TC = TC1 + TC2 TC2 = Minimum clock pulse width (low) (TPD) Pipeline Delay Number of clock cycles between the sampling edge of an input data and the associated output data being made available, (not taking in account the TOD). For the TS8308500 the TPD is 4 clock periods. (TRDR) Data Ready reset delay Delay between the falling edge of the Data Ready output asynchronous Reset signal (DDRB) and the reset to digital zero transition of the Data Ready output signal (DR). 26 TS8308500 TS8308500 (TR) Rise time Time delay for the output DATA signals to rise from 20% to 80% of delta between low level and high level. (TF) Fall time Time delay for the output DATA signals to fall from 80% to 20% of delta between low level and high level. (PSRR) Power supply rejection ratio Ratio of input offset variation to a change in power supply voltage. (NRZ) Non return to zero When the input signal is larger than the upper bound of the ADC input range, the output code is identical to the maximum code and the Out of Range bit is set to logic one. When the input signal is smaller than the lower bound of the ADC input range, the output code is identical to the minimum code, and the Out of range bit is set to logic one. (It is assumed that the input signal amplitude remains within the absolute maximum ratings). (IMD) InterModulation Distortion The two tones intermodulation distortion ( IMD ) rejection is the ratio of either input tone to the worst third order intermodulation products. The input tones levels are at - 7dB Full Scale. (NPR) Noise Power Ratio The NPR is measured to characterize the ADC performance in response to broad bandwidth signals. When using a notch-filtered broadband white-noise generator as the input to the ADC under test, the Noise Power Ratio is defined as the ratio of the average out-of-notch to the average in-notch power spectral density magnitudes for the FFT spectrum of the ADC output sample test. Preliminary Specification -site 27 Preliminary Specification -site 7. TS8308500 MAIN FEATURES 7.1. 7.1.1. TIMING INFORMATIONS TIMING VALUE FOR TS8308500 Timing values as defined in 3.3 are advanced data, issuing from electric simulations and first characterization results fitted with measurements. Timing values are given for CBGA72 package inputs/outputs, taking into account package internal controlled impedance traces propagation delays, and specified termination loads. Propagation delays in 50/75 ohms impedance traces are NOT taken into account for TOD and TDR. Apply proper derating values corresponding to termination topology. The min/max timing values are valid over the full temperature range in the following conditions : Note 1 : Specified Termination Load (Differential output Data and Data Ready) : 50 ohms resistor in parallel with 1 standard ECLinPS register from Motorola, (e.g : 10E452) (Typical ECLinPS inputs shows a typical input capacitance of 1.5 pF (including package and ESD protections) If addressing an output Dmux, take care if some Digital outputs do not have the same termination load and apply corresponding derating value given below. Note 2 : Output Termination Load derating values for TOD and TDR : ~ 35 ps/pF or 50 ps per additional ECLinPS load. Note 3 :Propagation time delay derating values have also to be applied for TOD and TDR : ~ 6 ps/mm (155 ps/inch) for TSEV8308500 Evaluation Board. Apply proper time delay derating value if a different dielectric layer is used. 7.1.2. PROPAGATION TIME CONSIDERATIONS TOD and TDR Timing values are given from pin to pin and DO NOT include the additional propagation times between device pins and input/output termination loads. For the TSEV8308500 Evaluation Board, the propagation time delay is 6ps/mm (155ps/inch) corresponding to 3.4 (@10GHz) dielectric constant of the RO4003 used for the Board. If a different dielectric layer is used (for instance Teflon), please use appropriate propagation time values. TD does NOT depend on propagation times because it is a differential data. (TD is the time difference between Data Ready output delay and digital Data output delay) TD is also the most straightforward data to measure, again because it is differential : TD can be measured directly onto termination loads, with matched Oscilloscopes probes. 7.1.3. TOD - TDR VARIATION OVER TEMPERATURE Values for TOD and TDR track each other over temperature (1 percent variation for TOD - TDR per 100 degrees Celsius temperature variation). Therefore TOD - TDR variation over temperature is negligible. Moreover, the internal (on-chip) and package skews between each Data TODs and TDR effect can be considered as negligible. Consequently, minimum values for TOD and TDR are never more than 100 ps apart. The same is true for the TOD and TDR maximum values. In other terms : If TOD is at 1150 ps, TDR will not be at 1620 ps ( maximum time delay for TDR ). If TOD is at 1660 ps, TDR will not be at 1110 ps ( minimum time delay for TDR ) However, external TOD - TDR values may be dictated by total digital data skews between every TODs (each digital data) and TDR : MCM Board , bonding wires and output lines lengths differences, and output termination impedance mismatches. The external (on board) skew effect has NOT been taken into account for the specification of the minimum and maximum values for TOD-TDR. 7.1.4. PRINCIPLE OF OPERATION The Analog input is sampled on the rising edge of external clock input (CLK,CLKB) after TA (aperture delay) of typically 250ps . The digitized data is available after 4 clock periods latency (pipeline delay (TPD)), on clock rising edge, after 1360 ps typical propagation delay TOD. The Data Ready differential output signal frequency (DR,DRB) is half the external clock frequency, that is it switches at the same rate as the digital outputs. The Data Ready output signal (DR,DRB) switches on external clock falling edge after a propagation delay TDR of typically 1320 ps. A Master Asynchronous Reset input command DRRB ( ECL compatible single-ended input) is available for initializing the differential Data Ready output signal ( DR,DRB ) .This feature is mandatory in certain applications using interleaved ADCs or using a single ADC with demultiplexed outputs. Actually, without Data Ready signal initialization, it is impossible to store the output digital data in a defined order. 28 TS8308500 TS8308500 7.2. PRINCIPLE OF DATA READY SIGNAL CONTROL BY DRRB INPUT COMMAND 7.2.1. DATA READY OUTPUT SIGNAL RESET The Data Ready signal is reset on falling edge of DRRB input command, on ECL logical low level (-1.8V). DRRB may also be tied to VEE = - 5V for Data Ready output signal Master Reset. So long DRRB remains at logical low level, (or tied to VEE = - 5V), the Data Ready output remains at logical zero and is independent of the external free running encoding clock. The Data Ready output signal (DR,DRB) is reset to logical zero after TRDR= 720 ps typical. TRDR is measured between the -1.3V point of the falling edge of DRRB input command and the zero crossing point of the differential Data Ready output signal (DR,DRB). The Data Ready Reset command may be a pulse of 1 ns minimum time width. 7.2.2. DATA READY OUTPUT SIGNAL RESTART The Data Ready output signal restarts on DRRB command rising edge, ECL logical high levels (-0.8V). DRRB may also be Grounded, or is allowed to float, for normal free running Data Ready output signal. The Data Ready signal restart sequence depends on the logical level of the external encoding clock, at DRRB rising edge instant : 1) 2) The DRRB rising edge occurs when external encoding clock input (CLK,CLKB) is LOW : The Data Ready output first rising edge occurs after half a clock period on the clock falling edge, after a delay time TDR = 1320 ps already defined hereabove. The DRRB rising edge occurs when external encoding clock input (CLK,CLKB) is HIGH : The Data Ready output first rising edge occurs after one clock period on the clock falling edge, and a delay TDR = 1320ps. Consequently, as the analog input is sampled on clock rising edge, the first digitized data corresponding to the first acquisition ( N ) after Data Ready signal restart ( rising edge ) is always strobed by the third rising edge of the data ready signal. The time delay (TD1) is specified between the last point of a change in the differential output data (zero crossing point) to the rising or falling edge of the differential Data Ready signal (DR,DRB) (zero crossing point). Note 1 : For normal initialization of Data Ready output signal, the external encoding clock signal frequency and level must be controlled. It is reminded that the minimum encoding clock sampling rate for the ADC is 10 MSPS and consequently the clock cannot be stopped. Note 2 : One single pin is used for both DRRB input command and die junction temperature monitoring. Pin denomination will be DRRB/DIOD.( On former version denomination was DIOD. ) Temperature monitoring and Data Ready control by DRRB is not possible simultaneously. 7.3. ANALOG INPUTS (VIN) (VINB) The analog input Full Scale range is 0.5 Volts peak to peak (Vpp), or -2 dBm into the 50 ohms termination resistor. In differential mode input configuration, that means 0.25 Volt on each input, or +/- 125 mV around zero volt. The input common mode is GROUND. The typical input capacitance is 3 pF for TS8308500 in CBGA package. Differential inputs voltage span [mV] VIN 125 250 mV 500mV Full Scale analog input VINB -250 mV 0 Volt t -125 (VIN,VINB) = +/- 250 mV = 500 mV diff Preliminary Specification -site 29 Preliminary Specification -site Differential versus single ended analog input operation The TS8308500 can operate at full speed in either differential or single ended configuration. This is explained by the fact the ADC uses a high input impedance differential preamplifier stage, (preceding the Sample and hold stage), which has been designed in order to be entered either in differential mode or single-ended mode. This is true so long as the out of phase analog input pin VINB is 50 ohms terminated very closely to one of the neighboring shield ground pins (52, 53, 58, 59) which constitute the local ground reference for the inphase analog input pin (VIN). Thus the differential analog input preamplifier will fully reject the local ground noise ( and any capacitively and inductively coupled noise) as common mode effects. In typical single-ended configuration, enter on the (VIN) input pin, with the inverted phase input pin (VINB) grounded through the 50 ohms termination resistor. In single-ended input configuration, the in-phase input amplitude is 0.5 Volt peak to peak, centered on 0V. (or -2 dBm into 50 ohms.) The inverted phase input is at ground potential through the 50 ohms termination resistor. However, dynamic performances can be somewhat improved by entering either analog or clock inputs in differential mode. Typical Single ended analog input configuration [mV] VIN 250 500 mV Full Scale analog input VIN or VINB double pads VIN or VINB 500 mV VINB = 0V 3 pF VINB t -250 VIN = +/- 250 mV 500 mV diff 7.4. 1M 50 (on packagel) 50 reverse termination CLOCK INPUTS (CLK) (CLKB) The TS8308500 can be clocked at full speed without noticeable performance degradation in either differential or single ended configuration. This is explained by the fact the ADC uses a differential preamplifier stage for the clock buffer, which has been designed in order to be entered either in differential or single-ended mode. Recommended sinewave generator characteristics are typically -120 dBc/Hz phase noise floor spectral density, @ 1 KHz from carrier , assuming a single tone 4 dBm input for the clock signal. 7.4.1. SINGLE ENDED CLOCK INPUT (GROUND COMMON MODE) Although the clock inputs were intended to be driven differentially with nominal -0.8V / -1.8V ECL levels, the TS8308500 clock buffer can manage a single-ended sinewave clock signal centered around 0 Volt. This is the most convenient clock input configuration as it does not require the use of a power splitter. No performance degradation ( e.g. : due to timing jitter) is observed in this particular single-ended configuration up to 500 MSPS Nyquist conditions ( Fin = 250 MHz ). This is all the more so true since the inverted phase clock input pin is 50 ohms terminated on the package (that is very close to one of the neighboring shield ground pin, which constitutes the local Ground reference for the inphase clock input). Thus the TS8308500 differential clock input buffer will fully reject the local ground noise ( and any capacitively and inductively coupled noise) as common mode effects. Moreover, a very low phase noise sinewave generator must be used for enhanced jitter performance. The typical inphase clock input amplitude is 1 Volt peak to peak, centered on 0 Volt (ground) common mode. This corresponds to a typical clock input power level of 4 dBm into the 50 ohms termination resistor. Do not exceed 10 dBm to avoid saturation of the preamplifier input transistors. 30 TS8308500 TS8308500 Single ended Clock input (Ground common mode) VCLK common mode = 0 Volt VCLKB=0 Volt 4 dBm typical clock input power level (into 50 ohms termination resistor) [V] CLK or CLKB double pad VCLK +0.5V CLK or CLKB VCLKB = ( 0 V ) 0.4 pF 50 reverse termination t -0.5V 1M 50 (on package) Note 1 : Do not exceed 10 dBm into the 50 ohms termination resistor for single clock input power level. 7.4.2. DIFFERENTIAL ECL CLOCK INPUT The clock inputs can be driven differentially with nominal -0.8V / -1.8V ECL levels. In this mode, a low phase noise sinewave generator can be used to drive the clock inputs, followed by a power splitter (hybrid junction) in order to obtain 180 degrees out of phase sinewave signals. Biasing tees can be used for offsetting the common mode voltage to ECL levels. Note: As the biasing tees propagation times are not matching, a tunable delay line is required in order to ensure the signals to be 180 degrees out of phase especially at fast clock rates in the 500 MSPS range. Differential Clock inputs (ECL Levels) [mV] CLK or CLKB double pad VCLK VCLKB -0.8V CLK or CLKB Common mode = -1.3 V 1M 50 (on package) 0.4 pF GND -1.8V t 50 reverse termination 7.4.3. SINGLE ENDED ECL CLOCK INPUT In single-ended configuration enter on CLK ( resp. CLKB ) pin , with the inverted phase Clock input pin CLKB (respectively CLK) connected to 1.3V through the 50 ohms termination resistor (on package). The inphase input amplitude is 1 Volt peak to peak, centered on -1.3 Volt common mode. Single ended Clock input (ECL): VCLK common mode = -1.3 Volt. VCLKB = -1.3 Volt [V] VCLK -0.8V VCLKB = -1.3 V -1.8V t Preliminary Specification -site 31 Preliminary Specification -site 7.5. NOISE IMMUNITY INFORMATIONS Circuit noise immunity performance begins at design level. Efforts have been made on the design in order to make the device as insensitive as possible to chip environment perturbations resulting from the circuit itself or induced by external circuitry. (Cascode stages isolation, internal damping resistors, clamps, internal (onchip) decoupling capacitors.) Furthermore, the fully differential operation from analog input up to the digital outputs provides enhanced noise immunity by common mode noise rejection. Common mode noise voltage induced on the differential analog and clock inputs will be canceled out by these balanced differential amplifiers. Moreover, proper active signals shielding has been provided on the chip to reduce the amount of coupled noise on the active inputs : The analog inputs and clock inputs of the TS8308500 device have been surrounded by ground pins, which must be directly connected to the external ground plane. 7.6. DIGITAL OUTPUTS The TS8308500 differential output buffers are internally 75 ohms loaded. The 75 ohms resistors are connected to the digital ground pins through a -0.8v level shift diode (see Figures 3,4,5 on next page). The TS8308500 output buffers are designed for driving 75 ohms (default) or 50 ohms properly terminated impedance lines or coaxial cables. An 11 mA bias current flowing alternately into one of the 75 ohms resistors when switching ensures a 0.825 V voltage drop across the resistor (unterminated outputs). The VPLUSD positive supply voltage allows the adjustment of the output common mode level from -1.2V (VPLUSD=0V for ECL output compatibility) to +1.2V (VPLUSD=2.4V for LVDS output compatibility). Therefore, the single ended output voltages vary approximately between -0.8V and -1.625V, ( outputs unterminated ), around -1.2V common mode voltage. Three possible line driving and back-termination scenarios are proposed (assuming VPLUSD=0V) : 1 ) 75 Ohms impedance transmission lines, 75 ohms differentially terminated (Fig. 3) : Each output voltage varies between -1V and -1.42V (respectively +1.4V and +1V), leading to +/- 0.41V =0.825 V in differential, around -1.21 V (respectively +1.21V) common mode for VPLUSD=0V (respectively 2.4V). 2 ) 50 ohms impedance transmission lines, 50 ohms differentially termination (Fig. 4) : Each output voltage varies between -1.02V and -1.35V (respectively +1.38V and +1.05V), leading to +/- 0.33V=660 mV in differential, around 1.18V (respectively +1.21V) common mode for VPLUSD=0V (respectively 2.4V). 3 ) 75 ohms impedance open transmission lines (Fig. 5) : Each output voltage varies between -1.6 V and -0.8 V (respectively +0.8V and +1.6V), which are true ECL levels, leading to +/- 0.8V=1.6V in differential, around -1.2V (respectively +1.2V) common mode for VPLUSD=0V (respectively 2.4V). Therefore, it is possible to drive directly high input impedance storing registers, without terminating the 75 ohms transmission lines. In time domain, that means that the incident wave will reflect at the 75 ohms transmission line output and travel back to the generator ( i.e. the 75 ohms data output buffer ). As the buffer output impedance is 75 ohms, no back reflection will occur. Note : This is no longer true if a 50 ohms transmission line is used, as the latter is not matching the buffer 75 ohms output impedance. Each differential output termination length must be kept identical . It is recommended to decouple the midpoint of the differential termination with a 10 nF capacitor to avoid common mode perturbation in case of slight mismatch in the differential output line lengths. Too large mismatches ( keep < a few mm ) in the differential line lengths will lead to switching currents flowing into the decoupling capacitor leading to switching ground noise. The differential output voltage levels ( 75 or 50 ohms termination ) are not ECL standard voltage levels, however it is possible to drive standard logic ECL circuitry like the ECLinPS logic line from MOTOROLA. 32 TS8308500 TS8308500 DIFFERENTIAL OUTPUT LOADING CONFIGURATIONS (LEVELS FOR ECL COMPATIBILITY) VPLUSD = 0V -0.8V 75 Out 75 75 Differential output : 0.41V = 0.825V 75 - + 75 impedance 10 nF -1V / -1.41V Common mode level : -1.2V (-1.2V below VPLUSD level) 75 OutB -1.41V / -1V 11 mA Figure 3 : DIFFERENTIAL OUTPUT : 75 TERMINATED DVEE VPLUSD = 0V -0.8V 75 Out 75 50 Differential output : 0.33V = 0.660V 50 - + 50 impedance 10 nF -1.02V / -1.35V Common mode level : -1.2V (-1.2V below VPLUSD level) 50 OutB -1.35V / -1.02V 11 mA Figure 4 : DIFFERENTIAL OUTPUT : 50 TERMINATED DVEE VPLUSD = 0V -0.8V 75 Out 75 75 - + 75 impedance -0.8V / -1.6V Differential output : 0.8V = 1.6V Common mode level : -1.2V (-1.2V below VPLUSD level) OutB -1.6V / -0.8V 11 mA DVEE Figure 5 : DIFFERENTIAL OUTPUT : OPEN LOADED Preliminary Specification -site 33 Preliminary Specification -site DIFFERENTIAL OUTPUT LOADING CONFIGURATIONS (LEVELS FOR LVDS COMPATIBILITY) VPLUSD = 2.4V 1.6V 75 Out 75 75 Differential output : 0.41V = 0.825V 75 - 75 impedance + 10 nF 1.4V / 0.99V Common mode level : -1.2V (-1.2V below VPLUSD level) 75 OutB 0.99V / 1.4V 11 mA Figure 6 : DIFFERENTIAL OUTPUT : 75 TERMINATED DVEE VPLUSD = 2.4V 1.6V 75 Out 75 50 Differential output : 0.33V = 0.660V 50 - 50 impedance + 10 nF 1.38V / 1.05V Common mode level : -1.2V (-1.2V below VPLUSD level) 50 OutB 1.05V / 1.38V 11 mA Figure 7 : DIFFERENTIAL OUTPUT : 50 TERMINATED DVEE VPLUSD = 2.4V 1.6V 75 Out 75 75 - 75 impedance + 1.6V / 0.8V Differential output : 0.8V = 1.6V Common mode level : -1.2V (-1.2V below VPLUSD level) OutB 0.8V / 1.6V 11 mA DVEE 34 Figure 8 : DIFFERENTIAL OUTPUT : OPEN LOADED TS8308500 TS8308500 7.7. OUT OF RANGE BIT An Out of Range (OR,ORB) bit is provided that goes to logical high state when the input exceeds the positive full scale or falls below the negative full scale. When the analog input exceeds the positive full scale, the digital output data remain at high logical state, with (OR,ORB) at logical one. When the analog input falls below the negative full scale, the digital outputs remain at logical low state, with (OR,ORB) at logical one again. 7.8. GRAY OR BINARY OUTPUT DATA FORMAT SELECT The TS8308500 internal regeneration latches indecision (for inputs very close to latches threshold) may produce errors in the logic encoding circuitry and leading to large amplitude output errors. This is due to the fact that the latches are regenerating the internal analog residues into logical states with a finite voltage gain value (Av) within a given positive amount of time (t) : Av= exp((t)/) , with the positive feedback regeneration time constant. The TS8308500 has been designed for reducing the probability of occurrence of such errors to approximately 10-13 (targeted for the TS8308500 at 500 MSPS). A standard technique for reducing the amplitude of such errors down to +/-1 LSB consists to output the digital data in Gray code format. Though the TS8308500 has been designed for featuring a Bit Error Rate of 10-13 with a binary output format, it is possible for the user to select between the Binary or Gray output data format, in order to reduce the amplitude of such errors when occurring, by storing Gray output codes. Digital Data format selection : BINARY output format if GORB is floating or VCC. GRAY output format if GORB is connected to ground (0V). 7.9. DIODE PIN K1 One single pin is used for both DRRB input command and die junction monitoring. The pin denomination is DRRB/DIOD. Temperature monitoring and Data Ready control by DRRB is not possible simultaneously. (See section 7.2 for Data Ready Reset input command). The operating die junction temperature must be kept below145C, therefore an adequate cooling system has to be set up. The diode mounted transistor measured Vbe value versus junction temperature is given below. 1000 960 920 VBE (mV) 880 840 800 760 720 680 640 600 -55 -35 -15 5 25 45 65 85 105 125 Junction temperature (deg.C) Preliminary Specification -site 35 Preliminary Specification -site 7.10. ADC GAIN CONTROL PIN K6 The ADC gain is adjustable by the means of the pin K6 (input impedance is 1M in parallel with 2pF) The gain adjust transfer function is given below : 1,20 1,15 ADC Gain 1,10 1,05 1,00 0,95 0,90 0,85 0,80 -500 -400 -300 -200 -100 0 100 Vgain (command voltage) (mV) 36 TS8308500 200 300 400 500 TS8308500 8. 8.1. EQUIVALENT INPUT / OUTPUT SCHEMATICS EQUIVALENT ANALOG INPUT CIRCUIT AND ESD PROTECTIONS VCC VCC=+5V -0.8V VCLAMP= +2.4V -0.8V GND=0V -5.8V GND -5.8V +1.65V 50 VEE 50 E21V E21V 200 VEE 200 VIN VINB Pad capacitance 340fF Pad capacitance 340fF 5.8V -1.55V 0.8V VEE=-5V Note : the ESD protection equivalent capacitance is 150 fF. 8.2. EQUIVALENT ANALOG CLOCK INPUT CIRCUIT AND ESD PROTECTIONS VCC=+5V VCC +0.8V -5.8V -5.8V -5.8V -5.8V GND=0V -5.8V -5.8V VEE CLK VEE 150 Pad capacitance 340fF 150 5.8V 5.8V 380 A CLKB Pad capacitance 340fF 380 A 0.8V 0.8V VEE=-5V Note : the ESD protection equivalent capacitance is 150 fF. Preliminary Specification -site 37 Preliminary Specification -site 8.3. EQUIVALENT DATA OUTPUT BUFFER CIRCUIT AND ESD PROTECTIONS VPLUSD=0V to 2.4V -5.8V -5.8V 75 75 VEE VEE OUTB OUT Pad capacitance 180 fF 5.8V Pad capacitance 180 fF 5.8V I=11mA -3.7V 0.8V 0.8V 0.8V 0.8V DVEE=-5V VEE=-5V VEE=-5V Note : the ESD protection equivalent capacitance is 150 fF. 8.4. ADC GAIN ADJUST EQUIVALENT INPUT CIRCUITS AND ESD PROTECTIONS VCC=+5V VCC -0.8 V NP1032C2 -0.8 V +1.6V VEE NP1032C2 -5.8 V -5.8 V 1 k VEE 1 k GA GAB 0.8V Pad capacitance 180 fF 2 pF 2 pF 0.8V VEE GND 500 A 500 A VEE=-5V Note : the ESD protection equivalent capacitance is 150 fF. 38 TS8308500 Pad capacitance 180 fF 0.8V GND 5.8V 0.8V 5.8V VEE TS8308500 8.5. GORB EQUIVALENT INPUT SCHEMATIC AND ESD PROTECTIONS GORB: gray or binary select input; floating or tied to VCC -> binary VCC=+5V -0.8V 1 k 1 k -0.8V 1 k -5.8V VEE GORB 5 k Pad capacitance 180fF 5.8V 5.8V 250 A 250 A 5.8V VEE=-5V GND=0V Note : the ESD protection equivalent capacitance is 150 fF. 8.6. DRRB EQUIVALENT INPUT SCHEMATIC AND ESD PROTECTIONS VCC=+5V Actual protection range: 6.6V above VEE, In fact stress above GND are clipped by the CB diode used for Tj monitoring GND=0V NP1032C2 10 k DRRB -1.3V 200 Pad capacitance 180 fF -2.6V 5.8 V VEE 0.8 V VEE=-5V Note : the ESD protection equivalent capacitance is 150 fF. Preliminary Specification -site 39 Preliminary Specification -site 9. TSEV8308500G : DEVICE EVALUATION BOARD For complete specification, see separate TSEV8308500 document. GENERAL DESCRIPTION The TSEV8308500 Evaluation Board (CEB) is a board which has been designed in order to facilitate the evaluation and the characterization of the TS8308500 device up to its 1.3 GHz full power bandwidth at up to 500 Msps in the commercial temperature range. The high speed of the TS8308500 requires careful attention to circuit design and layout to achieve optimal performance. This four metal layer board with internal ground plane has the adequate functions in order to allow a quick and simple evaluation of the TS8308500 ADC performances over the temperature range. The TSEV8308500 Evaluation Board is very straightforward as it only implements the TS8308500 ADC, SMA connectors for input / output accesses and a 2.54 mm pitch connector compatible with HP16500C high frequency probes. The board also implements a de-embedding fixture in order to facilitate the evaluation of the high frequency insertion loss of the input microstrip lines, and a die junction temperature measurement setting. The board is constituted by a sandwich of two dielectric layers, featuring low insertion loss and enhanced thermal characteristics for operation in the high frequency domain and extended temperature range. The board dimensions are 130 mm x 130 mm. The board set comes fully assembled and tested, with the TS8308500 and its heatsink installed. 40 TS8308500 TS8308500 10. ORDERING INFORMATION 10.1. PACKAGE DEVICE TS 8308500 C G Screening level : Manufacturer prefix ___ : standard Device or family Temperature range : Package : C : 0 < Tc ; Tj < 90C G : CBGA72 with C and R 10.2. EVALUATION BOARD TSEV 8308500 G ZA2 * ZA2 : with MC100EL16 digital receivers * ---- : No digital receiver Evaluation board prefix G : CBGA72 with C and R The evaluation board is delivered with an ADC and includes the heat sink. Preliminary Specification -site 41 Preliminary Specification -site Atmel Headquarters Atmel Operations Corporate Headquarters Atmel Colorado Springs 2325 Orchard Parkway San Jose, CA 95131 TEL (408) 441-0311 FAX (408) 487-2600 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TEL (719) 576-3300 FAX (719) 540-1759 Europe Atmel Rousset Atmel SarL Route des Arsenaux 41 Casa Postale 80 CH-1705 Fribourg Switzerland TEL (41) 26-426-5555 FAX (41) 26-426-5500 Zone Industrielle 13106 Rousset Cedex France TEL (33) 4-4253-6000 FAX (33) 4-4253-6001 Asia Atmel Asia, Ltd. Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimhatsui East Kowloon Hong Kong TEL (852) 2721-9778 FAX (852) 2722-1369 Japan Atmel Smart Card ICs Scottish Enterprise Technology Park East Kilbride, Scotland G75 0QR TEL (44) 1355-357-000 FAX (44) 1355-242-743 Atmel Grenoble Avenue de Rochepleine BP 123 38521 Saint-Egreve Cedex France TEL (33) 4-7658-3000 FAX (33) 4-7658-3480 Atmel Japan K.K. 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan TEL (81) 3-3523-3551 FAX (81) 3-3523-7581 Fax-on-Demand e-mail North America: 1-(800) 292-8635 International: 1-(408) 441-0732 literature@atmel.com Web Site http://www.atmel.com BBS 1-(408) 436-4309 (c) Atmel Corporation 2001. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life support devices or systems. Marks bearing (R) and/or TM are registered trademarks and trademarks of Atmel Corporation. Terms and product names in this document may be trademarks of others. This product is manufactured and commercialized by Atmel Grenoble. For further information, please contact : Atmel Grenoble - Route Departementale 128 - BP 46 - 91901 Orsay Cedex - France Phone +33 (0) 1 69 33 03 24 - Fax +33 (0) 1 69 33 03 21 Email monique.lafrique@gfo.atmel.com - Web site http://www.atmel-grenoble.com For further technical information, please contact the technical support : Email HOTLINE-BDC@gfo.atmel.com 42 TS8308500