W24L257 32K x 8 CMOS STATIC RAM GENERAL DESCRIPTION The W24L257 is a normal-speed, very low-power CMOS static RAM organized as 32768 x 8 bits that operates on a wide voltage range from 3V to 5.5V power supply. This device is manufactured using Winbond's high performance CMOS technology. FEATURES * Low power consumption: Access time: 70 nS * 3.3V/5V power supply * Fully static operation * All inputs and outputs directly TTL compatible * * * PIN CONFIGURATIONS BLOCK DIAGRAM Three-state outputs Battery back-up operation capability * Data retention voltage: 2V (min.) * Packaged in 330 mil SOP, and standard type one STSOP (8 mm x 13.4 mm) CLK GEN. PRECHARGE CKT. R O W CORE CELL ARRAY A12 A14 1 28 VDD A12 2 27 #WE A7 3 26 A13 A6 4 25 A8 A5 5 24 A9 A4 6 23 A11 A3 7 22 #OE A2 8 21 A10 A1 9 20 CS A0 10 19 I/O8 I/O1 11 18 I/O7 I/O2 12 17 I/O6 I/O3 13 16 I/O5 VSS 14 15 I/O4 A14 A2 A3 A4 A5 A6 D E C O D E R 512 ROWS 32 X 8 COLUMNS A7 A13 I/O1 : I/O8 DATA CNTRL . CLK GEN. I/O CKT. COLUMN DECODER A11 A10 A1 A0 A8 A9 #WE #CS #OE PIN DESCRIPTION #OE A11 A9 A8 A13 #W EDD V A14 A12 A7 A6 A5 A4 A3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28-pin TSOP 28 27 26 25 24 23 22 21 20 19 18 17 16 15 SYMBOL A0 - A14 I/O1 - I/O8 #CS #WE #OE VDD VSS NC A10 #CS I/O8 I/O7 I/O6 I/O5 I/O4 VSS I/O3 I/O2 I/O1 A0 A1 A2 -1- DESCRIPTION Address Inputs Data Inputs/Outputs Chip Select Input Write Enable Input Output Enable Input Power Supply Ground No Connection Publication Release Date: October 3, 2001 Revision A5 W24L257 TRUTH TABLE #CS H #OE X #WE X L H L L VDD CURRENT ISB, ISB1 MODE Not Selected I/O1-I/O8 High Z H Output Disable High Z IDD L H Read Data Out IDD X L Write Data In IDD DC CHARACTERISTICS Absolute Maximum Ratings PARAMETER UNIT RATING Supply Voltage to VSS Potential 3.3V 5V -0.5 to +4.6 -0.5 to +7.0 V Input/Output to VSS Potential -0.5 to VDD +0.5 V Allowable Power Dissipation 1.0 W -65 to +150 C L/LL 0 to 70 C LE LI -20 to 85 -40 to 85 Storage Temperature Operating Temperature Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. Operating Characteristics (VDD = 5V 10%; VDD = 3.3V 5%; VSS = 0V; TA (C) = 0 to 70 for L/LL, -20 to 85 for LE, -40 to 85 for LI) PARAMETER SYM. TEST CONDITIONS 3.3V MIN. MAX. 5V MIN. MAX. Input Low Voltage VIL - -0.5 +0.6 -0.5 Input High Voltage VIH - +2.0 VDD +0.5 Input Leakage Current ILI VIN = VSS to VDD -1 +1 -2 +2 A Output Leakage Current ILO VI/O = VSS to VDD, #CS = VIH (Min.) or #OE = VIH (Min.) or #CS = VIL (Max.) -1 +1 -2 +2 A Output Low Voltage VOL IOL = +2.1 mA - 0.4 - 0.4 V Output High Voltage VOH IOH = -1.0 mA 2.2 - 2.4 - V - 35 - 70 mA Operating Power Supply Current IDD #CS = VIL (Max.) and I/O = 0 mA, Cycle = Min. Duty = 100% -2- +0.8 +2.2 VDD +0.5 UNIT V V W24L257 Operating Characteristics, continued PARAMETER SYM. TEST CONDITIONS 3.3V 5V UNIT MIN. MAX. MIN. MAX. ISB #CS = VIH (min.) or Cycle = min. Duty = 100% - 1 - 3 mA ISB1 #CS VDD -0.2V LL/LE/LI - 15 - 15 A L - 30 - 30 Standby Power Supply Current Note: Typical parameter is measured under ambient temperature TA = 25 C and VDD = 3.3V/5V CAPACITANCE (VDD = 5V 10%; VDD = 3V 5%, TA = 25 C, f = 1 MHz) PARAMETER SYM. CONDITIONS MAX. UNIT Input Capacitance CIN VIN = 0V 6 pF Input/Output Capacitance CI/O VOUT = 0V 8 pF Note: These parameters are sampled but not 100% tested. AC Characteristics AC Test Conditions PARAMETER CONDITIONS Input Pulse Levels 0V to 3.0V Input Rise and Fall Times 5 nS Input and Output Timing Reference Level 1.5V Output Load See the drawing below AC Test Loads and Waveform 1 TTL 1 TTL OUTPUT OUTPUT 5 pF Including Jig and Scope 100 pF Including Jig and Scope (For TCLZ, TOLZ, TCHZ, TOHZ, TWHZ, TOW ) 3.0 V 90% 10% 0V 90% 10% 5 nS 5 nS -3- Publication Release Date: October 3, 2001 Revision A5 W24L257 AC Characteristics, continued Read Cycle (VDD = 5V 10%; VDD = 3V 5%; VSS = 0V; TA (C) = 0 to 70 for L/LL, -20 to 85 for LE, -40 to 85 for LI) PARAMETER SYMBOL 3.3V/5V UNIT MIN. MAX. Read Cycle Time TRC 70 - nS Address Access Time TAA - 70 nS Chip Select Access Time TACS - 70 nS Output Enable to Output Valid TAOE - 35 nS Chip Selection to Output in Low Z TCLZ* 10 - nS Output Enable to Output in Low Z TOLZ* 5 - nS Chip Deselection to Output in High Z TCHZ* - 30 nS Output Disable to Output in High Z TOHZ* - 30 nS Output Hold from Address Change TOH 10 - nS These parameters are sampled but not 100% tested Write Cycle PARAMETER SYMBOL 3.3V/5V UNIT MIN. MAX. Write Cycle Time TWC 70 - nS Chip Selection to End of Write TCW 55 - nS Address Valid to End of Write TAW 55 - nS Address Setup Time TAS 0 - nS Write Pulse Width TWP 40 - nS TWR 0 - nS Data Valid to End of Write TDW 35 - nS Data Hold from End of Write TDH 0 - nS Write to Output in High Z TWHZ* - 25 nS Output Disable to Output in High Z TOHZ* - 25 nS Output Active from End of Write TOW 5 - nS Write Recovery Time #CS, #WE These parameters are sampled but not 100% tested -4- W24L257 TIMING WAVEFORMS Read Cycle 1 (Address Controlled) TRC Address TOH TAA TOH DOUT Read Cycle 2 (Chip Select Controlled) #CS1 TACS TCHZ TCLZ DOUT Read Cycle 3 (Output Enable Controlled) T RC Address TAA #OE TAOE TOH TOLZ #CS TACS DOUT T CHZ TOHZ TCLZ -5- Publication Release Date: October 3, 2001 Revision A5 W24L257 Timing Waveforms, continued Write Cycle 1 TWC Address TWR #OE TCW #CS TAW #WE TWP TAS TOHZ (1, 4) D OUT TDW TDH DIN Write Cycle 2 (#OE = VIL Fixed) T WC Address TWR TCW #CS TAW #WE TOH TWP TAS TWHZ (1, 4) D OUT TDW (2) (3) TOW TDH DIN Notes: 1. During this period, I/O pins are in the output state, so input signals of opposite phase to the outputs should not be applied. 2. The data output from DOUT are the same as the data written to DIN during the write cycle. 3. DOUT provides the read data for the next address. 4. Transition is measured 500 mV from steady state with CL = 5 pF. This parameter is guaranteed but not 100% tested. -6- W24L257 DATA RETENTION CHARACTERISTICS (TA (C) = 0 to 70 for L/LL, -20 to 85 for LE, -40 to 85 for LI) PARAMETER SYM. TEST CONDITIONS VDD for Data Retention VDR #CS VDD -0.2V Data Retention Current IDDDR #CS VDD -0.2V, VDD = 3V Chip Deselect to Data Retention Time TCDR Operation Recovery Time TR MIN. TYP. MAX. UNIT 2.0 - - V LL/LE/LI - - 15 A L - - 30 A 0 - - nS TRC* - - nS See data retention waveform * Read Cycle Time DATA RETENTION WAVEFORM VDD 0.9 VDD > 2V V DR = TCDR #CS 0.9 VDD TR #CS > = VDD - 0.2V -7- Publication Release Date: October 3, 2001 Revision A5 W24L257 ORDERING INFORMATION ACCESS TIME OPERATING VOLTAGE OPERATING TEMPERATURE STANDBY CURRENT MAX. (nS) (V) (C) (A) W24L257S70L 70 3.3V/5V 0 to 70 30 330 mil SOP W24L257S70LL 70 3.3V/5V 0 to 70 15 330 mil SOP W24L257S70LE 70 3.3V/5V -20 to 85 15 330 mil SOP W24L257S70LI 70 3.3V/5V -40 to 85 15 330 mil SOP W24L257Q70L 70 3.3V/5V 0 to 70 30 Small TSOP W24L257Q70LL 70 3.3V/5V 0 to 70 15 Small TSOP W24L257Q70LE 70 3.3V/5V -20 to 85 15 Small TSOP W24L257Q70LI 70 3.3V/5V -40 to 85 15 Small TSOP PART NO. PACKAGE Notes: 1. Winbond reserves the right to make changes to its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure. -8- W24L257 BONDING PAD DIAGRAM 6 A4 5 A5 4 3 A6 A7 A12 A14 VDD VDD WEB A13 2 1 30 29 28 27 26 25 PAD NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 24 A8 A9 A11 AC5394 23 7 A3 OEB Y X 8 22 A2 A10 9 A1 10 11 12 13 14 A0 I/O0 I/O1 I/O2 VSS 15 16 17 18 19 20 21 VSS I/O3 I/O4 I/O5 I/O6 I/O7 CSB X -232.25 -351.70 -471.15 -590.60 -710.05 -829.50 -992.79 -992.79 -857.86 -738.41 -594.84 -451.06 -310.67 -171.78 24.45 151.80 298.07 443.28 588.20 732.84 871.11 992.75 992.75 810.09 690.64 571.19 451.74 332.29 120.25 -93.23 Y 1445.22 1445.22 1445.22 1445.22 1445.22 1445.22 1362.24 -1306.11 -1452.79 -1452.79 -1414.13 -1414.13 -1414.13 -1405.28 -1405.28 -1414.13 -1414.13 -1414.13 -1414.13 -1414.13 -1452.79 -1312.15 1373.67 1445.22 1445.22 1445.22 1445.22 1445.22 1444.65 1444.65 Note: For bare chip form (C.O.B.) applications, the substrate must be connected to VDD or left floating in the PCB layout. -9- Publication Release Date: October 3, 2001 Revision A5 W24L257 PACKAGE DIMENSIONS 28-pin SOP Symbol 28 A A1 A2 b c D E e HE L LE S y 15 e1 E HE L Detail F 14 1 b Dimension in Inches Dimension in mm Min. Nom. Max. Min. Nom. Max. 2.85 0.112 0.004 0.10 0.093 0.098 0.103 2.36 2.49 0.014 0.016 0.020 0.36 0.41 0.51 0.008 0.010 0.014 0.20 0.25 0.36 18.11 18.62 2.62 0.713 0.733 0.326 0.331 0.336 8.28 8.41 8.53 0.044 0.050 0.056 1.12 1.27 1.42 0.453 0.465 0.477 11.51 11.81 12.12 0.028 0.036 0.044 0.71 0.91 1.12 0.059 0.067 0.075 1.50 1.70 1.91 0.047 1.19 0.10 0.004 10 0 10 0 Notes: 1. Dimension D Max. & S include mold flash or tie bar burrs. 2. Dimension b does not include dambar protrusion/intrusion. 3. Dimension D & E include mold mismatch . and determined at the mold parting line. 4. Controlling dimension: Inches. 5. General appearance spec should be based on final visual inspection spec. e1 D c A2 A S e y LE A1 See Detail F Seating Plane 28-pin Standard Type One TSOP HD Dimension In Inches Dimension In mm Symbol D Min. c A A1 A2 b c D E HD e L L1 Y 1 e E b A2 A A1 L L1 - 10 - Nom. Max. Min. 0.006 0.002 Max. 1.20 0.05 0.15 0.035 0.040 0.041 0.95 1.00 0.007 0.008 0.011 0.17 0.20 0.27 0.004 0.006 0.008 0.10 0.15 0.21 11.90 1.05 0.461 0.465 0.469 11.70 11.80 0.311 0.315 0.319 7.90 8.00 8.10 0.520 0.528 0.536 13.20 13.40 13.60 0.020 0.024 0.028 0.50 0.60 0.022 0.55 0.010 0.000 0 3 0.70 0.25 0.004 0.00 5 0 Controlling dimension: Millimeters Y Nom. 0.047 0.10 3 5 W24L257 VERSION HISTORY VERSION DATE PAGE A1 May 2000 - A2 Nov. 2000 1, 2, 3, 4, 7 1, 9 2, 3, 7, 8 DESCRIPTION Initial Issued Add in 5V specification Modify package as 330 mil SOP and standard type one TSOP (8 mm x 13.4 mm) Add in LE, LI specification Modify the 3.3V 10%, to 3.3V 5% A3 Dec. 2000 2, 4, 5 A4 Jun. 2001 8 Correct Ordering Information SOP description 8 Correct Standby Current 4 Correct Write Recover Time (TWR) parameter A5 Oct. 3, 2001 Headquarters Winbond Electronics (H.K.) Ltd. Unit 9-15, 22F, Millennium City, No. 4, Creation Rd. III, No. 378 Kwun Tong Rd; Science-Based Industrial Park, Kowloon, Hong Kong Hsinchu, Taiwan TEL: 852-27513100 TEL: 886-3-5770066 FAX: 852-27552064 FAX: 886-3-5796096 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886-2-27197006 Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab. 2727 N. First Street, San Jose, CA 95134, U.S.A. TEL: 408-9436666 FAX: 408-5441798 Taipei Office 11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-27190505 FAX: 886-2-27197502 Note: All data and specifications are subject to change without notice. - 11 - Publication Release Date: October 3, 2001 Revision A5