Integrated Communications Processors MPC860 PowerQUICCTM Family Freescale Semiconductor's PowerQUICCTM MPC860 Block Diagram MPC860 family is designed to deliver a versatile, on-chip integrated processor and peripheral combination that can be used in 4 KB or 16 KB I-Cache a variety of controller applications--excelling Instruction Bus particularly in communications and networking the MPC850 family, the MPC860 family processing blocks: the embedded 8xx core compatible with the Power ArchitectureTM technology instruction-set architecture (ISA), and the communications processor module System Functions 4 KB or 8 KB D-Cache Real-Time Clock to provide higher performance in all areas The MPC860 architecture integrates two Bus Interface Unit Unified Bus and MPC855T derivative are engineered extensions in capability and integration. Memory Controller I-MMU Embedded 8xx Core products. Providing functionality beyond of device operation including flexibility, System Interface Unit Load/Store Bus D-MMU PCMCIA Interface Fast Ethernet Controller DMAs Four Timers Parallel I/O FIFOs Baud Rate Generators 10/100 Base-T Media Access Control Parallel Port Pins Interrupt Control Dual-Port RAM Virtual IDMA and 16 Serial DMA 32-bit Controller and Program ROM Timer MII (CPM). The CPM is a dedicated RISC-based communications engine designed to support SCC1 four serial communications controllers (SCCs), SCC2 providing a total of eight serial channels: four SCC3 SCC4 Time Slot Assigner SMC1 SMC2 SPI I 2C Serial Interface SCCs, two serial management controllers (SMCs), one serial peripheral interface (SPI) and one I2C interface. This dual-processor architecture is designed to provide superior performance over traditional architectures because the CPM offloads communications Key Features intensive processing from the embedded 8xx * Power Architecture Technology core. This partitioning frees up the 8xx core to perform other system functions. Embedded 8xx core *4 KB instruction cache and 4 KB data cache (16 KB instruction cache and 8 KB data cache available) in MPC860P and MPC860DP *Powerful memory controller and system functions *Efficient architecture that involves a separate RISC processor (CPM) for handling communications *Up to four serial communications controllers (SCC) *Support for Ethernet, Fast Ethernet, HDLC, asynchronous transfer mode (ATM) and more *Two SMCs, one SPI and one I2C *Additional support features, including timers, baud rate generators, etc. *8K dual-port RAM *Available at 50, 66 and 80 MHz in a 357-pin RoHS compliant PBGA package *Strong third-party tool support through Freescale's Design Alliance Program MPC 860 EN 800 Series Device Number (850, 860, etc.) Product Code KMPC Sample Pack (2 units) MPC Fully Qualified C VR 66 Temp. Range None=0C Ta to +95C Tj C=-40C Ta to +95C Tj Part/Module Modifier DE Dual Channel (Ethernet) DT Dual Channel (10/100, Multi-HDLC, ATM) DP Dual Channel (16K I-Cache and 8K D-Cache, 10/100, Multi-HDLC, ATM) EN Four Channel (Ethernet) SR Four Channel (Ethernet, Multi-HDLC, ATM) T Four Channel (10/100, Multi-HDLC, ATM) P Four Channel (16K I-Cache and 8K D-Cache, 10/100, Multi-HDLC, ATM) D Frequency MHz Die Mask Revision Package VR=RoHS compliant (Pb-free) 357 PBGA ZQ=357 PBGA 855T 860DE 860DT 860DP 860EN 860SR 860T 860P Serial Communications Controllers (SCCs) 1 2 2 2 4 4 4 4 I-Cache (KB) 4 4 4 16 4 4 4 16 D-Cache (KB) 4 4 4 8 4 4 4 8 Ethernet (10T) 1 2 2 2 4 4 4 4 Ethernet (10/100) 1 - 1 1 - - 1 1 Yes - Yes Yes - Yes Yes Yes Up to 32 - Up to 64 Up to 64 - Up to 64 Up to 64 Up to 64 ATM Multi-channel HDLC Technical Specifications *Embedded 8xx core designed to provide 106 MIPS (using Dhrystone 2.1) at 80 MHz Single-issue, 32-bit version of the *Communications processor module Protocols supported 8 KB dual-port RAM ** Ethernet IEEE(R) 802.3 and Fast Ethernet Up to four serial communications ** ATM ** HDLC controllers (SCCs) embedded 8xx core with 32- x 32-bit 32-bit scaler RISC controller ** Asynchronous HDLC fixed point registers Two serial management controllers ** Channelized HDLC 16 serial DMA (SDMA) channels ** Multi-channel HDLC cache (16 KB instruction cache and 8 KB One I2C port ** Appletalk(R) data cache available in 860P and 860DP) One serial peripheral interface ** UART Four general-purpose timers ** IrDA TLBs and fully associative instruction and Time slot assigner ** Basic rate ISDN (BRI) data TLBs Interrupts ** Primary rate ISDN (PRI) Four baud rate generators ** Totally transparent mode with/ 4 KB instruction cache and 4 KB data Memory management units with 32-entry *Advanced on-chip emulation debug mode without CRC *Data bus dynamic bus sizing for 8-, 16- and *System integration unit 32-bit buses Memory controller Real-time clock PCMCIA interface System functions Bus interface unit Learn More: FreescaleTM and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. The Power Architecture and Power.org word marks and the Power and Power.org logos and related marks are trademarks and service marks licensed by Power.org. (c) Freescale Semiconductor, Inc. 2007 Document Number: MPC860FACT REV 10 For current information about Freescale products and documentation, please visit www.freescale.com.