Freescale Semiconductor’s PowerQUICC™
MPC860 family is designed to deliver a
versatile, on-chip integrated processor and
peripheral combination that can be used in
a variety of controller applications—excelling
particularly in communications and networking
products. Providing functionality beyond
the MPC850 family, the MPC860 family
and MPC855T derivative are engineered
to provide higher performance in all areas
of device operation including flexibility,
extensions in capability and integration.
The MPC860 architecture integrates two
processing blocks: the embedded 8xx core
compatible with the Power Architecture™
technology instruction-set architecture (ISA),
and the communications processor module
(CPM). The CPM is a dedicated RISC-based
communications engine designed to support
four serial communications controllers (SCCs),
providing a total of eight serial channels: four
SCCs, two serial management controllers
(SMCs), one serial peripheral interface (SPI)
and one I2C interface. This dual-processor
architecture is designed to provide superior
performance over traditional architectures
because the CPM offloads communications
intensive processing from the embedded 8xx
core. This partitioning frees up the 8xx core to
perform other system functions.
Key Features
• Power Architecture Technology
Embedded 8xx core
• 4 KB instruction cache and 4 KB data
cache (16 KB instruction cache and
8 KB data cache available) in MPC860P
and MPC860DP
• Powerful memory controller and
system functions
• Efficient architecture that involves
a separate RISC processor (CPM) for
handling communications
• Up to four serial communications
controllers (SCC)
• Support for Ethernet, Fast Ethernet,
HDLC, asynchronous transfer mode (ATM)
and more
• Two SMCs, one SPI and one I2C
• Additional support features, including
timers, baud rate generators, etc.
• 8K dual-port RAM
• Available at 50, 66 and 80 MHz in a
357-pin RoHS compliant PBGA package
• Strong third-party tool support through
Freescale’s Design Alliance Program
Integrated Communications Processors
MPC860 PowerQUICC™ Family
MPC860 Block Diagram
DMAs
MII
FIFOs
10/100 Base-T
Media Access
Control
Embedded
8xx
Core
I-MMU
4 KB or 8 KB
D-Cache
D-MMU
System Interface Unit
Memory Controller
Real-Time Clock
System Functions
PCMCIA Interface
Bus Interface Unit
Parallel I/O Four
Timers
Interrupt
Control
Dual-Port
RAM
Baud Rate
Generators
Parallel
Port Pins
32-bit Controller
and Program ROM
Timer
Virtual IDMA
and
16 Serial DMA
Time Slot Assigner
SCC1
Unified Bus
Instruction
Bus
SCC2 SCC3 SCC4
SMC1
SMC2 SPI I
2
C
Fast Ethernet
Controller
4 KB or 16 KB
I-Cache
Load/Store
Bus
Serial Interface