STFU16N65M2 N-channel 650 V, 0.32 typ., 11 A MDmeshTM M2 Power MOSFET in a TO-220FP ultra narrow leads package Datasheet - production data Features 1 2 3 Order code VDS RDS(on) max ID STFU16N65M2 650 V 0.36 11 A Extremely low gate charge Excellent output capacitance (COSS) profile 100% avalanche tested Zener-protected Applications TO-220FP ultra narrow leads Figure 1: Internal schematic diagram D(2) Switching applications Description This device is an N-channel Power MOSFET developed using MDmeshTM M2 technology. Thanks to its strip layout and an improved vertical structure, the device exhibits low on-resistance and optimized switching characteristics, rendering it suitable for the most demanding high efficiency converters. G(1) S(3) AM15572v1_no_tab Table 1: Device summary Order code Marking Package Packaging STFU16N65M2 16N65M2 TO-220FP ultra narrow leads Tube April 2017 DocID030485 Rev 1 This is information on a product in full production. 1/12 www.st.com Contents STFU16N65M2 Contents 1 Electrical ratings ............................................................................. 3 2 Electrical characteristics ................................................................ 4 2.1 Electrical characteristics (curves) ...................................................... 6 3 Test circuits ..................................................................................... 8 4 Package mechanical data ............................................................... 9 4.1 5 2/12 TO-220FP ultra narrow leads package information ........................... 9 Revision history ............................................................................ 11 DocID030485 Rev 1 STFU16N65M2 1 Electrical ratings Electrical ratings Table 2: Absolute maximum ratings Symbol Parameter VGS ID Value Unit Gate-source voltage 25 V Drain current (continuous) at TC = 25 C 11(1) A A Drain current (continuous) at TC = 100 C 6.9(1) IDM(2) Drain current (pulsed) 44(1) A PTOT Total dissipation at TC = 25 C 25 W VISO Insulation withstand voltage (RMS) from all three leads to external heat sink (t = 1 s; TC = 25 C) 2500 V ID dv/dt (3) Peak diode recovery voltage slope 15 dv/dt (4) MOSFET dv/dt ruggedness 50 Tstg Storage temperature range Tj V/ns -55 to 150 Operating junction temperature range C Notes: (1)Limited (2)Pulse (3)I SD (4)V by maximum junction temperature.. width limited by safe operating area. 11 A, di/dt 400 A/s; VDSpeak < V(BR)DSS, VDD=400 V DS 520 V Table 3: Thermal data Symbol Parameter Rthj-case Thermal resistance junction-case Rthj-amb Thermal resistance junction-ambient Value Unit 5 C/W 62.5 C/W Table 4: Avalanche characteristics Symbol Parameter Value Unit IAR Avalanche current, repetitive or not repetitive (pulse width limited by T jmax) 1.9 A EAS Single pulse avalanche energy (starting Tj = 25C, ID = IAR; VDD = 50 V) 360 mJ DocID030485 Rev 1 3/12 Electrical characteristics 2 STFU16N65M2 Electrical characteristics (TC = 25 C unless otherwise specified) Table 5: On /off states Symbol Parameter Test conditions Drain-source breakdown voltage V(BR)DSS ID = 1 mA, VGS = 0 V Min. Typ. Max. 650 Unit V VGS = 0 V, VDS = 650 V 1 A VGS = 0 V, VDS = 650 V, TC = 125 C(1) 100 A Gate-body leakage current VDS = 0 V, VGS = 25 V 10 A VGS(th) Gate threshold voltage VDS = VGS, ID = 250 A 3 4 V RDS(on) Static drain-source on-resistance VGS = 10 V, ID = 5.5 A 0.32 0.36 Min. Typ. Max. Unit - 718 - pF - 32 - pF - 1.1 - pF IDSS Zero gate voltage drain current IGSS 2 Notes: (1)Defined by design, not subject to production test. Table 6: Dynamic Symbol Parameter Test conditions Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Coss eq.(1) Equivalent output capacitance VDS = 0 to 520 V, VGS = 0 V - 189 - pF RG Intrinsic gate resistance f = 1 MHz open drain - 5.2 - Qg Total gate charge - 19.5 - nC Qgs Gate-source charge - 4 - nC Qgd Gate-drain charge VDD = 520 V, ID = 11 A, VGS = 0 to 10 V (see Figure 15: "Test circuit for gate charge behavior" - 8.3 - nC VDS = 100 V, f = 1 MHz, VGS = 0 V Notes: (1)C oss eq. is defined as a constant equivalent capacitance giving the same charging time as C oss when VDS increases from 0 to 80% VDSS Table 7: Switching times Symbol td(on) tr td(off) tf 4/12 Parameter Turn-on delay time Rise time Turn-off delay time Fall time Test conditions Min. Typ. Max. Unit VDD = 325 V, ID = 5.5 A, RG = 4.7 , VGS = 10 V (see Figure 14: "Test circuit for resistive load switching times" and Figure 19: "Switching time waveform") - 11.3 - ns - 8.2 - ns - 36 - ns - 11.3 - ns DocID030485 Rev 1 STFU16N65M2 Electrical characteristics Table 8: Source drain diode Symbol Parameter Test conditions Min. Typ. Max. Unit ISD Source-drain current - 11 A ISDM(1) Source-drain current (pulsed) - 44 A VSD(2) Forward on voltage ISD = 11 A, VGS = 0 V - 1.6 V trr Reverse recovery time - 342 ns Qrr Reverse recovery charge - 3.5 C IRRM Reverse recovery current ISD = 11 A, di/dt = 100 A/s, VDD = 60 V (see Figure 16: "Test circuit for inductive load switching and diode recovery times") - 20.4 A ISD = 11 A, di/dt = 100 A/s, VDD = 60 V, Tj = 150 C (see Figure 16: "Test circuit for inductive load switching and diode recovery times") - 458 ns - 4.6 C - 20.5 A trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current Notes: (1)Pulse (2) width limited by safe operating area. Pulsed: pulse duration = 300 s, duty cycle 1.5% DocID030485 Rev 1 5/12 Electrical characteristics 2.1 STFU16N65M2 Electrical characteristics (curves) Figure 2: Safe operating area Figure 3: Thermal impedance Figure 4: Output characteristics Figure 5: Transfer characteristics GIPD221020141412FSR ID (A) VGS= 7, 8, 9, 10 V 24 24 6V 20 20 16 16 5V 12 VDS = 18 V 12 8 8 4 0 0 GIPD221020141640FSR ID (A) 4 4V 5 10 VDS(V) 15 Figure 6: Normalized VBR(DSS)vs. temperature GIPD180920141448FSR V (BR)DSS (norm) 1.08 0 0 2 4 6 8 VGS(V) Figure 7: Static drain-source on-resistance GADG300420171114FSR RDS(on) () VGS= 10V 0.34 ID= 1m A 1.04 0.33 1.00 0.32 0.96 0.31 0.92 0.88 -75 6/12 -25 25 75 125 T j(C) 0.30 0 DocID030485 Rev 1 2 4 6 8 10 ID(A) STFU16N65M2 Electrical characteristics Figure 8: Gate charge vs. gate-source voltage GIPD221020141708FSR VDS (V) VGS (V) VDS VDD = 520 V ID = 11 A 10 500 8 Figure 9: Capacitance variations GIPD221020141716FSR C (pF) Ciss 1000 400 100 6 300 4 200 Coss 10 Crss 2 100 0 0 4 8 12 16 20 0 Qg(nC) Figure 10: Normalized gate threshold voltage vs. temperature 1 0.1 0.1 1 10 100 VDS(V) Figure 11: Normalized on-resistance vs. temperature GIPD180920141442FSR V GS(th) (norm) ID = 250 A 1.1 1.0 0.9 0.8 0.7 0.6 -75 -25 25 75 125 T j(C) Figure 12: Source-drain diode forward characteristics GIPD221020141733FSR VSD (V) 1.1 Figure 13: Output capacitance stored energy GIPD221020141721FSR E (J) 5 Tj= -50C 1 4 0.9 Tj= 25C 3 0.8 2 Tj= 150C 0.7 1 0.6 0.5 0 0 2 4 6 8 10 ISD(A) 0 DocID030485 Rev 1 100 200 300 400 500 600 VDS(V) 7/12 Test circuits 3 8/12 STFU16N65M2 Test circuits Figure 14: Test circuit for resistive load switching times Figure 15: Test circuit for gate charge behavior Figure 16: Test circuit for inductive load switching and diode recovery times Figure 17: Unclamped inductive load test circuit Figure 18: Unclamped inductive waveform Figure 19: Switching time waveform DocID030485 Rev 1 STFU16N65M2 4 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK (R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. 4.1 TO-220FP ultra narrow leads package information Figure 20: TO-220FP ultra narrow leads package outline 8576148_1 DocID030485 Rev 1 9/12 Package mechanical data STFU16N65M2 Table 9: TO-220FP ultra narrow leads mechanical data mm Dim. Min. 10/12 Typ. Max. A 4.40 4.60 B 2.50 2.70 D 2.50 2.75 E 0.45 0.60 F 0.65 0.75 F1 - 0.90 G 4.95 5.20 G1 2.40 H 10.00 10.40 L2 15.10 15.90 L3 28.50 30.50 L4 10.20 11.00 L5 2.50 3.10 L6 15.60 16.40 L7 9.00 9.30 L8 L9 3.20 3.60 - 1.30 Dia. 3.00 3.20 DocID030485 Rev 1 2.54 2.70 STFU16N65M2 5 Revision history Revision history Table 10: Document revision history Date Revision 03-Apr-2017 1 DocID030485 Rev 1 Changes Initial release 11/12 STFU16N65M2 IMPORTANT NOTICE - PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST's terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers' products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. (c) 2017 STMicroelectronics - All rights reserved 12/12 DocID030485 Rev 1