Semiconductor
MSC23B2321D-xxBS4/DS4
2,097, 152- word x 32- bit DY NAMIC RAM MO DULE : FAST PAGE MODE TY P E
This vers ion: Mar. 3. 1999
DESCRIPTION
The MSC23B2321D-xxBS4/DS4 is a fully decoded, 2,097,152-word x 32-bit CMOS dynamic random access
m em ory modul e com posed of f our 16Mb DRAMs in SO J packages m ounted with ei ght dec oupli ng capac it ors on a
72-pin glass epoxy single-inline package. This module supports any application where high density and large
capacity of stor age memory ar e r equired.
FEATURES
· 2, 097,152-word x 32- bit or ganizat ion
· 72-pin Single Inline Memory M odule
MSC23B2321D- xxBS4 : Gold tab
MSC23B2321D- xxDS4 : S older t ab
· Singl e +5V supply ± 10% tol er anc e
· I nput : T TL compatible
· Output : TTL compatible, 3-state
· Refresh : 1024cycles/16ms
· / CA S befor e /RAS refr esh, hidden refresh, /RAS only refresh capability
· F ast page mode capability
PRODUCT FAMILY
Access Time (Max. ) Power Dissipat i on
Family tRAC tAA tCAC
Cycle
Time
(Min.) Operating (Max.) Standby (Max.)
MSC23B2321D-60BS4/DS4 60ns 30ns 15ns 110ns 1430mW
MSC23B2321D-70BS4/DS4 70ns 35ns 20ns 130ns 1320mW 22mW
Semiconductor MSC23B2321D
MODULE OUTLINE
1
72
R1.57
6.35
1.04Typ.
1.27±0.1
95.25
2.03Typ.
6.35Typ.
Typ.
6.35
Typ.
10.16
(
3.18
19.0±0.2
101.19Typ.
107.95±0.2*1
3.38Typ.
5.7Min.
9.3Max.
+0.1
-0.08
1.27
(Un i t : m m)
MSC23B2321D-xxBS4/DS4
*1 The common size difference of the board width 12.5mm of its height is specified as ±0.2.
The value above 12.5mm is specified as ±0.5.
Semiconductor MSC23B2321D
PIN C ONFIGURATI ON
Pin No. Pin Na me Pin No. Pin Na me Pin No. Pin Na me Pin No. Pin Na me
1V
SS 19 NC 37 NC 55 DQ11
2 DQ0 20 DQ4 38 NC 56 DQ27
3 DQ16 21 DQ20 39 VSS 57 DQ12
4 DQ1 22 DQ5 40 /CAS0 58 DQ28
5 DQ17 23 DQ21 41 /CAS2 59 VCC
6 DQ2 24 DQ6 42 /CAS3 60 DQ29
7 DQ18 25 DQ22 43 /CAS1 61 DQ13
8 DQ3 26 DQ7 44 /RAS0 62 DQ30
9 DQ19 27 DQ23 45 /RAS1 63 DQ14
10 VCC 28 A7 46 NC 64 DQ31
11 NC 29 NC 47 /WE 65 DQ15
12 A0 30 VCC 48 NC 66 NC
13 A1 31 A8 49 DQ8 67 PD1
14 A2 32 A9 50 DQ24 68 PD2
15 A3 33 /RAS3 51 DQ9 69 PD3
16 A4 34 /RAS2 52 DQ25 70 PD4
17 A5 35 NC 53 DQ10 71 NC
18 A6 36 NC 54 DQ26 72 VSS
Presence Det ect P ins
Pin No. Pin Na me MSC23B2321D
-60BS4/DS4 MSC23B2321D
-70BS4/DS4
67 PD1 NC NC
68 PD2 NC NC
69 PD3 NC VSS
70 PD4 NC NC
Semiconductor MSC23B2321D
BLOCK DIAGRAM
/WE
/CAS1
/CAS0
A0-A9
/CAS3
/CAS2
DQ0
A0-A9
/RAS
/LCAS
/UCAS
DQ1
DQ2
DQ3
/RAS1
V
CC
V
SS
C1-C8
SS
CC
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
A0-A9
/RAS
/LCAS
/UCAS
CC
/WE
/OE
SS
/RAS0
/RAS2
/RAS3
DQ16
A0-A9
/RAS
/LCAS
/UCAS
DQ17
DQ18
DQ19
SS
CC
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
A0-A9
/RAS
/LCAS
/UCAS
CC
/WE
/OE
SS
Semiconductor MSC23B2321D
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter Symbol Rating Unit
Volt age on Any Pin Relat i ve to VSS VIN, VOUT -1.0 to +7.0 V
Vol t age on VCC Supply Relative to V SS VCC -1.0 to +7.0 V
Short Ci r cuit Output Current IOS 50 mA
Power Dissipation PD *4W
Operating Temperature TOPR 0 to +70 °C
Storage Temperature TSTG - 40 to +125 °C
* Ta = 25°C
Recommen ded O perating Conditions ( Ta = 0°C to +70°C )
Parameter Symbol Min. Typ. Max. Unit
VCC 4.5 5.0 5.5 V
Power Suppl y Volt age VSS 000V
Input High Volt age VIH 2.4 - 6.5 V
Input Low Vol tage VIL -1.0 - 0.8 V
Capacitance ( VCC = 5V ± 10%, Ta = 25°C, f = 1 MHz )
Parameter Symbol Typ. Max. Unit
Input Capacitance (A0 - A9) CIN1 -31pF
Input Capaci t ance (/WE) CIN2 -35pF
Input Capaci t ance (/RAS0- /RAS3) CIN3 -13pF
Input Capaci t ance (/CAS0- /CAS3) CIN4 -20pF
I/O Capacitance (DQ0 - DQ31) CDQ -20pF
Note: Capaci tance measured wi th Boonton M eter.
Semiconductor MSC23B2321D
DC Characteristics (VCC = 5V ± 10% , Ta = 0°C to +70°C )
MSC23B2321D
-60BS4/DS4 MSC23B2321D
-70BS4/DS4
Parameter Symbo
lCondition
Min. Max. Min. Max.
Unit Note
Input Leakage Current ILI
0V ≤ VIN ≤ 6.5V;
All ot her pins not
under test = 0V -40 40 -40 40 µA
Out put Leakage Current ILO DQ disable
0V ≤ VOUT ≤ 5.5V -20 20 -20 20 µA
Out put Hi gh Volt age VOH IOH = -5.0mA 2.4 VCC 2.4 VCC V
Out put Low Vol tage VOL IOL = 4.2mA 0 0.4 0 0.4 V
Average Power Suppl y Curr ent
(Operating) ICC1 /RAS, /CAS cycling,
tRC = min. - 260 - 240 mA 1, 2
/RAS, /CAS = VIH -8-8mA1
Power supply current
(Standby) ICC2 /RAS, /CAS
≥ VCC -0.2V -4-4mA1
Average Power Suppl y Curr ent
(/RAS only r efresh) ICC3
/RAS cy c lin g ,
/CAS = VIH,
tRC = min. - 260 - 240 mA 1, 2
Average Power Suppl y Curr ent
(/CAS before /RAS refresh) ICC6 /RAS cycli ng ,
/CAS before /RAS - 260 - 240 m A 1, 2
Average Power Suppl y Curr ent
(Fast Page Mode) ICC7
/RAS = VIL,
/CAS cy c lin g ,
tPC = m i n. - 260 - 240 mA 1, 3
Notes: 1. ICC Max. is specified as ICC for output open condition.
2. Address can be changed once or less whil e /RAS = VIL.
3. Address can be changed once or less whil e /CAS = VIH.
Semiconductor MSC23B2321D
AC Characteristics (1/2) (VCC = 5V ± 10% , Ta = 0°C to +70°C ) Note: 1, 2, 3
MSC23B2321D
-60BS4/DS4 MSC23B2321D
-70BS4/DS4
Parameter Symbol
Min. Max. Min. Max.
Unit Note
Random Read or Wr ite Cycle Time tRC 110 - 130 - ns
Fast Page Mode Cycle Time tPC 40 - 45 - ns
Access Time from /RAS tRAC - 60 - 70 ns 4, 5, 6
Access Time from /CAS tCAC - 15 - 20 ns 4, 5
Access Time from Colum n Address tAA - 30 - 35 ns 4, 6
Access Time from /CAS Precharge tCPA - 35 - 40 ns 4
Out put Low Impedance Tim e from /CAS t CLZ 0-0-ns4
/CAS to Data Output Buffer Turn-off Delay Time tOFF 0 15 0 20 ns 7
Transi tion Time tT3 50 3 50 ns 3
Refr esh Period tREF -16-16ms
/RAS Pr echarge Time tRP 40 - 50 - ns
/RAS Pulse Wi d th tRAS 60 10K 70 10K ns
/RAS Pulse Widt h ( Fast Page Mode) tRASP 60 100K 70 100K ns
/RAS Hold Time tRSH 15 - 20 - ns
/CAS Precharge Time (Fast Page Mode) tCP 10 - 10 - ns
/CAS Pulse Wi d th tCAS 15 10K 20 10K ns
/CAS Hold Time tCSH 60 - 70 - ns
/CAS t o /RAS Prechar ge Time tCRP 5-5-ns
/RAS Hold Time from /CAS Precharge tRHCP 35 - 40 - ns
/RAS to /CAS Delay Time tRCD 20 45 20 50 ns 5
/RAS to Column Address Delay Time tRAD 15 30 15 35 ns 6
Row Address Set-up Time tASR 0-0-ns
Row Address Hol d Ti me tRAH 10 - 10 - ns
Column Address Set-up Time tASC 0-0-ns
Col u mn Add ress Hol d Ti me tCAH 10 - 15 - ns
Column Address to /RAS Lead Time tRAL 30 - 35 - ns
Read Com mand Set-up Tim e tRCS 0-0-ns
Read Com mand Hold Time tRCH 0-0-ns8
Read Com mand Hold Time referenced t o / RAS tRRH 0-0-ns8
Semiconductor MSC23B2321D
AC Characteristics (2/2) (VCC = 5V ± 10% , Ta = 0°C to +70°C ) Note: 1, 2, 3
MSC23B2321D
-60BS4/DS4 MSC23B2321D
-70BS4/DS4
Parameter Symbol
Min. Max. Min. Max.
Unit Note
W r ite Command Set-up Time tWCS 0-0-ns
W r ite Command Hold Time t WCH 10 - 15 - ns
W r ite Command Pulse Wi dt h tWP 10 - 10 - ns
W r ite Command to / RAS Lead Ti me t RWL 15 - 20 - ns
W r ite Command to / CAS Lead Ti me t CWL 15 - 20 - ns
Data-i n Set-up Time tDS 0-0-ns
Dat a-i n Ho ld Time t DH 10 - 15 - ns
/CAS Active Delay Time from /RAS Precharge tRPC 5-5-ns
/RAS to /CAS Set-up Time
(/ CAS b efore /RAS) tCSR 10 - 10 - ns
/RAS to /CAS Hold Tim e
(/ CAS b efore /RAS) tCHR 10 - 10 - ns
Semiconductor MSC23B2321D
Notes: 1. A start- up delay of 200µs is required after power-up, followed by a mi nimum of eight ini tializ ation cycles
(/RA S only refr esh or / CA S befor e /RAS refr esh) before pr oper devic e oper ation is achieved.
2. The AC c har ac teri stics assumes tT = 5ns.
3. VIH(Min. ) and VIL(Max .) are ref erence l ev els for measuring input timi ng signals. Transiti on ti me (tT) are
m easured bet ween VIH and VIL.
4. This parameter i s measured wi th a load c ircuit equivalent to 2TT L loads and 100pF.
5. Operation within the tRCD(M ax. ) li mit ensures that t RAC(Max . ) can be met.
tRCD(Max.) is s pecified as a reference point only . If tRCD is greater than the s pecified tRCD(Max.) limit, then
the acc ess ti me is controlled by tCAC.
6. Operation within the tRAD(Max.) li mit ensures that tRAC(Max . ) can be met.
tRAD(Max.) is s pecified as a reference point only. If tRAD is greater than the specified tRAD(Max.) limit, the n
the acc ess ti me is controlled by tAA.
7. tOFF(Max.) define the time at w hich the output achieves the open circuit condition and are not referenced
to out put voltage levels.
8. tRCH or tRRH must be satisfied for a read cycle.