UCD7230 www.ti.com SLUS741C - NOVEMBER 2006 - REVISED MARCH 2007 Digital Control Compatible Synchronous Buck Gate Drivers with Current Sense Conditioning Amplifier FEATURES APPLICATIONS * * * * * * * * * * * Input from Digital Controller Sets Operating Frequency and Duty Cycle Up to 2-MHz Switching Frequency Dual Current Limit Protection with Independently Adjustable Thresholds Fast Current Sense Circuit with Adjustable Blanking Interval Prevents Catastrophic Current Levels Digital Output Current Limit Flag Low Offset, Gain of 48, Differential Current Sense Amplifier 3.3-V, 10-mA Internal Regulator Dual TrueDriveTM High-Current Drivers 10-ns Typical Rise/Fall Times with 2.2-nF Loads 4.5-V to 15.5-V Supply Voltage Range * * * Digitally-Controlled Synchronous-Buck Power Stages for Single and Multi-Phase Applications Especially Suited for Use with UCD91xx or UCD95xx Contollers High-Current Multi-Phase VRM/EVRD Regulators for Desktop, Server, Telecom and Notebook Processors Digitally-Controlled Synchronous-Buck Power Supplies Using Cs or the TMS320TM DSP Family DESCRIPTION The UCD7230 is part of the UCD7K family of digital control compatible drivers for applications utilizing digital control techniques or applications requiring fast local peak current limit protection. VOUT VIN CS BIAS VDD CS+ BST OUT1 SW PVDD OUT2 PGND + IO UVLO + IDLY 0.6 V POS BIAS 3V3 3V3 REG 48x NEG + Drive and Dead-Time ControlLogic (D;1-D) Enable Blank AGND I MAX AO ILOAD IN PWM Over Current ILIM SRE Current Limit Logic ILIM/10 IDLY SRE DLY CLF CLF UCD7230 + Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. TrueDrive, PowerPAD are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2006-2007, Texas Instruments Incorporated UCD7230 www.ti.com SLUS741C - NOVEMBER 2006 - REVISED MARCH 2007 The UCD7230 is a MOSFET gate driver specifically designed for synchronous buck applications. It is ideally suited to provide the bridge between digital controllers such as the UCD91xx or the UCD95xx and the power stage. With cycle-by-cycle current limit protection, the UCD7230 device protects the power stage from faulty input signals or excessive load currents. The UCD7230 includes high-side and low-side gate drivers which utilize Texas Instrument's TrueDriveTM output architecture. This architecture delivers rated current into the gate capacitance of a MOSFET during the Miller plateau region of the switching. Furthermore, the UCD7230 offers a low offset differential amplifier with a fixed gain of 48. This amplifier greatly simplifies the task of conditioning small current sense signals inherent in high efficiency buck converters. The UCD7230 includes a 3.3-V, 10-mA linear regulator to provide power to digital controllers such as the UCD91xx. The UCD7230 is compatible with standard 3.3-V I/O ports of the UCD91xx, the TMS320TM family DSPs, Cs, or ASICs. The UCD7230 is offered in PowerPADTM HTSSOP or space-saving QFN packages. Package pin out has been carefully designed for optimal board layout SIMPLIFIED APPLICATION DIAGRAMS VIN UCD7230 UCD9112 ADC3 2 RB0 DPWMA0 1 VDD CS+ 20 2 SRE CSBIAS 19 3 SW 18 AD33 4 3V3 AVSS 5 VD25 2 IN 2 AGND VOUT OUT1 17 BST 16 6 DLY PVDD 15 7 ILIM OUT2 14 8 CLF PGND 13 RPOS GSENSE 1 EAP VOUT DPWMB0 RB1/TMRI1 9 EAM I0 NEG 12 RNEG 1 GSENSE 10 A0 ADC2 POS 11 RST COMMUNICATION (Programming& StatusReporting) 2 Figure 1. Single-Phase Synchronous Buck Converter using UCD9112 and one UCD7230 2 UCD7230 www.ti.com SLUS741C - NOVEMBER 2006 - REVISED MARCH 2007 SIMPLIFIED APPLICATION DIAGRAMS (continued) VIN UCD7230PWP RB0 1 VDD UCD9112 2 RB0 ADC3 2 SRE DPWMA0 CSBIAS 19 3 IN 2 SW AD33 4 3V3 AVSS 5 VD25 CS+ 20 AGND 6 DLY 2 18 OUT1 17 VOUT RPOS1 BST 16 GSENSE PVDD 15 1 EAP VOUT DPWMB0 ILIM OUT2 14 8 CLF PGND 13 7 RB1/TMRI1 RNEG1 9 EAM I0 NEG 12 1 GSENSE 10 A0 ADC2 POS 11 RST UCD7230PWP 1 VDD 2 RB0 2 SRE 3 IN DPWMA1 COMMUNICATION (Programming& StatusReporting) 4 3V3 5 AGND 6 DLY 2 CSBIAS 19 2 SW 18 OUT1 17 RPOS2 BST 16 PVDD 15 ILIM OUT2 14 8 CLF PGND 13 7 DPWMB1 RB3/TMRI0 CS+ 20 RNEG2 9 I0 10 A0 ADC5 NEG 12 1 POS 11 2 Figure 2. Multi-Phase Synchronous Buck Converter using UCD9112 and two UCD7230 3 UCD7230 www.ti.com SLUS741C - NOVEMBER 2006 - REVISED MARCH 2007 SRE CSBIAS 19 3 IN SW 18 6 DLY 7 ILIM 8 CLF 9 10 UCD7230 (HTSSOP) BST 16 PVDD 15 OUT2 14 PGND 13 I0 NEG 12 A0 POS 11 AGND 2 DLY 3 ILIM 4 CLF 17 16 15 SW UCD7230 (QFN RGW) (5x5, 0.65) 14 OUT1 13 BST 12 PVDD 5 11 OUT2 6 7 8 9 NEG AGND 17 18 POS 5 OUT1 19 A0 3V3 1 I0 4 20 3V3 CSBIAS 2 10 PGND 20 CS+ CS+ VDD VDD IN 1 SRE CONNECTION DIAGRAMS ORDERING INFORMATION (1) (2) TEMPERATURE RANGE -40C to + 125C (1) (2) 4 PACKAGED DEVICES PowerPADTM HTSSOP-20 (PWP) QFN-20 (RGW) UCD7230PWP UCD7230RGW These products are packaged in Pb-Free and green lead finish of Pd-Ni-Au which is compatible with MSL level 1 at 255-260C peak reflow temperature to be compatible with either lead free or Sn/Pb soldering operations. HTSSOP-20 (PWP), and QFN-20 (RGW) packages are available taped and reeled. Add R suffix to device type (e.g. UCD7230PWPR) to order quantities of 2,000 devices per reel for the PWP package and 1,000 devices per reel for the RGW packages. UCD7230 www.ti.com SLUS741C - NOVEMBER 2006 - REVISED MARCH 2007 ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) PARAMETER VDD CONDITION 16 Supply voltage BST IDD Supply current VO Output gate drive voltage VALUE SW + 16 Quiescent 20 Switching, TA = 25C, VDD = 12 V 200 OUT1, BST OUT2 -1 V to 36 -1 V to VDD+0.3 IOUT(sink) OUT1 4.0 IOUT(source) OUT1 -2.0 OUT2 4.0 IOUT(sink) Output gate drive current IOUT(source) OUT2 Analog inputs -1 to 20 CS+ -0.3 to 20 CSBIAS -0.3 to 16 POS, NEG -0.3 to 5.6 ILIM, DLY, I0 -0.3 to 3.6 Analog output A0 -0.3 to 3.6 Digital I/O's IN, SRE, CLF -0.3 to 3.6 Power dissipation 2.67 TA = 25C (QFN-20 package) TJ Junction operating temperature -55 to 150 Tstg Storage temperature -65 to 150 HBM CDM ESD rating Lead temperature (soldering, 10 sec) (1) V mA VV A -4.0 SW TA = 25C (PWP-20 package) UNIT Human body model 2000 Charged device model 500 300 V W C V C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other condition beyond those indicated is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. All voltages are with respect to GND. Currents are positive into, negative out of the specified terminal. Consult company packaging information for thermal limitations and considerations of packages. 5 UCD7230 www.ti.com SLUS741C - NOVEMBER 2006 - REVISED MARCH 2007 ELECTRICAL CHARACTERISTICS VDD = PVDD = 12 V, 4.7-F from VDD to AGND, 1 F from PVDD to PGND, 0.1 F from CSBIAS to AGND, 0.22 F from BST to SW, TA = TJ = -40C to +125C, RCS+ = 5 k, RDLY = 50 k over operating free-air temperature range (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 500 700 A 5 8 mA SUPPLY Supply current, off VDD = 4.2 V Supply current Outputs not switching IN = LOW LOW-VOLTAGE UNDER-VOLTAGE LOCKOUT VDD UVLO ON VDD rising 4.25 4.50 4.75 VDD UVLO OFF VDD falling 4.00 4.25 4.50 100 250 400 3.267 3.3 3.333 3.234 3.3 3.366 VDD UVLO hysteresis V mV REFERENCE / EXTERNAL BIAS SUPPLY 3V3 initial set point TA = 25C 3V3 over temperature 3V3 load regulation ILOAD = 1 mA to 10 mA, VDD = 5V 1 7 3V3 line regulation VDD = 4.75 V to 12 V, ILOAD = 10 mA 3 10 Short circuit current VDD = 4.75 V to 12 V 11 3V3 OK threshold, ON 3.3 V rising 2.8 3 3.2 3V3 OK threshold, OFF 3.3 V falling 2.6 2.8 3.0 20 V mV mA V INPUT SIGNAL (IN) INHigh Positive-going input threshold voltage 1.6 1.9 2.2 INLow Negative-going input threshold voltage 1.0 1.3 1.6 INHigh - INLow Input voltage hysteresis 0.4 0.6 0.8 Input resistance to AGND 50 100 150 Frequency ceiling 2 V k MHz CURRENT LIMIT (ILIM) ILIM internal voltage setpoint ILIM=OPEN ILIM input impedance CLF output high level ILOAD = 4 mA CLF output low level ILOAD = 4 mA Propagation delay from IN to reset CLF 2nd IN rising to CLF falling after a current limit event 0.47 0.50 0.53 20 42 65 2.7 0.6 15 35 V k V ns CURRENT SENSE COMPARATOR (OUTPUT SENSE) CS threshold (POS - NEG) (1) 6 ILIM = open 40 50 60 ILIM = 3.3 V 80 100 120 ILIM = 0.75 V 60 75 90 ILIM = 0.25 V 15 25 35 Propagation delay from POS to OUT1 falling (1) ILIM = open, CS = threshold + 60 mV 90 Propagation delay from POS to CLF (1) ILIM = open, CS = threshold + 60 mV 100 mV ns As designed and characterized. Not 100% tested in production. UCD7230 www.ti.com SLUS741C - NOVEMBER 2006 - REVISED MARCH 2007 ELECTRICAL CHARACTERISTICS (continued) VDD = PVDD = 12 V, 4.7-F from VDD to AGND, 1 F from PVDD to PGND, 0.1 F from CSBIAS to AGND, 0.22 F from BST to SW, TA = TJ = -40C to +125C, RCS+ = 5 k, RDLY = 50 k over operating free-air temperature range (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX RDLY = 24.3 k (CSBIAS-CS+) 170 235 300 RDLY = 49.9 k (CSBIAS-CS+) 90 114 140 UNIT CURRENT SENSE COMPARATOR (INPUT SENSE) CS threshold CS blanking time (2) RDLY = 24.3 k , IN rising to OUT1, IN falling to OUT2, VDD = 6 V 120 RDLY = 49.9 k , IN rising to OUT1, IN falling to OUT2, VDD = 6 V 230 RDELAY range (2) Propagation delay from CS+ to OUT1 (2) Propagation delay from CS+ to CLF (2) mV ns 24.3 50.0 100.0 k 80 CS = threshold + 60mV ns 70 CURRENT SENSE AMP VOO Output offset voltage I0 = OPEN; POS = NEG = 1.25 V; measure AO - IO Closed loop dc gain -100 0 100 mV I0 = FLOAT; VPOS = 1.26 V; VNEG = 1.25 V, RPOS = RNEG = 0 46 48 50 V/V Input impedance POS = 1.25 V, NEG = 1.29 V,R = (POS - NEG) / (IPOS - INEG) 5.5 8.3 12 k VCM Input Common Mode Voltage Range VCM(max) is limited to (VDD-1.2V), RPOS = 0 5.6 V A0_Vol Minimum Output Voltage VPOS = 1.2 V; VNEG = 1.3 V; A0_ISINK = 250 A A0_Voh Maximum Output Voltage VPOS =1.3 V; VNEG = 1.2 V; A0_ ISOURCE = 500 A Input Bias Current, POS or NEG I0 = FLOAT; VPOS = VNEG = 0.8 V to 5.0 V, RPOS = RNEG = 0 0 0.15 0.3 3.1 3.5 V 3 -2 30 A ZERO CURRENT REFERENCE (IO) IO (2) Reference voltage Measured at I0 0.54 0.6 0.66 V Input transition voltage With respect to IO reference 10 60 120 mV Output impedance IZERO = 0.6 V 10 15 21 k As designed and characterized. Not 100% tested in production. 7 UCD7230 www.ti.com SLUS741C - NOVEMBER 2006 - REVISED MARCH 2007 ELECTRICAL CHARACTERISTICS (continued) VDD = PVDD = 12 V, 4.7-F from VDD to AGND, 1 F from PVDD to PGND, 0.1 F from CSBIAS to AGND, 0.22 F from BST to SW, TA = TJ = -40C to +125C, RCS+ = 5 k, RDLY = 50 k over operating free-air temperature range (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT LOW-SIDE OUTPUT DRIVER (OUT2) Source current (3) Sink current Source (3) current (3) Sink current VDD = 12 V, IN = high, OUT2 = 5 V 2.2 VDD = 12 V, IN = low, OUT2 = 5 V 3.5 VDD = 4.75 V, IN = high, OUT2 = 0 1.6 VDD = 4.75 V, IN = low, OUT2 = 4.75 V (3) A 2 Rise time (3) CLOAD = 2.2 nF, VDD = 12 V 15 Fall time (3) CLOAD = 2.2 nF, VDD = 12 V 15 Output with VDD <UVLO VDD = 1.0 V, Isink = 10 mA 0.8 Propagation delay from IN to OUT2 (3) CLOAD = 2.2 nF, IN rising, SW = 2.5 V, BST = PVDD = VDD = 12 V 30 VDD = 12 V, BST = 12 V IN = High, OUT1 = 5 V 1.7 VDD = 12 V, BST = 12 V IN = Low, OUT1 = 5 V 3.5 VDD = 4.75 V = BST = 4.75 V, IN = High, OUT1 = 0 1 ns 1.2 V ns HIGH-SIDE OUTPUT DRIVER (OUT1) Source current (3) Sink current (3) Source current Sink current (3) (3) Rise time (3) Fall time (3) Propagation delay from IN to OUT1 (3) (3) 8 A VDD = 4.75 V, BST = 4.75 V, IN = Low, OUT1 = 4.75 V 2.4 CLOAD = 2.2 nF OUT1 to SW, VDD = 12 V 20 CLOAD = 2.2 nF OUT1 to SW, VDD = 12 V 15 CLOAD = 2.2 nF, IN falling, SW = 2.5 V, BST = PVDD = VDD = 12 V 30 As designed and characterized. Not 100% tested in production. ns UCD7230 www.ti.com SLUS741C - NOVEMBER 2006 - REVISED MARCH 2007 DEVICE INFORMATION TERMINAL FUNCTIONS TERMINAL UCD7230 NAME I/O DESCRIPTION HTSSOP20 QFN-20 VDD 1 18 - Supply input pin to power the internal circuitry except the driver outputs. The UCD7230 accepts an input range of 4.5 V to 15.5 V. SRE 2 19 I Synchronous Rectifier Enable. The SRE pin is a high impedance digital input capable of accepting 3.3-V logic level signals, used to disable the synchronous rectifier switch. The synchronous rectifier is disabled when this signal is low. A Schmitt trigger input comparator desensitizes this pin from external noise. IN 3 20 I The IN pin is a high impedance digital input capable of accepting 3.3-V logic level signals up to 2 MHz. A Schmitt trigger input comparator desensitizes this pin from external noise. 3V3 4 1 O Regulated 3.3-V rail. The onboard linear voltage regulator is capable of sourcing up to 10 mA of current. Bypass with 0.22-F ceramic capacitance from this pin to analog ground, AGND. AGND 5 2 - Analog ground return. DLY 6 3 I Requires a resistor to AGND for setting the current sense blanking time for both the high-side and low-side current sense comparators. The value of this resistor in conjunction with the resistor in series with the CS+ pin sets the high side current sense threshold. ILIM 7 4 I Output current limit threshold set pin. The output current threshold is 1/10th of the value set on this pin. If left floating the voltage on this pin is 0.55 V. The voltage on the ILIM pin can range from 0.25 V to 1V to set the threshold from 25 mV to 100 mV. CLF 8 5 O Current Limit Flag. The CLF signal is a 3.3-V digital output which is latched high after an over current event, triggered by either of the two current sense comparators and reset after two rising edges received on the IN pin. IO 9 6 I Sets the current sense linear amplifier "Zero" output level. The default value is 0.6 V which allows negative current measurement. AO 10 7 O Current sense linear amplifier output. The output voltage level on this pin represents the average output current. Any value below the level on the I0 pin represents negative output current. POS 11 8 I Non-inverting input of the output current sense amplifier and current limit comparator. NEG 12 9 I Inverting input of the output current sense amplifier and current limit comparator. PGND 13 10 - Power ground return. This pin should be connected close to the source of the low-side synchronous rectifier MOSFET. OUT2 14 11 I The low-side high-current TrueDriveTM driver output. Drives the gate of the low-side synchronous MOSFET between PVDD and PGND. PVDD 15 12 - Supply pin provides power for the output drivers. It is not connected internally to the VDD supply rail. The bypass capacitor for this pin should be returned to PGND. BST 16 13 I Floating OUT1 driver supply powered by an external Schottky diode from the PVDD pin during the synchronous MOSFET on time. OUT1 17 14 I The high-side high-current TrueDriveTM driver output. Drives the gate of the high-side buck MOSFET between SW and BST. SW 18 15 I/O CSBIAS 19 16 I Supply pin for the high-side current sense comparator. CS+ 20 17 I Non-inverting Input for the high side current sense comparator. A resistor connected between this pin and the high side MOSFET drain, in conjunction with the DLY resistor sets the high-side current limit threshold. OUT1 gate drive return and square wave input to output inductor. 9 UCD7230 www.ti.com SLUS741C - NOVEMBER 2006 - REVISED MARCH 2007 APPLICATION INFORMATION Introduction The UCD7230 is a synchronous buck driver with peak-current limiting. It is a member of the UCD7K family of digital compatible drivers suitable either for applications utilizing digital control techniques or analog applications that require local fast peak current limit protection. In systems using the UCD7230, the feedback loop is closed externally and the IN signal represents the PWM information required to regulate the output voltage. The PWM signal may be implemented by either a digital or analog controller. The UCD7230 has two over-current protection features, one that limits the peak current in the high-side switch and one that limits the output current. Both limits are individually programmable. The internal current sense blanking enables ease of design with real-world signals. In addition to over current limit protection, current sense signals can be conditioned by the on board amplifier for use by the system controller. Supply Requirements The UCD7230 operates on a supply range of 4.5 V to 15.5 V. The supply voltage should be applied to three pins, PVDD, VDD, and CSBIAS. PVDD is the supply pin for the lower driver, and has the greatest current demands. The supply connection to PVDD is also the point where an external Schottky diode provides current to the high side flying driver. PVDD should be bypassed to PGND with a low ESR ceramic capacitor. In the same fashion, the flying driver should be bypassed between BST and SW. VDD and CSBIAS are less demanding supply pins, and should be resistively coupled to the supply voltage for isolation from noise generated by high current switching and parasitic board inductance. Use 33 for CSBIAS and 1 for VDD. VDD should be bypassed to AGND with a 4.7-F ceramic capacitor while CSBIAS should be bypassed to AGND with 0.1 F. Although the three supply pins are not internally connected, they must be biased to the same voltage. It is important that all bypassing be done with low parasitic inductance techniques to good ground planes. PGND and AGND are the ground return connections to the chip. Ground plane construction should be used for both pins. For a MOSFET driver operating at high frequency, it is critical to minimize the stray inductance to minimize overshoot, undershoot, and ringing. The low output impedance of the drivers produces waveforms with high di/dt. This induces ringing in the parasitic inductances. It is highly desirable that the UCD7230 and the MOSFETs be collocated. PGND and the AGND pins should be connected to the PowerPADTM of the package with two thin traces. It is critical to ensure that the voltage potential between these two pins does not exceed 0.3 V. Although quiescent VDD current is low, total supply current depends on the gate drive output current required for the capacitive load and the switching frequency. Total supply current is the sum of quiescent VDD current and the average OUT current. Knowing the operating frequency and the MOSFET gate charge (Qg), average OUT current can be calculated from (IOUT = Qg x f), where f is the operating frequency. Reference / External Bias Supply The UCD7230 includes a series pass regulator to provide a regulated 3.3 V at the 3V3 pin that can be used to power other circuits such as the UCD91xx, a microcontroller or an ASIC. 3V3 can source 10 mA of current. For normal operation, place a 0.22-F ceramic capacitor between 3V3 and AGND. Control Inputs IN and SRE are high impedance digital inputs designed for 3.3-V logic-level signals. They both have 100-k pull-down resistors. Schmitt Trigger input stage design immunizes the internal circuitry from external noise. IN is the command input for the upper driver, OUT1, and can function up to 2 MHz. SRE controls the function of the lower driver, OUT2. When SRE is false (low), OUT2 is held low. When SRE is true, OUT2 is inverted from OUT1 with appropriate delays that preclude cross conduction in the Buck MOSFETs. 10 UCD7230 www.ti.com SLUS741C - NOVEMBER 2006 - REVISED MARCH 2007 APPLICATION INFORMATION (continued) Driver Stages The driver outputs utilize Texas Instruments' TrueDriveTM architecture, which delivers rated current into the gate of a MOSFET when it is most needed, during the Miller plateau region of the switching transition. This provides best switching speeds and reduces switching losses. TrueDriveTM consists of pull-up/ pull-down circuits using bipolar and MOSFET transistors in parallel. This hybrid output stage also allows relatively constant current sourcing even at reduced supply voltages. The low-side high-current output stage of the UCD7230 device is capable of sourcing 1.7-A and sinking 3.5-A current pulses and swings from PVDD to PGND. The high-side floating output driver is capable of sourcing 2.2-A and sinking 3.5-A peak-current pulses. This ratio of gate currents, common to synchronous buck applications, minimizes the possibility of parasitic turn on of the low-side power MOSFET due to dv/dt currents during the rising edge switching transition. See the typical curves of sink and source current in Figure 3 and Figure 4 below. If further limiting of the rise or fall times to the power device is desired, an external resistance can be added between the output of the driver and the power MOSFET gate. The external resistor also helps remove power dissipation from the driver. Driver outputs follow IN and SRE as previously described provided that VDD and 3V3 are above their respective under-voltage lockout thresholds. When the supplies are insufficient, the chip holds both OUT1 and OUT2 low. It is worth reiterating the need mentioned in the supply section for sound high frequency design techniques in the circuit board layout and bypass capacitor selection and placement. Some applications may generate excessive ringing at the switch-inductor node. This ringing can drag SW to negative voltages that might cause functional irregularities. To prevent this, carefull board layout and appropriate snubbing are essential. In addition, it may be appropriate to couple SW to the inductor with a 1- resistor, and then bypass SW to PGND with a low impedance Schottky diode. OUT1 SOURCE/SINK CURRENT vs OUT1 VOLTAGE WITH RESPECT TO SW VOLTAGE OUT2 SOURCE/SINK CURRENT vs OUT2 VOLTAGE 5.0 ISOURCE/ISINK - Source Current/Sink Current - A ISOURCE/ISINK - Source Current/Sink Current - A 5.0 4.5 Sink Current VDD = 12 V 4.0 3.5 Source Current VDD = 12 V 3.0 Sink Current VDD = 5 V 2.5 2.0 1.5 Source Current VDD = 5 V 1.0 0.5 Source Current VDD = 12 V 4.5 4.0 Sink Current VDD = 12 V 3.5 3.0 2.5 2.0 Sink Current VDD = 5 V 1.5 Source Current VDD = 5 V 1.0 0.5 0 0 0 1 2 3 OUT1 - SW - V Figure 3. 4 5 6 0 1 2 3 4 5 6 OUT2 - V Figure 4. 11 UCD7230 www.ti.com SLUS741C - NOVEMBER 2006 - REVISED MARCH 2007 APPLICATION INFORMATION (continued) Current Sensing and Overload Protection Since the UCD7230 is physically collocated with the high-current elements of the power converter, it is logical that current be monitored by the chip. An internal instrumentation amplifier conditions current sense signals so that they can be used by the control chip generating the PWM signal. POS and NEG are inputs to an instrumentation amplifier circuit. This amplifier has a nominal gain of 48 and presents its output at AO. This can be used to monitor either an external current sense shunt or a parallel RC around the buck inductor shown in Figure 5. The shunt yields the highest accuracy and will be insensitive to inductor core saturation effects. It comes with the price of added power dissipation. Using the shunt, AO is given by: AO = ( 48 I OUT RSHUNT ) + IO The internal configuration of the instrumentation amplifier is such that AO is 0.6 V when POS - NEG = 0. Because of this output offset, the amplifier can accurately pass information for both positive and negative load current. The offset is controlled by IO. If IO is left to float, the offset is 0.6 V. 0.6 V is present at IO through an internal 10-k resistor and should be bypassed to AGND. If a higher value of offset is desired, a voltage in excess of 0.66 V can be externally applied to IO. Once IO is forced above 0.66 V, the internal 10 k is disconnected, and the AO output offset is now equal to the voltage applied to IO. + I0 SW SW + I0 8.33k RPOS L 8.33k 400k CurrentSenseAmp L + R CurrentSenseAmp + C + RNEG RSHUNT 8.33k NEG 400k AO 400k NEG COUT IO Buffer Amp POS IO Buffer Amp POS 8.33k 400k VOUT AO VOUT COUT Figure 5. Current Sense Using External Shunt and Lossless Average Output Current Sensing Using DC Resistance of the Output Inductor. Figure 5 also shows lossless current sensing utilizing an RC across the buck inductor to generate an analog of the IR drop on the copper of the inductor. As long as the RPOS x C time constant is the same as the L/R of the inductor and its parasitic equivalent series resistance, then the voltage on C is the same as the IR drop on the parasitic inductor resistance. A resistor, RNEG = RPOS is used for amplifier bias current cancellation. The transfer function of the amplifier is given by: AO = ( A I OUT RCOPPER ) + IO 12 UCD7230 www.ti.com SLUS741C - NOVEMBER 2006 - REVISED MARCH 2007 APPLICATION INFORMATION (continued) With the addition of RPOS and RNEG, the natural gain, A, of the current sense is predictably decreased as: A= 48 ae RPOS o 1+ c / e 8.33 k W o For RPOS << 8.33 k, the gain is 48. While the 400 k and 8.33 k are well matched, it is important to keep RPOS as small as possible since they have absolute variation from chip-to-chip and over temperature. The graph in Figure 6 shows the band of expected gain for A as a function of RPOS. The gain variation at RPOS = 1 k results in around 4% error. However, the tolerance of the value of R in the inductor has a more significant effect on measurement accuracy as does the temperature coefficient of R. Copper has a temperature coefficient of approximately 3800 ppm/C. For a 100C rise in winding temperature, the dc resistance of the inductor increases by 38%. The worst case scenario would be a cracked core or under-designed inductor in which cases the core could tend towards saturation. In that scenario, inductor current could change slope drastically and is not correctly modeled by the capacitor voltage. Note that inferring inductor current by use of a parallel RC has an additional caveat. As long as TRC = RPOS C is the same as TLR = L/R, then the voltage across C is the same as the IR drop across the equivalent R of the inductor. If the time constants don't match, the average voltage across C is still the same as the average voltage across R, but the indication of ripple current amplitude will be off. Furthermore, load transients results in reported current that appears to have overshoot or undershoot if TRC is respectively faster or slower than TLR. While the amp faithfully passes the sensed dc current signal, it should be noted that the amplifier is bandwidth limited for normal switching frequencies. Therefore, AO represents a moving average of the sensed current. Current Sense AMP Gain vs RPOS 49 48 47 Maximum Gain Corner (minimum sheet and Cold temperature) 46 Amp Gain - V/V 45 44 43 42 41 Normal Gain 40 39 38 Minimum Gain Corner (minimum sheet and hot temperature) 37 36 35 0 500 1000 1500 2000 RPOS - W Figure 6. Current Sense Amp Gain as a Function of RPOS 13 UCD7230 www.ti.com SLUS741C - NOVEMBER 2006 - REVISED MARCH 2007 APPLICATION INFORMATION (continued) The amp output can go up to 3.3 V, so reasonable designs limits full scale to 3.0 V. Should attenuation be necessary, use a resistive divider between AO and the control chip A/D input as shown in Figure 7. To A/D A0 Figure 7. Attenuating and Filtering the Voltage Representation of the Average Output Current While the current sense amplifier is useful for accurate current monitoring or controlling overload conditions, extreme overload conditions must be handled in timeframes that are generally much shorter than the A/D of a control chip can achieve. Therefore, there are two comparators on the UCD7230 to sense extreme overload and protect the driven power MOSFETs. Extreme current overload is handled in two ways by the UCD7230. One is a comparator that monitors the voltage between POS and NEG, or effectively the output current of the converter.. The other is a comparator that monitors the voltage drop across the high-side MOSFET, or effectively the input current. Should either condition exceed a preset value, OUT1 is immediately turned off for the remainder of the cycle. To program the current limit, a value of resistance from DLY to AGND must first be chosen to establish a blanking time during which the comparators will be blinded to switching noise. The blanking time starts with the rising edge on IN for the input comparator and from both the rising and falling edge of IN for the output comparator. Blanking time is given by: t BLANK ( ns ) 5 RDLY ( k W ) where RDLY is the resistor from DLY to AGND. RDLY should be limited to a range of 25 k to 100 k. Once RDLY has been chosen, the threshold for the input comparator, i.e., the drop allowed across the high-side MOSFET, is given by: aeR o VCS ( in ) = 1.2 c CS + / e RDLY o Where VCS(in) is the threshold of allowed voltage across the high-side MOSFET and RCS+ is a resistor connected from CS+ to the drain of the high-side MOSFET. The blanking time for the output comparator is identical to the input comparator. The output comparator threshold is given by: VCS ( out ) = I LIM 10 where VCS(out) is the threshold of allowed voltage between the POS and NEG pins and ILIM is the voltage on the ILIM pin. Note that the ILIM is internally connected to 0.5 V through a 42 k resistor. Any voltage between 0.25 V and 1.0 V can be applied to ILIM. For voltages above 1.0 V, the maximum VCS(OUT) threshold is clamped to 0.1 V. Possible methods for setting ILIM are shown in Figure 8. When using the output comparator to monitor the voltage on the parallel sensing capacitor across the inductor, the same caveats apply as described for the current sense amplifier. 14 UCD7230 www.ti.com SLUS741C - NOVEMBER 2006 - REVISED MARCH 2007 APPLICATION INFORMATION (continued) A) GPIO Outputs DIGITAL CONTROLLER UCD7230 VCC 3V3 GND AGND 40 kW ILIM GPIO1 20 kW GPIO2 ILIM SETPOINT [Volts] ILIM (open) 0.50 ILIM0 0.00 ILIM1 0.14 ILIM2 0.29 ILIM3 0.43 ILIM4 0.57 ILIM5 0.72 ILIM6 0.86 ILIM7 1.00 10 kW GPIO3 2.5 kW GPIO4 B) PWM Output DIGITAL CONTROLLER VCC GPIO2 OPEN 0 0 1 1 0 0 1 1 GPIO1 OPEN 0 1 0 1 0 1 0 1 GPIO4 OPEN 0 0 0 0 0 0 0 0 UCD7230 3V3 GND AGND Cf Rf ILIM PWM C) Resistor Divider GPIO3 OPEN 0 0 0 0 1 1 1 1 Rf and Cf filter the PWM output to generate a DC input to the ILIM PIN DIGITAL CONTROLLER UCD7230 VCC 3V3 GND AGND R1 R2 ILIM D) Internal Set Point UCD7230 3V3 AGND Cf ILIM Figure 8. Setting the ILIM Voltage with: a) GPIO Outputs, b) PWM Output, c) Resistor Divider, d) Internal Set Point 15 UCD7230 www.ti.com SLUS741C - NOVEMBER 2006 - REVISED MARCH 2007 APPLICATION INFORMATION (continued) If either comparator threshold is exceeded, OUT1 is immediately turned off for the remainder of the cycle and CLF is asserted true. Upon the rising edge of IN, the switches resume normal operation, but the CLF assertion is maintained. If a fault is not detected in this switching cycle, then the next rising edge of IN removes the CLF assertion. However, if one of the comparators detects a fault, then CLF assertion continues. It is the privilege of the control device to monitor CLF and decide how to handle the fault condition. In the mean while, the protection comparators protect the power MOSFET switches on a cycle-by-cycle basis. If the output-sense comparator (POS - NEG) detects continuous over-current, then the driver assumes 0% duty cycle until the current drops to a safe value. Note that when a fault condition causes OUT1 to be driven low, OUT2 behaves as if the input pulse had been terminated normally. In some fault conditions, it is advantageous to drive OUT2 low. SRE can be used to cause OUT2 to remain low at the discretion of the control chip. This can be used to achieve faster discharge of the inductor and also to fully disconnect the converter from the output voltage. Startup Handshaking The UCD7230 has a built-in handshaking feature to facilitate efficient start-up of the digitally controlled power supply. At start-up the CLF flag is held high until all the internal and external supply voltages of the device are within their operating range. Once the supply voltages are within acceptable limits, CLF goes low and the device will process input commands. The digital controller should monitor CLF at start-up and wait for CLF to go low before sending pwm information to the UCD7230. Thermal Management The usefulness of a driver is greatly affected by the drive power requirements of the load and the thermal characteristics of the device package. In order for a power driver to be used over a particular temperature range, the package must allow for the efficient removal of the heat while keeping the junction temperature within rated limits. The UCD7230 is available in PowerPADTM HTSSOP and QFN packages to cover a range of application requirements. Both have the exposed pads to remove thermal energy from the semiconductor junction. As illustrated in Reference [3 & 4], the PowerPADTM packages offer a lead-frame die pad that is exposed at the base of the package. This pad is soldered to the copper on the PC board (PCB) directly underneath the device package, reducing the JA down to 38C/W. The PC board must be designed with thermal lands and thermal vias to complete the heat removal subsystem, as summarized in Reference [3]. Note that the PowerPADTM is not directly connected to any leads of the package. However, it is electrically and thermally connected to the substrate which is the ground of the device. The PowerPADTM should be connected to the quiet ground of the circuit. REFERENCES 1. Power Supply Seminar SEM-1600 Topic 6: A Practical Introduction to Digital Power Supply Control, by Laszlo Balogh, Texas Instruments Literature No. SLUP224 2. Power Supply Seminar SEM-1400 Topic 2: Design and Application Guide for High Speed MOSFET Gate Drive Circuits, by Laszlo Balogh, Texas Instruments Literature No. SLUP133. 3. Technical Brief, PowerPad Thermally Enhanced Package, Texas Instruments Literature No. SLMA002 4. Application Brief, PowerPADTM Made Easy, Texas Instruments Literature No. SLMA004 RELATED PRODUCTS RELATED PRODUCTS PRODUCT DESCRIPTION UCD9501 Digital power controller for high performance multi-loop applications UCD9111 Digital power controller for power supply applications UCD9112 Digital power controller for power supply applications 16 FEATURES PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel Diameter Width (mm) W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) UCD7230PWPR HTSSOP PWP 20 2000 330.0 UCD7230RGWR QFN RGW 20 3000 UCD7230RGWT QFN RGW 20 250 16.4 6.95 7.1 1.6 8.0 16.0 Q1 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 180.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 Pack Materials-Page 1 W Pin1 (mm) Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) UCD7230PWPR HTSSOP PWP 20 2000 346.0 346.0 33.0 UCD7230RGWR QFN RGW 20 3000 346.0 346.0 29.0 UCD7230RGWT QFN RGW 20 250 190.5 212.7 31.8 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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